--- /dev/null
+From 9a6a2b96dfd8b01336f8519a5be7fb353cfa62fb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Sat, 14 Mar 2015 17:55:54 +0100
+Subject: [PATCH] MIPS: BCM47XX: Support SPROM prefixes for PCI devices
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Support parsing SPROMs with prefixes defined like devpath1=pci/1/1
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Patchwork: https://patchwork.linux-mips.org/patch/9552/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/sprom.c | 33 +++++++++++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c
+index 2eff7fe..eff9205 100644
+--- a/arch/mips/bcm47xx/sprom.c
++++ b/arch/mips/bcm47xx/sprom.c
+@@ -836,6 +836,38 @@ static int bcm47xx_get_sprom_ssb(struct ssb_bus *bus, struct ssb_sprom *out)
+ #endif
+
+ #if defined(CONFIG_BCM47XX_BCMA)
++/*
++ * Having many NVRAM entries for PCI devices led to repeating prefixes like
++ * pci/1/1/ all the time and wasting flash space. So at some point Broadcom
++ * decided to introduce prefixes like 0: 1: 2: etc.
++ * If we find e.g. devpath0=pci/2/1 or devpath0=pci/2/1/ we should use 0:
++ * instead of pci/2/1/.
++ */
++static void bcm47xx_sprom_apply_prefix_alias(char *prefix, size_t prefix_size)
++{
++ size_t prefix_len = strlen(prefix);
++ size_t short_len = prefix_len - 1;
++ char nvram_var[10];
++ char buf[20];
++ int i;
++
++ /* Passed prefix has to end with a slash */
++ if (prefix_len <= 0 || prefix[prefix_len - 1] != '/')
++ return;
++
++ for (i = 0; i < 3; i++) {
++ if (snprintf(nvram_var, sizeof(nvram_var), "devpath%d", i) <= 0)
++ continue;
++ if (bcm47xx_nvram_getenv(nvram_var, buf, sizeof(buf)) < 0)
++ continue;
++ if (!strcmp(buf, prefix) ||
++ (short_len && strlen(buf) == short_len && !strncmp(buf, prefix, short_len))) {
++ snprintf(prefix, prefix_size, "%d:", i);
++ return;
++ }
++ }
++}
++
+ static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out)
+ {
+ char prefix[10];
+@@ -847,6 +879,7 @@ static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out)
+ snprintf(prefix, sizeof(prefix), "pci/%u/%u/",
+ bus->host_pci->bus->number + 1,
+ PCI_SLOT(bus->host_pci->devfn));
++ bcm47xx_sprom_apply_prefix_alias(prefix, sizeof(prefix));
+ bcm47xx_fill_sprom(out, prefix, false);
+ return 0;
+ case BCMA_HOSTTYPE_SOC:
+--
+1.8.4.5
+
--- /dev/null
+From e0c3678ae640db049f738f30b5f23cde740799ac Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 1 Apr 2015 16:01:02 +0200
+Subject: [PATCH] MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Since the day of adding this code it was broken. We were iterating over
+a wrong array and checking for wrong NVRAM entry.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Patchwork: https://patchwork.linux-mips.org/patch/9654/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/board.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
+index b3ae068..3fd369d 100644
+--- a/arch/mips/bcm47xx/board.c
++++ b/arch/mips/bcm47xx/board.c
+@@ -247,8 +247,8 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
+ }
+
+ if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0 &&
+- bcm47xx_nvram_getenv("boardtype", buf2, sizeof(buf2)) >= 0) {
+- for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) {
++ bcm47xx_nvram_getenv("boardnum", buf2, sizeof(buf2)) >= 0) {
++ for (e2 = bcm47xx_board_list_hw_version_num; e2->value1; e2++) {
+ if (!strstarts(buf1, e2->value1) &&
+ !strcmp(buf2, e2->value2))
+ return &e2->board;
+--
+1.8.4.5
+
--- /dev/null
+From 23d2bc42aceb829eaf90c694941e4523c22865e8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 10 Dec 2014 11:49:53 +0100
+Subject: [PATCH] MIPS: BCM47XX: Use helpers for reading NVRAM content
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Also drop some unneeded memset-s.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/8661/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/nvram.c | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
+index c5c381c..5e4ae04 100644
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -91,7 +91,6 @@ static int nvram_find_and_copy(void __iomem *iobase, u32 lim)
+ return -ENXIO;
+
+ found:
+-
+ if (header->len > size)
+ pr_err("The nvram size accoridng to the header seems to be bigger than the partition on flash\n");
+ if (header->len > NVRAM_SPACE)
+@@ -101,10 +100,9 @@ found:
+ src = (u32 *) header;
+ dst = (u32 *) nvram_buf;
+ for (i = 0; i < sizeof(struct nvram_header); i += 4)
+- *dst++ = *src++;
++ *dst++ = __raw_readl(src++);
+ for (; i < header->len && i < NVRAM_SPACE && i < size; i += 4)
+- *dst++ = le32_to_cpu(*src++);
+- memset(dst, 0x0, NVRAM_SPACE - i);
++ *dst++ = readl(src++);
+
+ return 0;
+ }
+@@ -165,7 +163,6 @@ static int nvram_init(void)
+ err = mtd_read(mtd, from, len, &bytes_read, dst);
+ if (err)
+ return err;
+- memset(dst + bytes_read, 0x0, NVRAM_SPACE - bytes_read);
+
+ return 0;
+ }
+--
+1.8.4.5
+
--- /dev/null
+From 80aaaa8b93d860f828e2cf883f307894640765f0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 10 Dec 2014 11:49:54 +0100
+Subject: [PATCH] MIPS: BCM47XX: Use strnchr to avoid reading out of the buffer
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/8662/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/nvram.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
+index 5e4ae04..d805d8a 100644
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -175,7 +175,7 @@ static int nvram_init(void)
+ int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
+ {
+ char *var, *value, *end, *eq;
+- int err;
++ int data_left, err;
+
+ if (!name)
+ return -EINVAL;
+@@ -191,7 +191,9 @@ int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
+ end = nvram_buf + sizeof(nvram_buf) - 2;
+ end[0] = end[1] = '\0';
+ for (; *var; var = value + strlen(value) + 1) {
+- eq = strchr(var, '=');
++ data_left = end - var;
++
++ eq = strnchr(var, data_left, '=');
+ if (!eq)
+ break;
+ value = eq + 1;
+--
+1.8.4.5
+
--- /dev/null
+From 138173d4e826587da66c7d321da1a91283222536 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Mon, 1 Dec 2014 07:58:18 +0100
+Subject: [PATCH] MIPS: BCM47xx: Move NVRAM header to the include/linux/.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are two reasons for having this header in the common place:
+1) Simplifying drivers that read NVRAM entries. We will be able to
+ safely call bcm47xx_nvram_* functions without #ifdef-s.
+2) Getting NVRAM driver out of MIPS arch code. This is needed to support
+ BCM5301X arch which also requires this NVRAM driver. Patch for that
+ will follow once we get is reviewed.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
+Cc: linux-mips@linux-mips.org
+Cc: Arnd Bergmann <arnd@arndb.de>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: linux-soc@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/8619/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/board.c | 2 +-
+ arch/mips/bcm47xx/nvram.c | 2 +-
+ arch/mips/bcm47xx/setup.c | 1 -
+ arch/mips/bcm47xx/sprom.c | 1 -
+ arch/mips/bcm47xx/time.c | 1 -
+ arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 1 +
+ arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h | 21 -------------
+ drivers/bcma/driver_mips.c | 2 +-
+ drivers/net/ethernet/broadcom/b44.c | 2 +-
+ drivers/net/ethernet/broadcom/bgmac.c | 2 +-
+ drivers/ssb/driver_chipcommon_pmu.c | 2 +-
+ drivers/ssb/driver_mipscore.c | 2 +-
+ include/linux/bcm47xx_nvram.h | 34 ++++++++++++++++++++++
+ 13 files changed, 42 insertions(+), 31 deletions(-)
+ delete mode 100644 arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
+ create mode 100644 include/linux/bcm47xx_nvram.h
+
+diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
+index b3ae068..6e85130 100644
+--- a/arch/mips/bcm47xx/board.c
++++ b/arch/mips/bcm47xx/board.c
+@@ -1,8 +1,8 @@
+ #include <linux/errno.h>
+ #include <linux/export.h>
+ #include <linux/string.h>
++#include <bcm47xx.h>
+ #include <bcm47xx_board.h>
+-#include <bcm47xx_nvram.h>
+
+ struct bcm47xx_board_type {
+ const enum bcm47xx_board board;
+diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
+index d805d8a..7c77a88 100644
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -16,7 +16,7 @@
+ #include <linux/kernel.h>
+ #include <linux/string.h>
+ #include <linux/mtd/mtd.h>
+-#include <bcm47xx_nvram.h>
++#include <linux/bcm47xx_nvram.h>
+
+ #define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
+ #define NVRAM_SPACE 0x8000
+diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
+index e43b504..b26c9c2 100644
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -42,7 +42,6 @@
+ #include <asm/reboot.h>
+ #include <asm/time.h>
+ #include <bcm47xx.h>
+-#include <bcm47xx_nvram.h>
+ #include <bcm47xx_board.h>
+
+ union bcm47xx_bus bcm47xx_bus;
+diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c
+index eff9205..c114b02 100644
+--- a/arch/mips/bcm47xx/sprom.c
++++ b/arch/mips/bcm47xx/sprom.c
+@@ -27,7 +27,6 @@
+ */
+
+ #include <bcm47xx.h>
+-#include <bcm47xx_nvram.h>
+ #include <linux/if_ether.h>
+ #include <linux/etherdevice.h>
+
+diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c
+index 2c85d92..5b46510 100644
+--- a/arch/mips/bcm47xx/time.c
++++ b/arch/mips/bcm47xx/time.c
+@@ -27,7 +27,6 @@
+ #include <linux/ssb/ssb.h>
+ #include <asm/time.h>
+ #include <bcm47xx.h>
+-#include <bcm47xx_nvram.h>
+ #include <bcm47xx_board.h>
+
+ void __init plat_time_init(void)
+diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+index 7527c1d..8ed77f6 100644
+--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+@@ -22,6 +22,7 @@
+ #include <linux/ssb/ssb.h>
+ #include <linux/bcma/bcma.h>
+ #include <linux/bcma/bcma_soc.h>
++#include <linux/bcm47xx_nvram.h>
+
+ enum bcm47xx_bus_type {
+ #ifdef CONFIG_BCM47XX_SSB
+--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
+@@ -1,21 +1 @@
+-/*
+- * Copyright (C) 2005, Broadcom Corporation
+- * Copyright (C) 2006, Felix Fietkau <nbd@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- */
+-
+-#ifndef __BCM47XX_NVRAM_H
+-#define __BCM47XX_NVRAM_H
+-
+-#include <linux/types.h>
+-#include <linux/kernel.h>
+-
+-int bcm47xx_nvram_init_from_mem(u32 base, u32 lim);
+-int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);
+-int bcm47xx_nvram_gpio_pin(const char *name);
+-
+-#endif /* __BCM47XX_NVRAM_H */
++#include <linux/bcm47xx_nvram.h>
+diff --git a/drivers/bcma/driver_mips.c b/drivers/bcma/driver_mips.c
+index 04faf6d..24424f3 100644
+--- a/drivers/bcma/driver_mips.c
++++ b/drivers/bcma/driver_mips.c
+@@ -21,7 +21,7 @@
+ #include <linux/serial_reg.h>
+ #include <linux/time.h>
+ #ifdef CONFIG_BCM47XX
+-#include <bcm47xx_nvram.h>
++#include <linux/bcm47xx_nvram.h>
+ #endif
+
+ enum bcma_boot_dev {
+diff --git a/drivers/net/ethernet/broadcom/b44.c b/drivers/net/ethernet/broadcom/b44.c
+index bd5916a..77363d6 100644
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -400,7 +400,7 @@ static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
+ }
+
+ #ifdef CONFIG_BCM47XX
+-#include <bcm47xx_nvram.h>
++#include <linux/bcm47xx_nvram.h>
+ static void b44_wap54g10_workaround(struct b44 *bp)
+ {
+ char buf[20];
+diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
+index 0469f72..be059df 100644
+--- a/drivers/net/ethernet/broadcom/bgmac.c
++++ b/drivers/net/ethernet/broadcom/bgmac.c
+@@ -18,7 +18,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/platform_data/b53.h>
+-#include <bcm47xx_nvram.h>
++#include <linux/bcm47xx_nvram.h>
+
+ static const struct bcma_device_id bgmac_bcma_tbl[] = {
+ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
+diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c
+index 1173a09..0942841 100644
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -14,7 +14,7 @@
+ #include <linux/delay.h>
+ #include <linux/export.h>
+ #ifdef CONFIG_BCM47XX
+-#include <bcm47xx_nvram.h>
++#include <linux/bcm47xx_nvram.h>
+ #endif
+
+ #include "ssb_private.h"
+diff --git a/drivers/ssb/driver_mipscore.c b/drivers/ssb/driver_mipscore.c
+index 7b986f9..f87efef 100644
+--- a/drivers/ssb/driver_mipscore.c
++++ b/drivers/ssb/driver_mipscore.c
+@@ -16,7 +16,7 @@
+ #include <linux/serial_reg.h>
+ #include <linux/time.h>
+ #ifdef CONFIG_BCM47XX
+-#include <bcm47xx_nvram.h>
++#include <linux/bcm47xx_nvram.h>
+ #endif
+
+ #include "ssb_private.h"
+diff --git a/include/linux/bcm47xx_nvram.h b/include/linux/bcm47xx_nvram.h
+new file mode 100644
+index 0000000..b12b07e
+--- /dev/null
++++ b/include/linux/bcm47xx_nvram.h
+@@ -0,0 +1,34 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#ifndef __BCM47XX_NVRAM_H
++#define __BCM47XX_NVRAM_H
++
++#include <linux/types.h>
++#include <linux/kernel.h>
++
++#ifdef CONFIG_BCM47XX
++int bcm47xx_nvram_init_from_mem(u32 base, u32 lim);
++int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);
++int bcm47xx_nvram_gpio_pin(const char *name);
++#else
++static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim)
++{
++ return -ENOTSUPP;
++};
++static inline int bcm47xx_nvram_getenv(const char *name, char *val,
++ size_t val_len)
++{
++ return -ENOTSUPP;
++};
++static inline int bcm47xx_nvram_gpio_pin(const char *name)
++{
++ return -ENOTSUPP;
++};
++#endif
++
++#endif /* __BCM47XX_NVRAM_H */
+--
+1.8.4.5
+
--- /dev/null
+From d548ca6b0784a99f0fcae397f115823ccd0361a5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 10 Dec 2014 17:38:26 +0100
+Subject: [PATCH] MIPS: BCM47XX: Fix coding style to match kernel standards
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[ralf@linux-mips.org: Fixed conflicts.]
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
+Cc: linux-mips@linux-mips.org
+Cc: Paul Walmsley <paul@pwsan.com>
+Patchwork: https://patchwork.linux-mips.org/patch/8665/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/bcm47xx_private.h | 4 ++++
+ arch/mips/bcm47xx/board.c | 3 +--
+ arch/mips/bcm47xx/nvram.c | 25 ++++++++++++++-----------
+ arch/mips/bcm47xx/prom.c | 3 +--
+ arch/mips/bcm47xx/serial.c | 8 ++++----
+ arch/mips/bcm47xx/setup.c | 12 ++++++------
+ arch/mips/bcm47xx/sprom.c | 8 ++++----
+ arch/mips/bcm47xx/time.c | 1 -
+ 8 files changed, 34 insertions(+), 30 deletions(-)
+
+diff --git a/arch/mips/bcm47xx/bcm47xx_private.h b/arch/mips/bcm47xx/bcm47xx_private.h
+index ea909a5..41796be 100644
+--- a/arch/mips/bcm47xx/bcm47xx_private.h
++++ b/arch/mips/bcm47xx/bcm47xx_private.h
+@@ -1,6 +1,10 @@
+ #ifndef LINUX_BCM47XX_PRIVATE_H_
+ #define LINUX_BCM47XX_PRIVATE_H_
+
++#ifndef pr_fmt
++#define pr_fmt(fmt) "bcm47xx: " fmt
++#endif
++
+ #include <linux/kernel.h>
+
+ /* prom.c */
+diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
+index 6e85130..d4a5a51 100644
+--- a/arch/mips/bcm47xx/board.c
++++ b/arch/mips/bcm47xx/board.c
+@@ -330,9 +330,8 @@ void __init bcm47xx_board_detect(void)
+ err = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf));
+
+ /* init of nvram failed, probably too early now */
+- if (err == -ENXIO) {
++ if (err == -ENXIO)
+ return;
+- }
+
+ board_detected = bcm47xx_board_get_nvram();
+ bcm47xx_board.board = board_detected->board;
+diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
+index 7c77a88..6a97732 100644
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -18,8 +18,10 @@
+ #include <linux/mtd/mtd.h>
+ #include <linux/bcm47xx_nvram.h>
+
+-#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
+-#define NVRAM_SPACE 0x8000
++#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
++#define NVRAM_SPACE 0x8000
++#define NVRAM_MAX_GPIO_ENTRIES 32
++#define NVRAM_MAX_GPIO_VALUE_LEN 30
+
+ #define FLASH_MIN 0x00020000 /* Minimum flash size */
+
+@@ -97,8 +99,8 @@ found:
+ pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
+ header->len, NVRAM_SPACE);
+
+- src = (u32 *) header;
+- dst = (u32 *) nvram_buf;
++ src = (u32 *)header;
++ dst = (u32 *)nvram_buf;
+ for (i = 0; i < sizeof(struct nvram_header); i += 4)
+ *dst++ = __raw_readl(src++);
+ for (; i < header->len && i < NVRAM_SPACE && i < size; i += 4)
+@@ -189,7 +191,8 @@ int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
+ /* Look for name=value and return value */
+ var = &nvram_buf[sizeof(struct nvram_header)];
+ end = nvram_buf + sizeof(nvram_buf) - 2;
+- end[0] = end[1] = '\0';
++ end[0] = '\0';
++ end[1] = '\0';
+ for (; *var; var = value + strlen(value) + 1) {
+ data_left = end - var;
+
+@@ -197,11 +200,10 @@ int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
+ if (!eq)
+ break;
+ value = eq + 1;
+- if ((eq - var) == strlen(name) &&
+- strncmp(var, name, (eq - var)) == 0) {
++ if (eq - var == strlen(name) &&
++ strncmp(var, name, eq - var) == 0)
+ return snprintf(val, val_len, "%s", value);
+ }
+- }
+ return -ENOENT;
+ }
+ EXPORT_SYMBOL(bcm47xx_nvram_getenv);
+@@ -209,10 +211,11 @@ EXPORT_SYMBOL(bcm47xx_nvram_getenv);
+ int bcm47xx_nvram_gpio_pin(const char *name)
+ {
+ int i, err;
+- char nvram_var[10];
+- char buf[30];
++ char nvram_var[] = "gpioXX";
++ char buf[NVRAM_MAX_GPIO_VALUE_LEN];
+
+- for (i = 0; i < 32; i++) {
++ /* TODO: Optimize it to don't call getenv so many times */
++ for (i = 0; i < NVRAM_MAX_GPIO_ENTRIES; i++) {
+ err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i);
+ if (err <= 0)
+ continue;
+diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
+index 1b170bf..ab698ba 100644
+--- a/arch/mips/bcm47xx/prom.c
++++ b/arch/mips/bcm47xx/prom.c
+@@ -35,7 +35,6 @@
+ #include <bcm47xx.h>
+ #include <bcm47xx_board.h>
+
+-
+ static char bcm47xx_system_type[20] = "Broadcom BCM47XX";
+
+ const char *get_system_type(void)
+@@ -83,7 +82,7 @@ static __init void prom_init_mem(void)
+ /* Loop condition may be not enough, off may be over 1 MiB */
+ if (off + mem >= max) {
+ mem = max;
+- printk(KERN_DEBUG "assume 128MB RAM\n");
++ pr_debug("Assume 128MB RAM\n");
+ break;
+ }
+ if (!memcmp(prom_init, prom_init + mem, 32))
+diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c
+index 2f5bbd6..df761d3 100644
+--- a/arch/mips/bcm47xx/serial.c
++++ b/arch/mips/bcm47xx/serial.c
+@@ -36,8 +36,8 @@ static int __init uart8250_init_ssb(void)
+ struct plat_serial8250_port *p = &(uart8250_data[i]);
+ struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]);
+
+- p->mapbase = (unsigned int) ssb_port->regs;
+- p->membase = (void *) ssb_port->regs;
++ p->mapbase = (unsigned int)ssb_port->regs;
++ p->membase = (void *)ssb_port->regs;
+ p->irq = ssb_port->irq + 2;
+ p->uartclk = ssb_port->baud_base;
+ p->regshift = ssb_port->reg_shift;
+@@ -62,8 +62,8 @@ static int __init uart8250_init_bcma(void)
+ struct bcma_serial_port *bcma_port;
+ bcma_port = &(cc->serial_ports[i]);
+
+- p->mapbase = (unsigned int) bcma_port->regs;
+- p->membase = (void *) bcma_port->regs;
++ p->mapbase = (unsigned int)bcma_port->regs;
++ p->membase = (void *)bcma_port->regs;
+ p->irq = bcma_port->irq;
+ p->uartclk = bcma_port->baud_base;
+ p->regshift = bcma_port->reg_shift;
+diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
+index b26c9c2..82ff9fd 100644
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -52,7 +52,7 @@ EXPORT_SYMBOL(bcm47xx_bus_type);
+
+ static void bcm47xx_machine_restart(char *command)
+ {
+- printk(KERN_ALERT "Please stand by while rebooting the system...\n");
++ pr_alert("Please stand by while rebooting the system...\n");
+ local_irq_disable();
+ /* Set the watchdog timer to reset immediately */
+ switch (bcm47xx_bus_type) {
+@@ -107,7 +107,7 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus,
+ char buf[20];
+
+ /* Fill boardinfo structure */
+- memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
++ memset(&iv->boardinfo, 0 , sizeof(struct ssb_boardinfo));
+
+ bcm47xx_fill_ssb_boardinfo(&iv->boardinfo, NULL);
+
+@@ -126,7 +126,7 @@ static void __init bcm47xx_register_ssb(void)
+ char buf[100];
+ struct ssb_mipscore *mcore;
+
+- err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE,
++ err = ssb_bus_ssbbus_register(&bcm47xx_bus.ssb, SSB_ENUM_BASE,
+ bcm47xx_get_invariants);
+ if (err)
+ panic("Failed to initialize SSB bus (err %d)", err);
+@@ -136,7 +136,7 @@ static void __init bcm47xx_register_ssb(void)
+ if (strstr(buf, "console=ttyS1")) {
+ struct ssb_serial_port port;
+
+- printk(KERN_DEBUG "Swapping serial ports!\n");
++ pr_debug("Swapping serial ports!\n");
+ /* swap serial ports */
+ memcpy(&port, &mcore->serial_ports[0], sizeof(port));
+ memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1],
+@@ -168,7 +168,7 @@ void __init plat_mem_setup(void)
+ struct cpuinfo_mips *c = ¤t_cpu_data;
+
+ if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) {
+- printk(KERN_INFO "bcm47xx: using bcma bus\n");
++ pr_info("Using bcma bus\n");
+ #ifdef CONFIG_BCM47XX_BCMA
+ bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
+ bcm47xx_sprom_register_fallbacks();
+@@ -179,7 +179,7 @@ void __init plat_mem_setup(void)
+ #endif
+ #endif
+ } else {
+- printk(KERN_INFO "bcm47xx: using ssb bus\n");
++ pr_info("Using ssb bus\n");
+ #ifdef CONFIG_BCM47XX_SSB
+ bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
+ bcm47xx_sprom_register_fallbacks();
+diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c
+index c114b02..5d32afc 100644
+--- a/arch/mips/bcm47xx/sprom.c
++++ b/arch/mips/bcm47xx/sprom.c
+@@ -780,8 +780,8 @@ void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
+ bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
+ break;
+ default:
+- pr_warn("Unsupported SPROM revision %d detected. Will extract"
+- " v1\n", sprom->revision);
++ pr_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
++ sprom->revision);
+ sprom->revision = 1;
+ bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
+ bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
+@@ -828,7 +828,7 @@ static int bcm47xx_get_sprom_ssb(struct ssb_bus *bus, struct ssb_sprom *out)
+ bcm47xx_fill_sprom(out, prefix, false);
+ return 0;
+ } else {
+- pr_warn("bcm47xx: unable to fill SPROM for given bustype.\n");
++ pr_warn("Unable to fill SPROM for given bustype.\n");
+ return -EINVAL;
+ }
+ }
+@@ -893,7 +893,7 @@ static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out)
+ }
+ return 0;
+ default:
+- pr_warn("bcm47xx: unable to fill SPROM for given bustype.\n");
++ pr_warn("Unable to fill SPROM for given bustype.\n");
+ return -EINVAL;
+ }
+ }
+diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c
+index 5b46510..74224cf 100644
+--- a/arch/mips/bcm47xx/time.c
++++ b/arch/mips/bcm47xx/time.c
+@@ -22,7 +22,6 @@
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+-
+ #include <linux/init.h>
+ #include <linux/ssb/ssb.h>
+ #include <asm/time.h>
+--
+1.8.4.5
+
--- /dev/null
+From 50c979109c484c07358a1ac75b99df36d563c132 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 1 Apr 2015 08:23:03 +0200
+Subject: [PATCH] MIPS: BCM47XX: Include io.h directly and fix brace indent
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We use IO functions like readl & ioremap_nocache, so include linux/io.h
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Patchwork: https://patchwork.linux-mips.org/patch/9650/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/nvram.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
+index 6a97732..2357ea3 100644
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -11,6 +11,7 @@
+ * option) any later version.
+ */
+
++#include <linux/io.h>
+ #include <linux/types.h>
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+@@ -203,7 +204,7 @@ int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
+ if (eq - var == strlen(name) &&
+ strncmp(var, name, eq - var) == 0)
+ return snprintf(val, val_len, "%s", value);
+- }
++ }
+ return -ENOENT;
+ }
+ EXPORT_SYMBOL(bcm47xx_nvram_getenv);
+--
+1.8.4.5
+
--- /dev/null
+From 6ab7c29099390b3d23c97f14498fd26a5ef6b22b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 1 Apr 2015 08:23:04 +0200
+Subject: [PATCH] MIPS: BCM47XX: Increase NVRAM buffer size to 64 KiB
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For years Broadcom devices use 64 KiB NVRAM partition size and some of
+them indeed have it filled in more than 50%. This change allows reading
+whole NVRAM e.g. on Netgear WNDR4500 and Netgear R8000.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Patchwork: https://patchwork.linux-mips.org/patch/9651/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/nvram.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
+index 2357ea3..2ac7482 100644
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -20,7 +20,7 @@
+ #include <linux/bcm47xx_nvram.h>
+
+ #define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
+-#define NVRAM_SPACE 0x8000
++#define NVRAM_SPACE 0x10000
+ #define NVRAM_MAX_GPIO_ENTRIES 32
+ #define NVRAM_MAX_GPIO_VALUE_LEN 30
+
+--
+1.8.4.5
+
--- /dev/null
+From 40d12172c8a5c2f3fc39642fc564b053575cd000 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 1 Apr 2015 08:23:05 +0200
+Subject: [PATCH] MIPS: BCM47XX: Don't try guessing NVRAM size on MTD partition
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When dealing with whole flash content (bcm47xx_nvram_init_from_mem) we
+need to find NVRAM start trying various partition sizes (nvram_sizes).
+This is not needed when using MTD as we have direct partition access.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Patchwork: https://patchwork.linux-mips.org/patch/9652/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/nvram.c | 36 ++++++++++++++----------------------
+ 1 file changed, 14 insertions(+), 22 deletions(-)
+
+diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
+index 2ac7482..ba632ff 100644
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -139,36 +139,28 @@ static int nvram_init(void)
+ struct mtd_info *mtd;
+ struct nvram_header header;
+ size_t bytes_read;
+- int err, i;
++ int err;
+
+ mtd = get_mtd_device_nm("nvram");
+ if (IS_ERR(mtd))
+ return -ENODEV;
+
+- for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
+- loff_t from = mtd->size - nvram_sizes[i];
+-
+- if (from < 0)
+- continue;
+-
+- err = mtd_read(mtd, from, sizeof(header), &bytes_read,
+- (uint8_t *)&header);
+- if (!err && header.magic == NVRAM_MAGIC) {
+- u8 *dst = (uint8_t *)nvram_buf;
+- size_t len = header.len;
++ err = mtd_read(mtd, 0, sizeof(header), &bytes_read, (uint8_t *)&header);
++ if (!err && header.magic == NVRAM_MAGIC) {
++ u8 *dst = (uint8_t *)nvram_buf;
++ size_t len = header.len;
+
+- if (header.len > NVRAM_SPACE) {
+- pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
+- header.len, NVRAM_SPACE);
+- len = NVRAM_SPACE;
+- }
++ if (header.len > NVRAM_SPACE) {
++ pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
++ header.len, NVRAM_SPACE);
++ len = NVRAM_SPACE;
++ }
+
+- err = mtd_read(mtd, from, len, &bytes_read, dst);
+- if (err)
+- return err;
++ err = mtd_read(mtd, 0, len, &bytes_read, dst);
++ if (err)
++ return err;
+
+- return 0;
+- }
++ return 0;
+ }
+ #endif
+
+--
+1.8.4.5
+
--- /dev/null
+From 7515c6f1da334184c3ece06e6f61461086d8e2b1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 1 Apr 2015 18:18:01 +0200
+Subject: [PATCH] MIPS: BCM47xx: Keep ID entries for non-standard devices
+ together
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Patchwork: https://patchwork.linux-mips.org/patch/9655/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/board.c | 48 ++++++++++++++++++++---------------------------
+ 1 file changed, 20 insertions(+), 28 deletions(-)
+
+diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
+index d4a5a51..f936dcc 100644
+--- a/arch/mips/bcm47xx/board.c
++++ b/arch/mips/bcm47xx/board.c
+@@ -40,20 +40,6 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = {
+ { {0}, NULL},
+ };
+
+-/* model_no */
+-static const
+-struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = {
+- {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"},
+- { {0}, NULL},
+-};
+-
+-/* machine_name */
+-static const
+-struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = {
+- {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"},
+- { {0}, NULL},
+-};
+-
+ /* hardware_version */
+ static const
+ struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = {
+@@ -202,6 +188,18 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_board_type_rev[] __initconst
+ { {0}, NULL},
+ };
+
++/*
++ * Some devices don't use any common NVRAM entry for identification and they
++ * have only one model specific variable.
++ * They don't deserve own arrays, let's group them there using key-value array.
++ */
++static const
++struct bcm47xx_board_type_list2 bcm47xx_board_list_key_value[] __initconst = {
++ {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "model_no", "WL700"},
++ {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "machine_name", "WRTSL54GS"},
++ { {0}, NULL},
++};
++
+ static const
+ struct bcm47xx_board_type bcm47xx_board_unknown[] __initconst = {
+ {BCM47XX_BOARD_UNKNOWN, "Unknown Board"},
+@@ -225,20 +223,6 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
+ }
+ }
+
+- if (bcm47xx_nvram_getenv("model_no", buf1, sizeof(buf1)) >= 0) {
+- for (e1 = bcm47xx_board_list_model_no; e1->value1; e1++) {
+- if (strstarts(buf1, e1->value1))
+- return &e1->board;
+- }
+- }
+-
+- if (bcm47xx_nvram_getenv("machine_name", buf1, sizeof(buf1)) >= 0) {
+- for (e1 = bcm47xx_board_list_machine_name; e1->value1; e1++) {
+- if (strstarts(buf1, e1->value1))
+- return &e1->board;
+- }
+- }
+-
+ if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0) {
+ for (e1 = bcm47xx_board_list_hardware_version; e1->value1; e1++) {
+ if (strstarts(buf1, e1->value1))
+@@ -314,6 +298,14 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
+ return &e2->board;
+ }
+ }
++
++ for (e2 = bcm47xx_board_list_key_value; e2->value1; e2++) {
++ if (bcm47xx_nvram_getenv(e2->value1, buf1, sizeof(buf1)) >= 0) {
++ if (!strcmp(buf1, e2->value2))
++ return &e2->board;
++ }
++ }
++
+ return bcm47xx_board_unknown;
+ }
+
+--
+1.8.4.5
+
--- /dev/null
+From 160f14312b0b7d35759535b1f60be79247b263c4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 1 Apr 2015 18:18:02 +0200
+Subject: [PATCH] MIPS: BCM47xx: Devices database update for 4.1 (or 4.2?)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Patchwork: https://patchwork.linux-mips.org/patch/9656/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/board.c | 4 ++++
+ arch/mips/bcm47xx/buttons.c | 18 ++++++++++++++++++
+ arch/mips/bcm47xx/leds.c | 10 ++++++++++
+ arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 4 ++++
+ 4 files changed, 36 insertions(+)
+
+diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
+index f936dcc..41b9736 100644
+--- a/arch/mips/bcm47xx/board.c
++++ b/arch/mips/bcm47xx/board.c
+@@ -151,9 +151,11 @@ static const
+ struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
+ {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
+ {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
++ {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
+ {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"},
+ {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"},
+ {{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"},
++ {{BCM47XX_BOARD_NETGEAR_WNDR3400_V3, "Netgear WNDR3400 V3"}, "U12H208T00_NETGEAR"},
+ {{BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, "Netgear WNDR3400 Vcna"}, "U12H155T01_NETGEAR"},
+ {{BCM47XX_BOARD_NETGEAR_WNDR3700V3, "Netgear WNDR3700 V3"}, "U12H194T00_NETGEAR"},
+ {{BCM47XX_BOARD_NETGEAR_WNDR4000, "Netgear WNDR4000"}, "U12H181T00_NETGEAR"},
+@@ -196,6 +198,8 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_board_type_rev[] __initconst
+ static const
+ struct bcm47xx_board_type_list2 bcm47xx_board_list_key_value[] __initconst = {
+ {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "model_no", "WL700"},
++ {{BCM47XX_BOARD_LINKSYS_WRT300N_V1, "Linksys WRT300N V1"}, "router_name", "WRT300N"},
++ {{BCM47XX_BOARD_LINKSYS_WRT600N_V11, "Linksys WRT600N V1.1"}, "Model_Name", "WRT600N"},
+ {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "machine_name", "WRTSL54GS"},
+ { {0}, NULL},
+ };
+diff --git a/arch/mips/bcm47xx/buttons.c b/arch/mips/bcm47xx/buttons.c
+index 913182b..276276a 100644
+--- a/arch/mips/bcm47xx/buttons.c
++++ b/arch/mips/bcm47xx/buttons.c
+@@ -252,6 +252,12 @@ bcm47xx_buttons_linksys_wrt160nv3[] __initconst = {
+ };
+
+ static const struct gpio_keys_button
++bcm47xx_buttons_linksys_wrt300n_v1[] __initconst = {
++ BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
++ BCM47XX_GPIO_KEY(6, KEY_RESTART),
++};
++
++static const struct gpio_keys_button
+ bcm47xx_buttons_linksys_wrt300nv11[] __initconst = {
+ BCM47XX_GPIO_KEY(4, KEY_UNKNOWN),
+ BCM47XX_GPIO_KEY(6, KEY_RESTART),
+@@ -327,6 +333,12 @@ bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
+ };
+
+ static const struct gpio_keys_button
++bcm47xx_buttons_netgear_wndr3400_v3[] __initconst = {
++ BCM47XX_GPIO_KEY(12, KEY_RESTART),
++ BCM47XX_GPIO_KEY(23, KEY_WPS_BUTTON),
++};
++
++static const struct gpio_keys_button
+ bcm47xx_buttons_netgear_wndr3700v3[] __initconst = {
+ BCM47XX_GPIO_KEY(2, KEY_RFKILL),
+ BCM47XX_GPIO_KEY(3, KEY_RESTART),
+@@ -516,6 +528,9 @@ int __init bcm47xx_buttons_register(void)
+ case BCM47XX_BOARD_LINKSYS_WRT160NV3:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt160nv3);
+ break;
++ case BCM47XX_BOARD_LINKSYS_WRT300N_V1:
++ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt300n_v1);
++ break;
+ case BCM47XX_BOARD_LINKSYS_WRT300NV11:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt300nv11);
+ break;
+@@ -557,6 +572,9 @@ int __init bcm47xx_buttons_register(void)
+ case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
+ break;
++ case BCM47XX_BOARD_NETGEAR_WNDR3400_V3:
++ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400_v3);
++ break;
+ case BCM47XX_BOARD_NETGEAR_WNDR3700V3:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3700v3);
+ break;
+diff --git a/arch/mips/bcm47xx/leds.c b/arch/mips/bcm47xx/leds.c
+index 903a656..0e4ade3 100644
+--- a/arch/mips/bcm47xx/leds.c
++++ b/arch/mips/bcm47xx/leds.c
+@@ -292,6 +292,13 @@ bcm47xx_leds_linksys_wrt160nv3[] __initconst = {
+ };
+
+ static const struct gpio_led
++bcm47xx_leds_linksys_wrt300n_v1[] __initconst = {
++ BCM47XX_GPIO_LED(1, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
++ BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
++ BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
++};
++
++static const struct gpio_led
+ bcm47xx_leds_linksys_wrt300nv11[] __initconst = {
+ BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+ BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+@@ -585,6 +592,9 @@ void __init bcm47xx_leds_register(void)
+ case BCM47XX_BOARD_LINKSYS_WRT160NV3:
+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt160nv3);
+ break;
++ case BCM47XX_BOARD_LINKSYS_WRT300N_V1:
++ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt300n_v1);
++ break;
+ case BCM47XX_BOARD_LINKSYS_WRT300NV11:
+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt300nv11);
+ break;
+diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+index 1f5643b..c41d1dc 100644
+--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+@@ -67,6 +67,7 @@ enum bcm47xx_board {
+ BCM47XX_BOARD_LINKSYS_WRT150NV11,
+ BCM47XX_BOARD_LINKSYS_WRT160NV1,
+ BCM47XX_BOARD_LINKSYS_WRT160NV3,
++ BCM47XX_BOARD_LINKSYS_WRT300N_V1,
+ BCM47XX_BOARD_LINKSYS_WRT300NV11,
+ BCM47XX_BOARD_LINKSYS_WRT310NV1,
+ BCM47XX_BOARD_LINKSYS_WRT310NV2,
+@@ -74,6 +75,7 @@ enum bcm47xx_board {
+ BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
+ BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
+ BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708,
++ BCM47XX_BOARD_LINKSYS_WRT600N_V11,
+ BCM47XX_BOARD_LINKSYS_WRT610NV1,
+ BCM47XX_BOARD_LINKSYS_WRT610NV2,
+ BCM47XX_BOARD_LINKSYS_WRTSL54GS,
+@@ -86,9 +88,11 @@ enum bcm47xx_board {
+
+ BCM47XX_BOARD_NETGEAR_WGR614V8,
+ BCM47XX_BOARD_NETGEAR_WGR614V9,
++ BCM47XX_BOARD_NETGEAR_WGR614_V10,
+ BCM47XX_BOARD_NETGEAR_WNDR3300,
+ BCM47XX_BOARD_NETGEAR_WNDR3400V1,
+ BCM47XX_BOARD_NETGEAR_WNDR3400V2,
++ BCM47XX_BOARD_NETGEAR_WNDR3400_V3,
+ BCM47XX_BOARD_NETGEAR_WNDR3400VCNA,
+ BCM47XX_BOARD_NETGEAR_WNDR3700V3,
+ BCM47XX_BOARD_NETGEAR_WNDR4000,
+--
+1.8.4.5
+
--- /dev/null
+From d55a52ccf8f80cdf51af2c5c6e56c825f98c4f85 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Thu, 2 Apr 2015 09:13:49 +0200
+Subject: [PATCH] MIPS: BCM47xx: Add generic function filling SPROM entries
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Handling many SPROM revisions became messy, we have tons of functions
+specific to various revision groups which are quite hard to track.
+For years there is yet another revision 11 asking for support, but
+adding it in current the form would make things even worse.
+To resolve this problem let's add new function with table-like entries
+that will contain revision bitmask for every SPROM variable.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Cc: Jonas Gorski <jonas.gorski@gmail.com>
+Patchwork: https://patchwork.linux-mips.org/patch/9659/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/sprom.c | 32 +++++++++++++++++++++++++++++---
+ 1 file changed, 29 insertions(+), 3 deletions(-)
+
+diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c
+index 5d32afc..77790c9 100644
+--- a/arch/mips/bcm47xx/sprom.c
++++ b/arch/mips/bcm47xx/sprom.c
+@@ -180,6 +180,33 @@ static void nvram_read_alpha2(const char *prefix, const char *name,
+ memcpy(val, buf, 2);
+ }
+
++/* This is one-function-only macro, it uses local "sprom" variable! */
++#define ENTRY(_revmask, _type, _prefix, _name, _val, _allset, _fallback) \
++ if (_revmask & BIT(sprom->revision)) \
++ nvram_read_ ## _type(_prefix, NULL, _name, &sprom->_val, \
++ _allset, _fallback)
++/*
++ * Special version of filling function that can be safely called for any SPROM
++ * revision. For every NVRAM to SPROM mapping it contains bitmask of revisions
++ * for which the mapping is valid.
++ * It obviously requires some hexadecimal/bitmasks knowledge, but allows
++ * writing cleaner code (easy revisions handling).
++ * Note that while SPROM revision 0 was never used, we still keep BIT(0)
++ * reserved for it, just to keep numbering sane.
++ */
++static void bcm47xx_sprom_fill_auto(struct ssb_sprom *sprom,
++ const char *prefix, bool fallback)
++{
++ const char *pre = prefix;
++ bool fb = fallback;
++
++ ENTRY(0xfffffffe, u16, pre, "boardrev", board_rev, 0, true);
++ ENTRY(0xfffffffe, u16, pre, "boardnum", board_num, 0, fb);
++
++ /* TODO: Move more mappings here */
++}
++#undef ENTRY /* It's specififc, uses local variable, don't use it (again). */
++
+ static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
+ const char *prefix, bool fallback)
+ {
+@@ -714,9 +741,6 @@ static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
+ static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
+ bool fallback)
+ {
+- nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0, true);
+- nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0,
+- fallback);
+ nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0, true);
+ nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo,
+ &sprom->boardflags_hi, fallback);
+@@ -787,6 +811,8 @@ void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
+ bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
+ bcm47xx_fill_sprom_r1(sprom, prefix, fallback);
+ }
++
++ bcm47xx_sprom_fill_auto(sprom, prefix, fallback);
+ }
+
+ #ifdef CONFIG_BCM47XX_SSB
+--
+1.8.4.5
+
--- /dev/null
+From e754dfcfe37f49c9249152e2e98e58887a4d87c8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Thu, 2 Apr 2015 12:30:24 +0200
+Subject: [PATCH] MIPS: BCM47xx: Move filling most of SPROM to the generic
+ function
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This simplifies code a lot by dropping many per-revision-group
+functions. There are still some paths left that use uncommon NVRAM read
+helpers or fill arrays. They will need to be handled in separated patch.
+
+I've tested this (by printing SPROM content) for regressions on:
+1) BCM4704 (SPROM revision 2)
+2) BCM4706 (SPROM revision 8 plus 11 & 9 on extra WiFi cards)
+The only difference is not reading board_type from SPROM rev 11 which is
+unsupported and treated as rev 1. This change for rev 1 is expected.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: Hauke Mehrtens <hauke@hauke-m.de>
+Cc: Jonas Gorski <jonas.gorski@gmail.com>
+Patchwork: https://patchwork.linux-mips.org/patch/9660/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm47xx/sprom.c | 605 ++++++++++++++++------------------------------
+ 1 file changed, 204 insertions(+), 401 deletions(-)
+
+diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c
+index 77790c9..68ebf23 100644
+--- a/arch/mips/bcm47xx/sprom.c
++++ b/arch/mips/bcm47xx/sprom.c
+@@ -201,9 +201,211 @@ static void bcm47xx_sprom_fill_auto(struct ssb_sprom *sprom,
+ bool fb = fallback;
+
+ ENTRY(0xfffffffe, u16, pre, "boardrev", board_rev, 0, true);
++ ENTRY(0x00000002, u16, pre, "boardflags", boardflags_lo, 0, fb);
++ ENTRY(0xfffffffc, u16, pre, "boardtype", board_type, 0, true);
+ ENTRY(0xfffffffe, u16, pre, "boardnum", board_num, 0, fb);
+-
+- /* TODO: Move more mappings here */
++ ENTRY(0x00000002, u8, pre, "cc", country_code, 0, fb);
++ ENTRY(0xfffffff8, u8, pre, "regrev", regrev, 0, fb);
++
++ ENTRY(0xfffffffe, u8, pre, "ledbh0", gpio0, 0xff, fb);
++ ENTRY(0xfffffffe, u8, pre, "ledbh1", gpio1, 0xff, fb);
++ ENTRY(0xfffffffe, u8, pre, "ledbh2", gpio2, 0xff, fb);
++ ENTRY(0xfffffffe, u8, pre, "ledbh3", gpio3, 0xff, fb);
++
++ ENTRY(0x0000070e, u16, pre, "pa0b0", pa0b0, 0, fb);
++ ENTRY(0x0000070e, u16, pre, "pa0b1", pa0b1, 0, fb);
++ ENTRY(0x0000070e, u16, pre, "pa0b2", pa0b2, 0, fb);
++ ENTRY(0x0000070e, u8, pre, "pa0itssit", itssi_bg, 0, fb);
++ ENTRY(0x0000070e, u8, pre, "pa0maxpwr", maxpwr_bg, 0, fb);
++
++ ENTRY(0x0000070c, u8, pre, "opo", opo, 0, fb);
++ ENTRY(0xfffffffe, u8, pre, "aa2g", ant_available_bg, 0, fb);
++ ENTRY(0xfffffffe, u8, pre, "aa5g", ant_available_a, 0, fb);
++ ENTRY(0x000007fe, s8, pre, "ag0", antenna_gain.a0, 0, fb);
++ ENTRY(0x000007fe, s8, pre, "ag1", antenna_gain.a1, 0, fb);
++ ENTRY(0x000007f0, s8, pre, "ag2", antenna_gain.a2, 0, fb);
++ ENTRY(0x000007f0, s8, pre, "ag3", antenna_gain.a3, 0, fb);
++
++ ENTRY(0x0000070e, u16, pre, "pa1b0", pa1b0, 0, fb);
++ ENTRY(0x0000070e, u16, pre, "pa1b1", pa1b1, 0, fb);
++ ENTRY(0x0000070e, u16, pre, "pa1b2", pa1b2, 0, fb);
++ ENTRY(0x0000070c, u16, pre, "pa1lob0", pa1lob0, 0, fb);
++ ENTRY(0x0000070c, u16, pre, "pa1lob1", pa1lob1, 0, fb);
++ ENTRY(0x0000070c, u16, pre, "pa1lob2", pa1lob2, 0, fb);
++ ENTRY(0x0000070c, u16, pre, "pa1hib0", pa1hib0, 0, fb);
++ ENTRY(0x0000070c, u16, pre, "pa1hib1", pa1hib1, 0, fb);
++ ENTRY(0x0000070c, u16, pre, "pa1hib2", pa1hib2, 0, fb);
++ ENTRY(0x0000070e, u8, pre, "pa1itssit", itssi_a, 0, fb);
++ ENTRY(0x0000070e, u8, pre, "pa1maxpwr", maxpwr_a, 0, fb);
++ ENTRY(0x0000070c, u8, pre, "pa1lomaxpwr", maxpwr_al, 0, fb);
++ ENTRY(0x0000070c, u8, pre, "pa1himaxpwr", maxpwr_ah, 0, fb);
++
++ ENTRY(0x00000708, u8, pre, "bxa2g", bxa2g, 0, fb);
++ ENTRY(0x00000708, u8, pre, "rssisav2g", rssisav2g, 0, fb);
++ ENTRY(0x00000708, u8, pre, "rssismc2g", rssismc2g, 0, fb);
++ ENTRY(0x00000708, u8, pre, "rssismf2g", rssismf2g, 0, fb);
++ ENTRY(0x00000708, u8, pre, "bxa5g", bxa5g, 0, fb);
++ ENTRY(0x00000708, u8, pre, "rssisav5g", rssisav5g, 0, fb);
++ ENTRY(0x00000708, u8, pre, "rssismc5g", rssismc5g, 0, fb);
++ ENTRY(0x00000708, u8, pre, "rssismf5g", rssismf5g, 0, fb);
++ ENTRY(0x00000708, u8, pre, "tri2g", tri2g, 0, fb);
++ ENTRY(0x00000708, u8, pre, "tri5g", tri5g, 0, fb);
++ ENTRY(0x00000708, u8, pre, "tri5gl", tri5gl, 0, fb);
++ ENTRY(0x00000708, u8, pre, "tri5gh", tri5gh, 0, fb);
++ ENTRY(0x00000708, s8, pre, "rxpo2g", rxpo2g, 0, fb);
++ ENTRY(0x00000708, s8, pre, "rxpo5g", rxpo5g, 0, fb);
++ ENTRY(0xfffffff0, u8, pre, "txchain", txchain, 0xf, fb);
++ ENTRY(0xfffffff0, u8, pre, "rxchain", rxchain, 0xf, fb);
++ ENTRY(0xfffffff0, u8, pre, "antswitch", antswitch, 0xff, fb);
++ ENTRY(0x00000700, u8, pre, "tssipos2g", fem.ghz2.tssipos, 0, fb);
++ ENTRY(0x00000700, u8, pre, "extpagain2g", fem.ghz2.extpa_gain, 0, fb);
++ ENTRY(0x00000700, u8, pre, "pdetrange2g", fem.ghz2.pdet_range, 0, fb);
++ ENTRY(0x00000700, u8, pre, "triso2g", fem.ghz2.tr_iso, 0, fb);
++ ENTRY(0x00000700, u8, pre, "antswctl2g", fem.ghz2.antswlut, 0, fb);
++ ENTRY(0x00000700, u8, pre, "tssipos5g", fem.ghz5.tssipos, 0, fb);
++ ENTRY(0x00000700, u8, pre, "extpagain5g", fem.ghz5.extpa_gain, 0, fb);
++ ENTRY(0x00000700, u8, pre, "pdetrange5g", fem.ghz5.pdet_range, 0, fb);
++ ENTRY(0x00000700, u8, pre, "triso5g", fem.ghz5.tr_iso, 0, fb);
++ ENTRY(0x00000700, u8, pre, "antswctl5g", fem.ghz5.antswlut, 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid2ga0", txpid2g[0], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid2ga1", txpid2g[1], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid2ga2", txpid2g[2], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid2ga3", txpid2g[3], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5ga0", txpid5g[0], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5ga1", txpid5g[1], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5ga2", txpid5g[2], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5ga3", txpid5g[3], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5gla0", txpid5gl[0], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5gla1", txpid5gl[1], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5gla2", txpid5gl[2], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5gla3", txpid5gl[3], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5gha0", txpid5gh[0], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5gha1", txpid5gh[1], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5gha2", txpid5gh[2], 0, fb);
++ ENTRY(0x000000f0, u8, pre, "txpid5gha3", txpid5gh[3], 0, fb);
++
++ ENTRY(0xffffff00, u8, pre, "tempthresh", tempthresh, 0, fb);
++ ENTRY(0xffffff00, u8, pre, "tempoffset", tempoffset, 0, fb);
++ ENTRY(0xffffff00, u16, pre, "rawtempsense", rawtempsense, 0, fb);
++ ENTRY(0xffffff00, u8, pre, "measpower", measpower, 0, fb);
++ ENTRY(0xffffff00, u8, pre, "tempsense_slope", tempsense_slope, 0, fb);
++ ENTRY(0xffffff00, u8, pre, "tempcorrx", tempcorrx, 0, fb);
++ ENTRY(0xffffff00, u8, pre, "tempsense_option", tempsense_option, 0, fb);
++ ENTRY(0x00000700, u8, pre, "freqoffset_corr", freqoffset_corr, 0, fb);
++ ENTRY(0x00000700, u8, pre, "iqcal_swp_dis", iqcal_swp_dis, 0, fb);
++ ENTRY(0x00000700, u8, pre, "hw_iqcal_en", hw_iqcal_en, 0, fb);
++ ENTRY(0x00000700, u8, pre, "elna2g", elna2g, 0, fb);
++ ENTRY(0x00000700, u8, pre, "elna5g", elna5g, 0, fb);
++ ENTRY(0xffffff00, u8, pre, "phycal_tempdelta", phycal_tempdelta, 0, fb);
++ ENTRY(0xffffff00, u8, pre, "temps_period", temps_period, 0, fb);
++ ENTRY(0xffffff00, u8, pre, "temps_hysteresis", temps_hysteresis, 0, fb);
++ ENTRY(0xffffff00, u8, pre, "measpower1", measpower1, 0, fb);
++ ENTRY(0xffffff00, u8, pre, "measpower2", measpower2, 0, fb);
++
++ ENTRY(0x000001f0, u16, pre, "cck2gpo", cck2gpo, 0, fb);
++ ENTRY(0x000001f0, u32, pre, "ofdm2gpo", ofdm2gpo, 0, fb);
++ ENTRY(0x000001f0, u32, pre, "ofdm5gpo", ofdm5gpo, 0, fb);
++ ENTRY(0x000001f0, u32, pre, "ofdm5glpo", ofdm5glpo, 0, fb);
++ ENTRY(0x000001f0, u32, pre, "ofdm5ghpo", ofdm5ghpo, 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs2gpo0", mcs2gpo[0], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs2gpo1", mcs2gpo[1], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs2gpo2", mcs2gpo[2], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs2gpo3", mcs2gpo[3], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs2gpo4", mcs2gpo[4], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs2gpo5", mcs2gpo[5], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs2gpo6", mcs2gpo[6], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs2gpo7", mcs2gpo[7], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5gpo0", mcs5gpo[0], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5gpo1", mcs5gpo[1], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5gpo2", mcs5gpo[2], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5gpo3", mcs5gpo[3], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5gpo4", mcs5gpo[4], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5gpo5", mcs5gpo[5], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5gpo6", mcs5gpo[6], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5gpo7", mcs5gpo[7], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5glpo0", mcs5glpo[0], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5glpo1", mcs5glpo[1], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5glpo2", mcs5glpo[2], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5glpo3", mcs5glpo[3], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5glpo4", mcs5glpo[4], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5glpo5", mcs5glpo[5], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5glpo6", mcs5glpo[6], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5glpo7", mcs5glpo[7], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5ghpo0", mcs5ghpo[0], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5ghpo1", mcs5ghpo[1], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5ghpo2", mcs5ghpo[2], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5ghpo3", mcs5ghpo[3], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5ghpo4", mcs5ghpo[4], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5ghpo5", mcs5ghpo[5], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5ghpo6", mcs5ghpo[6], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "mcs5ghpo7", mcs5ghpo[7], 0, fb);
++ ENTRY(0x000001f0, u16, pre, "cddpo", cddpo, 0, fb);
++ ENTRY(0x000001f0, u16, pre, "stbcpo", stbcpo, 0, fb);
++ ENTRY(0x000001f0, u16, pre, "bw40po", bw40po, 0, fb);
++ ENTRY(0x000001f0, u16, pre, "bwduppo", bwduppo, 0, fb);
++
++ ENTRY(0xfffffe00, u16, pre, "cckbw202gpo", cckbw202gpo, 0, fb);
++ ENTRY(0xfffffe00, u16, pre, "cckbw20ul2gpo", cckbw20ul2gpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "legofdmbw202gpo", legofdmbw202gpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "legofdmbw20ul2gpo", legofdmbw20ul2gpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "legofdmbw205glpo", legofdmbw205glpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "legofdmbw20ul5glpo", legofdmbw20ul5glpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "legofdmbw205gmpo", legofdmbw205gmpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "legofdmbw20ul5gmpo", legofdmbw20ul5gmpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "legofdmbw205ghpo", legofdmbw205ghpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "legofdmbw20ul5ghpo", legofdmbw20ul5ghpo, 0, fb);
++ ENTRY(0xfffffe00, u32, pre, "mcsbw202gpo", mcsbw202gpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "mcsbw20ul2gpo", mcsbw20ul2gpo, 0, fb);
++ ENTRY(0xfffffe00, u32, pre, "mcsbw402gpo", mcsbw402gpo, 0, fb);
++ ENTRY(0xfffffe00, u32, pre, "mcsbw205glpo", mcsbw205glpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "mcsbw20ul5glpo", mcsbw20ul5glpo, 0, fb);
++ ENTRY(0xfffffe00, u32, pre, "mcsbw405glpo", mcsbw405glpo, 0, fb);
++ ENTRY(0xfffffe00, u32, pre, "mcsbw205gmpo", mcsbw205gmpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "mcsbw20ul5gmpo", mcsbw20ul5gmpo, 0, fb);
++ ENTRY(0xfffffe00, u32, pre, "mcsbw405gmpo", mcsbw405gmpo, 0, fb);
++ ENTRY(0xfffffe00, u32, pre, "mcsbw205ghpo", mcsbw205ghpo, 0, fb);
++ ENTRY(0x00000600, u32, pre, "mcsbw20ul5ghpo", mcsbw20ul5ghpo, 0, fb);
++ ENTRY(0xfffffe00, u32, pre, "mcsbw405ghpo", mcsbw405ghpo, 0, fb);
++ ENTRY(0x00000600, u16, pre, "mcs32po", mcs32po, 0, fb);
++ ENTRY(0x00000600, u16, pre, "legofdm40duppo", legofdm40duppo, 0, fb);
++ ENTRY(0x00000700, u8, pre, "pcieingress_war", pcieingress_war, 0, fb);
++
++ /* TODO: rev 11 support */
++ ENTRY(0x00000700, u8, pre, "rxgainerr2ga0", rxgainerr2ga[0], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr2ga1", rxgainerr2ga[1], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr2ga2", rxgainerr2ga[2], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gla0", rxgainerr5gla[0], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gla1", rxgainerr5gla[1], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gla2", rxgainerr5gla[2], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gma0", rxgainerr5gma[0], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gma1", rxgainerr5gma[1], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gma2", rxgainerr5gma[2], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gha0", rxgainerr5gha[0], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gha1", rxgainerr5gha[1], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gha2", rxgainerr5gha[2], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gua0", rxgainerr5gua[0], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gua1", rxgainerr5gua[1], 0, fb);
++ ENTRY(0x00000700, u8, pre, "rxgainerr5gua2", rxgainerr5gua[2], 0, fb);
++
++ ENTRY(0xfffffe00, u8, pre, "sar2g", sar2g, 0, fb);
++ ENTRY(0xfffffe00, u8, pre, "sar5g", sar5g, 0, fb);
++
++ /* TODO: rev 11 support */
++ ENTRY(0x00000700, u8, pre, "noiselvl2ga0", noiselvl2ga[0], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl2ga1", noiselvl2ga[1], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl2ga2", noiselvl2ga[2], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gla0", noiselvl5gla[0], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gla1", noiselvl5gla[1], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gla2", noiselvl5gla[2], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gma0", noiselvl5gma[0], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gma1", noiselvl5gma[1], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gma2", noiselvl5gma[2], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gha0", noiselvl5gha[0], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gha1", noiselvl5gha[1], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gha2", noiselvl5gha[2], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gua0", noiselvl5gua[0], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gua1", noiselvl5gua[1], 0, fb);
++ ENTRY(0x00000700, u8, pre, "noiselvl5gua2", noiselvl5gua[2], 0, fb);
+ }
+ #undef ENTRY /* It's specififc, uses local variable, don't use it (again). */
+
+@@ -211,90 +413,12 @@ static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
+ const char *prefix, bool fallback)
+ {
+ nvram_read_u16(prefix, NULL, "devid", &sprom->dev_id, 0, fallback);
+- nvram_read_u8(prefix, NULL, "ledbh0", &sprom->gpio0, 0xff, fallback);
+- nvram_read_u8(prefix, NULL, "ledbh1", &sprom->gpio1, 0xff, fallback);
+- nvram_read_u8(prefix, NULL, "ledbh2", &sprom->gpio2, 0xff, fallback);
+- nvram_read_u8(prefix, NULL, "ledbh3", &sprom->gpio3, 0xff, fallback);
+- nvram_read_u8(prefix, NULL, "aa2g", &sprom->ant_available_bg, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "aa5g", &sprom->ant_available_a, 0,
+- fallback);
+- nvram_read_s8(prefix, NULL, "ag0", &sprom->antenna_gain.a0, 0,
+- fallback);
+- nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0,
+- fallback);
+ nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback);
+ }
+
+-static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom,
+- const char *prefix, bool fallback)
+-{
+- nvram_read_u16(prefix, NULL, "pa0b0", &sprom->pa0b0, 0, fallback);
+- nvram_read_u16(prefix, NULL, "pa0b1", &sprom->pa0b1, 0, fallback);
+- nvram_read_u16(prefix, NULL, "pa0b2", &sprom->pa0b2, 0, fallback);
+- nvram_read_u8(prefix, NULL, "pa0itssit", &sprom->itssi_bg, 0, fallback);
+- nvram_read_u8(prefix, NULL, "pa0maxpwr", &sprom->maxpwr_bg, 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "pa1b0", &sprom->pa1b0, 0, fallback);
+- nvram_read_u16(prefix, NULL, "pa1b1", &sprom->pa1b1, 0, fallback);
+- nvram_read_u16(prefix, NULL, "pa1b2", &sprom->pa1b2, 0, fallback);
+- nvram_read_u8(prefix, NULL, "pa1itssit", &sprom->itssi_a, 0, fallback);
+- nvram_read_u8(prefix, NULL, "pa1maxpwr", &sprom->maxpwr_a, 0, fallback);
+-}
+-
+-static void bcm47xx_fill_sprom_r1(struct ssb_sprom *sprom, const char *prefix,
+- bool fallback)
+-{
+- nvram_read_u16(prefix, NULL, "boardflags", &sprom->boardflags_lo, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "cc", &sprom->country_code, 0, fallback);
+-}
+-
+-static void bcm47xx_fill_sprom_r2389(struct ssb_sprom *sprom,
+- const char *prefix, bool fallback)
+-{
+- nvram_read_u8(prefix, NULL, "opo", &sprom->opo, 0, fallback);
+- nvram_read_u16(prefix, NULL, "pa1lob0", &sprom->pa1lob0, 0, fallback);
+- nvram_read_u16(prefix, NULL, "pa1lob1", &sprom->pa1lob1, 0, fallback);
+- nvram_read_u16(prefix, NULL, "pa1lob2", &sprom->pa1lob2, 0, fallback);
+- nvram_read_u16(prefix, NULL, "pa1hib0", &sprom->pa1hib0, 0, fallback);
+- nvram_read_u16(prefix, NULL, "pa1hib1", &sprom->pa1hib1, 0, fallback);
+- nvram_read_u16(prefix, NULL, "pa1hib2", &sprom->pa1hib2, 0, fallback);
+- nvram_read_u8(prefix, NULL, "pa1lomaxpwr", &sprom->maxpwr_al, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "pa1himaxpwr", &sprom->maxpwr_ah, 0,
+- fallback);
+-}
+-
+-static void bcm47xx_fill_sprom_r389(struct ssb_sprom *sprom, const char *prefix,
+- bool fallback)
+-{
+- nvram_read_u8(prefix, NULL, "bxa2g", &sprom->bxa2g, 0, fallback);
+- nvram_read_u8(prefix, NULL, "rssisav2g", &sprom->rssisav2g, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "rssismc2g", &sprom->rssismc2g, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "rssismf2g", &sprom->rssismf2g, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "bxa5g", &sprom->bxa5g, 0, fallback);
+- nvram_read_u8(prefix, NULL, "rssisav5g", &sprom->rssisav5g, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "rssismc5g", &sprom->rssismc5g, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "rssismf5g", &sprom->rssismf5g, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "tri2g", &sprom->tri2g, 0, fallback);
+- nvram_read_u8(prefix, NULL, "tri5g", &sprom->tri5g, 0, fallback);
+- nvram_read_u8(prefix, NULL, "tri5gl", &sprom->tri5gl, 0, fallback);
+- nvram_read_u8(prefix, NULL, "tri5gh", &sprom->tri5gh, 0, fallback);
+- nvram_read_s8(prefix, NULL, "rxpo2g", &sprom->rxpo2g, 0, fallback);
+- nvram_read_s8(prefix, NULL, "rxpo5g", &sprom->rxpo5g, 0, fallback);
+-}
+-
+ static void bcm47xx_fill_sprom_r3(struct ssb_sprom *sprom, const char *prefix,
+ bool fallback)
+ {
+- nvram_read_u8(prefix, NULL, "regrev", &sprom->regrev, 0, fallback);
+ nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time,
+ &sprom->leddc_off_time, fallback);
+ }
+@@ -302,309 +426,10 @@ static void bcm47xx_fill_sprom_r3(struct ssb_sprom *sprom, const char *prefix,
+ static void bcm47xx_fill_sprom_r4589(struct ssb_sprom *sprom,
+ const char *prefix, bool fallback)
+ {
+- nvram_read_u8(prefix, NULL, "regrev", &sprom->regrev, 0, fallback);
+- nvram_read_s8(prefix, NULL, "ag2", &sprom->antenna_gain.a2, 0,
+- fallback);
+- nvram_read_s8(prefix, NULL, "ag3", &sprom->antenna_gain.a3, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txchain", &sprom->txchain, 0xf, fallback);
+- nvram_read_u8(prefix, NULL, "rxchain", &sprom->rxchain, 0xf, fallback);
+- nvram_read_u8(prefix, NULL, "antswitch", &sprom->antswitch, 0xff,
+- fallback);
+ nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time,
+ &sprom->leddc_off_time, fallback);
+ }
+
+-static void bcm47xx_fill_sprom_r458(struct ssb_sprom *sprom, const char *prefix,
+- bool fallback)
+-{
+- nvram_read_u16(prefix, NULL, "cck2gpo", &sprom->cck2gpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "ofdm2gpo", &sprom->ofdm2gpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "ofdm5gpo", &sprom->ofdm5gpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "ofdm5glpo", &sprom->ofdm5glpo, 0,
+- fallback);
+- nvram_read_u32(prefix, NULL, "ofdm5ghpo", &sprom->ofdm5ghpo, 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "cddpo", &sprom->cddpo, 0, fallback);
+- nvram_read_u16(prefix, NULL, "stbcpo", &sprom->stbcpo, 0, fallback);
+- nvram_read_u16(prefix, NULL, "bw40po", &sprom->bw40po, 0, fallback);
+- nvram_read_u16(prefix, NULL, "bwduppo", &sprom->bwduppo, 0, fallback);
+- nvram_read_u16(prefix, NULL, "mcs2gpo0", &sprom->mcs2gpo[0], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs2gpo1", &sprom->mcs2gpo[1], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs2gpo2", &sprom->mcs2gpo[2], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs2gpo3", &sprom->mcs2gpo[3], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs2gpo4", &sprom->mcs2gpo[4], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs2gpo5", &sprom->mcs2gpo[5], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs2gpo6", &sprom->mcs2gpo[6], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs2gpo7", &sprom->mcs2gpo[7], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5gpo0", &sprom->mcs5gpo[0], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5gpo1", &sprom->mcs5gpo[1], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5gpo2", &sprom->mcs5gpo[2], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5gpo3", &sprom->mcs5gpo[3], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5gpo4", &sprom->mcs5gpo[4], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5gpo5", &sprom->mcs5gpo[5], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5gpo6", &sprom->mcs5gpo[6], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5gpo7", &sprom->mcs5gpo[7], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5glpo0", &sprom->mcs5glpo[0], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5glpo1", &sprom->mcs5glpo[1], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5glpo2", &sprom->mcs5glpo[2], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5glpo3", &sprom->mcs5glpo[3], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5glpo4", &sprom->mcs5glpo[4], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5glpo5", &sprom->mcs5glpo[5], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5glpo6", &sprom->mcs5glpo[6], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5glpo7", &sprom->mcs5glpo[7], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5ghpo0", &sprom->mcs5ghpo[0], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5ghpo1", &sprom->mcs5ghpo[1], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5ghpo2", &sprom->mcs5ghpo[2], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5ghpo3", &sprom->mcs5ghpo[3], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5ghpo4", &sprom->mcs5ghpo[4], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5ghpo5", &sprom->mcs5ghpo[5], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5ghpo6", &sprom->mcs5ghpo[6], 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs5ghpo7", &sprom->mcs5ghpo[7], 0,
+- fallback);
+-}
+-
+-static void bcm47xx_fill_sprom_r45(struct ssb_sprom *sprom, const char *prefix,
+- bool fallback)
+-{
+- nvram_read_u8(prefix, NULL, "txpid2ga0", &sprom->txpid2g[0], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid2ga1", &sprom->txpid2g[1], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid2ga2", &sprom->txpid2g[2], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid2ga3", &sprom->txpid2g[3], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5ga0", &sprom->txpid5g[0], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5ga1", &sprom->txpid5g[1], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5ga2", &sprom->txpid5g[2], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5ga3", &sprom->txpid5g[3], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5gla0", &sprom->txpid5gl[0], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5gla1", &sprom->txpid5gl[1], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5gla2", &sprom->txpid5gl[2], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5gla3", &sprom->txpid5gl[3], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5gha0", &sprom->txpid5gh[0], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5gha1", &sprom->txpid5gh[1], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5gha2", &sprom->txpid5gh[2], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "txpid5gha3", &sprom->txpid5gh[3], 0,
+- fallback);
+-}
+-
+-static void bcm47xx_fill_sprom_r89(struct ssb_sprom *sprom, const char *prefix,
+- bool fallback)
+-{
+- nvram_read_u8(prefix, NULL, "tssipos2g", &sprom->fem.ghz2.tssipos, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "extpagain2g",
+- &sprom->fem.ghz2.extpa_gain, 0, fallback);
+- nvram_read_u8(prefix, NULL, "pdetrange2g",
+- &sprom->fem.ghz2.pdet_range, 0, fallback);
+- nvram_read_u8(prefix, NULL, "triso2g", &sprom->fem.ghz2.tr_iso, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "antswctl2g", &sprom->fem.ghz2.antswlut, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "tssipos5g", &sprom->fem.ghz5.tssipos, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "extpagain5g",
+- &sprom->fem.ghz5.extpa_gain, 0, fallback);
+- nvram_read_u8(prefix, NULL, "pdetrange5g",
+- &sprom->fem.ghz5.pdet_range, 0, fallback);
+- nvram_read_u8(prefix, NULL, "triso5g", &sprom->fem.ghz5.tr_iso, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "antswctl5g", &sprom->fem.ghz5.antswlut, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "tempthresh", &sprom->tempthresh, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "tempoffset", &sprom->tempoffset, 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "rawtempsense", &sprom->rawtempsense, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "measpower", &sprom->measpower, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "tempsense_slope",
+- &sprom->tempsense_slope, 0, fallback);
+- nvram_read_u8(prefix, NULL, "tempcorrx", &sprom->tempcorrx, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "tempsense_option",
+- &sprom->tempsense_option, 0, fallback);
+- nvram_read_u8(prefix, NULL, "freqoffset_corr",
+- &sprom->freqoffset_corr, 0, fallback);
+- nvram_read_u8(prefix, NULL, "iqcal_swp_dis", &sprom->iqcal_swp_dis, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "hw_iqcal_en", &sprom->hw_iqcal_en, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "elna2g", &sprom->elna2g, 0, fallback);
+- nvram_read_u8(prefix, NULL, "elna5g", &sprom->elna5g, 0, fallback);
+- nvram_read_u8(prefix, NULL, "phycal_tempdelta",
+- &sprom->phycal_tempdelta, 0, fallback);
+- nvram_read_u8(prefix, NULL, "temps_period", &sprom->temps_period, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "temps_hysteresis",
+- &sprom->temps_hysteresis, 0, fallback);
+- nvram_read_u8(prefix, NULL, "measpower1", &sprom->measpower1, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "measpower2", &sprom->measpower2, 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr2ga0",
+- &sprom->rxgainerr2ga[0], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr2ga1",
+- &sprom->rxgainerr2ga[1], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr2ga2",
+- &sprom->rxgainerr2ga[2], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gla0",
+- &sprom->rxgainerr5gla[0], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gla1",
+- &sprom->rxgainerr5gla[1], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gla2",
+- &sprom->rxgainerr5gla[2], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gma0",
+- &sprom->rxgainerr5gma[0], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gma1",
+- &sprom->rxgainerr5gma[1], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gma2",
+- &sprom->rxgainerr5gma[2], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gha0",
+- &sprom->rxgainerr5gha[0], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gha1",
+- &sprom->rxgainerr5gha[1], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gha2",
+- &sprom->rxgainerr5gha[2], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gua0",
+- &sprom->rxgainerr5gua[0], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gua1",
+- &sprom->rxgainerr5gua[1], 0, fallback);
+- nvram_read_u8(prefix, NULL, "rxgainerr5gua2",
+- &sprom->rxgainerr5gua[2], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl2ga0", &sprom->noiselvl2ga[0], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl2ga1", &sprom->noiselvl2ga[1], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl2ga2", &sprom->noiselvl2ga[2], 0,
+- fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gla0",
+- &sprom->noiselvl5gla[0], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gla1",
+- &sprom->noiselvl5gla[1], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gla2",
+- &sprom->noiselvl5gla[2], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gma0",
+- &sprom->noiselvl5gma[0], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gma1",
+- &sprom->noiselvl5gma[1], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gma2",
+- &sprom->noiselvl5gma[2], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gha0",
+- &sprom->noiselvl5gha[0], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gha1",
+- &sprom->noiselvl5gha[1], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gha2",
+- &sprom->noiselvl5gha[2], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gua0",
+- &sprom->noiselvl5gua[0], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gua1",
+- &sprom->noiselvl5gua[1], 0, fallback);
+- nvram_read_u8(prefix, NULL, "noiselvl5gua2",
+- &sprom->noiselvl5gua[2], 0, fallback);
+- nvram_read_u8(prefix, NULL, "pcieingress_war",
+- &sprom->pcieingress_war, 0, fallback);
+-}
+-
+-static void bcm47xx_fill_sprom_r9(struct ssb_sprom *sprom, const char *prefix,
+- bool fallback)
+-{
+- nvram_read_u16(prefix, NULL, "cckbw202gpo", &sprom->cckbw202gpo, 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "cckbw20ul2gpo", &sprom->cckbw20ul2gpo, 0,
+- fallback);
+- nvram_read_u32(prefix, NULL, "legofdmbw202gpo",
+- &sprom->legofdmbw202gpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "legofdmbw20ul2gpo",
+- &sprom->legofdmbw20ul2gpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "legofdmbw205glpo",
+- &sprom->legofdmbw205glpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "legofdmbw20ul5glpo",
+- &sprom->legofdmbw20ul5glpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "legofdmbw205gmpo",
+- &sprom->legofdmbw205gmpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "legofdmbw20ul5gmpo",
+- &sprom->legofdmbw20ul5gmpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "legofdmbw205ghpo",
+- &sprom->legofdmbw205ghpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "legofdmbw20ul5ghpo",
+- &sprom->legofdmbw20ul5ghpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw202gpo", &sprom->mcsbw202gpo, 0,
+- fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw20ul2gpo", &sprom->mcsbw20ul2gpo, 0,
+- fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw402gpo", &sprom->mcsbw402gpo, 0,
+- fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw205glpo", &sprom->mcsbw205glpo, 0,
+- fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw20ul5glpo",
+- &sprom->mcsbw20ul5glpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw405glpo", &sprom->mcsbw405glpo, 0,
+- fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw205gmpo", &sprom->mcsbw205gmpo, 0,
+- fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw20ul5gmpo",
+- &sprom->mcsbw20ul5gmpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw405gmpo", &sprom->mcsbw405gmpo, 0,
+- fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw205ghpo", &sprom->mcsbw205ghpo, 0,
+- fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw20ul5ghpo",
+- &sprom->mcsbw20ul5ghpo, 0, fallback);
+- nvram_read_u32(prefix, NULL, "mcsbw405ghpo", &sprom->mcsbw405ghpo, 0,
+- fallback);
+- nvram_read_u16(prefix, NULL, "mcs32po", &sprom->mcs32po, 0, fallback);
+- nvram_read_u16(prefix, NULL, "legofdm40duppo",
+- &sprom->legofdm40duppo, 0, fallback);
+- nvram_read_u8(prefix, NULL, "sar2g", &sprom->sar2g, 0, fallback);
+- nvram_read_u8(prefix, NULL, "sar5g", &sprom->sar5g, 0, fallback);
+-}
+-
+ static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom,
+ const char *prefix, bool fallback)
+ {
+@@ -741,7 +566,6 @@ static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
+ static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
+ bool fallback)
+ {
+- nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0, true);
+ nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo,
+ &sprom->boardflags_hi, fallback);
+ nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo,
+@@ -759,48 +583,29 @@ void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
+ switch (sprom->revision) {
+ case 1:
+ bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r1(sprom, prefix, fallback);
+ break;
+ case 2:
+ bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
+ break;
+ case 3:
+ bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r389(sprom, prefix, fallback);
+ bcm47xx_fill_sprom_r3(sprom, prefix, fallback);
+ break;
+ case 4:
+ case 5:
+ bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
+ bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r458(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r45(sprom, prefix, fallback);
+ bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
+ bcm47xx_fill_sprom_path_r45(sprom, prefix, fallback);
+ break;
+ case 8:
+ bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r389(sprom, prefix, fallback);
+ bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r458(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r89(sprom, prefix, fallback);
+ bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
+ break;
+ case 9:
+ bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r389(sprom, prefix, fallback);
+ bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r89(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r9(sprom, prefix, fallback);
+ bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
+ break;
+ default:
+@@ -808,8 +613,6 @@ void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
+ sprom->revision);
+ sprom->revision = 1;
+ bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
+- bcm47xx_fill_sprom_r1(sprom, prefix, fallback);
+ }
+
+ bcm47xx_sprom_fill_auto(sprom, prefix, fallback);
+--
+1.8.4.5
+
--- /dev/null
+--- a/arch/mips/include/asm/r4kcache.h
++++ b/arch/mips/include/asm/r4kcache.h
+@@ -23,6 +23,20 @@
+ extern void (*r4k_blast_dcache)(void);
+ extern void (*r4k_blast_icache)(void);
+
++#ifdef CONFIG_BCM47XX
++#include <asm/paccess.h>
++#include <linux/ssb/ssb.h>
++#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
++
++#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
++#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
++#else
++#define BCM4710_DUMMY_RREG()
++
++#define BCM4710_FILL_TLB(addr)
++#define BCM4710_PROTECTED_FILL_TLB(addr)
++#endif
++
+ /*
+ * This macro return a properly sign-extended address suitable as base address
+ * for indexed cache operations. Two issues here:
+@@ -96,6 +110,7 @@ static inline void flush_icache_line_ind
+ static inline void flush_dcache_line_indexed(unsigned long addr)
+ {
+ __dflush_prologue
++ BCM4710_DUMMY_RREG();
+ cache_op(Index_Writeback_Inv_D, addr);
+ __dflush_epilogue
+ }
+@@ -123,6 +138,7 @@ static inline void flush_icache_line(uns
+ static inline void flush_dcache_line(unsigned long addr)
+ {
+ __dflush_prologue
++ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Writeback_Inv_D, addr);
+ __dflush_epilogue
+ }
+@@ -130,6 +146,7 @@ static inline void flush_dcache_line(uns
+ static inline void invalidate_dcache_line(unsigned long addr)
+ {
+ __dflush_prologue
++ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Invalidate_D, addr);
+ __dflush_epilogue
+ }
+@@ -185,6 +202,7 @@ static inline void protected_flush_icach
+ #ifdef CONFIG_EVA
+ protected_cachee_op(Hit_Invalidate_I, addr);
+ #else
++ BCM4710_DUMMY_RREG();
+ protected_cache_op(Hit_Invalidate_I, addr);
+ #endif
+ break;
+@@ -199,6 +217,7 @@ static inline void protected_flush_icach
+ */
+ static inline void protected_writeback_dcache_line(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ #ifdef CONFIG_EVA
+ protected_cachee_op(Hit_Writeback_Inv_D, addr);
+ #else
+@@ -553,8 +572,51 @@ static inline void invalidate_tcache_pag
+ : "r" (base), \
+ "i" (op));
+
++static inline void blast_dcache(void)
++{
++ unsigned long start = KSEG0;
++ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
++ unsigned long end = (start + dcache_size);
++
++ do {
++ BCM4710_DUMMY_RREG();
++ cache_op(Index_Writeback_Inv_D, start);
++ start += current_cpu_data.dcache.linesz;
++ } while(start < end);
++}
++
++static inline void blast_dcache_page(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = start + PAGE_SIZE;
++
++ BCM4710_FILL_TLB(start);
++ do {
++ BCM4710_DUMMY_RREG();
++ cache_op(Hit_Writeback_Inv_D, start);
++ start += current_cpu_data.dcache.linesz;
++ } while(start < end);
++}
++
++static inline void blast_dcache_page_indexed(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = start + PAGE_SIZE;
++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++ unsigned long ws_end = current_cpu_data.dcache.ways <<
++ current_cpu_data.dcache.waybit;
++ unsigned long ws, addr;
++ for (ws = 0; ws < ws_end; ws += ws_inc) {
++ start = page + ws;
++ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
++ BCM4710_DUMMY_RREG();
++ cache_op(Index_Writeback_Inv_D, addr);
++ }
++ }
++}
++
+ /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
+-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
++#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
+ static inline void extra##blast_##pfx##cache##lsize(void) \
+ { \
+ unsigned long start = INDEX_BASE; \
+@@ -566,6 +628,7 @@ static inline void extra##blast_##pfx##c
+ \
+ __##pfx##flush_prologue \
+ \
++ war \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+ for (addr = start; addr < end; addr += lsize * 32) \
+ cache##lsize##_unroll32(addr|ws, indexop); \
+@@ -580,6 +643,7 @@ static inline void extra##blast_##pfx##c
+ \
+ __##pfx##flush_prologue \
+ \
++ war \
+ do { \
+ cache##lsize##_unroll32(start, hitop); \
+ start += lsize * 32; \
+@@ -598,6 +662,8 @@ static inline void extra##blast_##pfx##c
+ current_cpu_data.desc.waybit; \
+ unsigned long ws, addr; \
+ \
++ war \
++ \
+ __##pfx##flush_prologue \
+ \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+@@ -607,26 +673,26 @@ static inline void extra##blast_##pfx##c
+ __##pfx##flush_epilogue \
+ }
+
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
+-
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
++
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
+
+ #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
+ static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
+@@ -655,17 +721,19 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
+ __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+
+ /* build blast_xxx_range, protected_blast_xxx_range */
+-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2) \
+ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
+ unsigned long end) \
+ { \
+ unsigned long lsize = cpu_##desc##_line_size(); \
+ unsigned long addr = start & ~(lsize - 1); \
+ unsigned long aend = (end - 1) & ~(lsize - 1); \
++ war \
+ \
+ __##pfx##flush_prologue \
+ \
+ while (1) { \
++ war2 \
+ prot##cache_op(hitop, addr); \
+ if (addr == aend) \
+ break; \
+@@ -677,8 +745,8 @@ static inline void prot##extra##blast_##
+
+ #ifndef CONFIG_EVA
+
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
+-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
+
+ #else
+
+@@ -715,14 +783,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
+ __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
+
+ #endif
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
+ __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
+- protected_, loongson2_)
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
+-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
++ protected_, loongson2_, , )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
+ /* blast_inv_dcache_range */
+-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
+-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
+
+ #endif /* _ASM_R4KCACHE_H */
+--- a/arch/mips/include/asm/stackframe.h
++++ b/arch/mips/include/asm/stackframe.h
+@@ -333,6 +333,10 @@
+ .macro RESTORE_SP_AND_RET
+ LONG_L sp, PT_R29(sp)
+ .set arch=r4000
++#ifdef CONFIG_BCM47XX
++ nop
++ nop
++#endif
+ eret
+ .set mips0
+ .endm
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
+@@ -32,6 +32,10 @@
+ NESTED(except_vec3_generic, 0, sp)
+ .set push
+ .set noat
++#ifdef CONFIG_BCM47XX
++ nop
++ nop
++#endif
+ #if R5432_CP0_INTERRUPT_WAR
+ mfc0 k0, CP0_INDEX
+ #endif
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -38,6 +38,9 @@
+ #include <asm/traps.h>
+ #include <asm/dma-coherence.h>
+
++/* For enabling BCM4710 cache workarounds */
++int bcm4710 = 0;
++
+ /*
+ * Special Variant of smp_call_function for use by cache functions:
+ *
+@@ -149,6 +152,9 @@ static void r4k_blast_dcache_user_page_s
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache_page = blast_dcache_page;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache_user_page = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -167,6 +173,9 @@ static void r4k_blast_dcache_page_indexe
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache_page_indexed = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -186,6 +195,9 @@ static void r4k_blast_dcache_setup(void)
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache = blast_dcache;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -784,6 +796,8 @@ static void local_r4k_flush_cache_sigtra
+ unsigned long addr = (unsigned long) arg;
+
+ R4600_HIT_CACHEOP_WAR_IMPL;
++ BCM4710_PROTECTED_FILL_TLB(addr);
++ BCM4710_PROTECTED_FILL_TLB(addr + 4);
+ if (dc_lsize)
+ protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
+ if (!cpu_icache_snoops_remote_store && scache_size)
+@@ -1580,6 +1594,17 @@ static void coherency_setup(void)
+ * silly idea of putting something else there ...
+ */
+ switch (current_cpu_type()) {
++ case CPU_BMIPS3300:
++ {
++ u32 cm;
++ cm = read_c0_diag();
++ /* Enable icache */
++ cm |= (1 << 31);
++ /* Enable dcache */
++ cm |= (1 << 30);
++ write_c0_diag(cm);
++ }
++ break;
+ case CPU_R4000PC:
+ case CPU_R4000SC:
+ case CPU_R4000MC:
+@@ -1626,6 +1651,15 @@ void r4k_cache_init(void)
+ extern void build_copy_page(void);
+ struct cpuinfo_mips *c = ¤t_cpu_data;
+
++ /* Check if special workarounds are required */
++#ifdef CONFIG_BCM47XX
++ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
++ printk("Enabling BCM4710A0 cache workarounds.\n");
++ bcm4710 = 1;
++ } else
++#endif
++ bcm4710 = 0;
++
+ probe_pcache();
+ setup_scache();
+
+@@ -1695,7 +1729,15 @@ void r4k_cache_init(void)
+ */
+ local_r4k___flush_cache_all(NULL);
+
++#ifdef CONFIG_BCM47XX
++ {
++ static void (*_coherency_setup)(void);
++ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
++ _coherency_setup();
++ }
++#else
+ coherency_setup();
++#endif
+ board_cache_error_setup = r4k_cache_error_setup;
+
+ /*
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -1286,6 +1286,9 @@ static void build_r4000_tlb_refill_handl
+ /* No need for uasm_i_nop */
+ }
+
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(&p);
++#endif
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
+ #else
+@@ -1848,6 +1851,9 @@ build_r4000_tlbchange_handler_head(u32 *
+ {
+ struct work_registers wr = build_get_work_registers(p);
+
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++#endif
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
+ #else
--- /dev/null
+--- a/arch/mips/include/asm/cpu-features.h
++++ b/arch/mips/include/asm/cpu-features.h
+@@ -154,6 +154,9 @@
+ #ifndef cpu_has_local_ebase
+ #define cpu_has_local_ebase 1
+ #endif
++#ifndef cpu_use_kmap_coherent
++#define cpu_use_kmap_coherent 1
++#endif
+
+ /*
+ * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
+--- a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
++++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
+@@ -79,4 +79,6 @@
+ #define cpu_scache_line_size() 0
+ #define cpu_has_vz 0
+
++#define cpu_use_kmap_coherent 0
++
+ #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -591,7 +591,7 @@ static inline void local_r4k_flush_cache
+ */
+ map_coherent = (cpu_has_dc_aliases &&
+ page_mapped(page) && !Page_dcache_dirty(page));
+- if (map_coherent)
++ if (map_coherent && cpu_use_kmap_coherent)
+ vaddr = kmap_coherent(page, addr);
+ else
+ vaddr = kmap_atomic(page);
+@@ -616,7 +616,7 @@ static inline void local_r4k_flush_cache
+ }
+
+ if (vaddr) {
+- if (map_coherent)
++ if (map_coherent && cpu_use_kmap_coherent)
+ kunmap_coherent();
+ else
+ kunmap_atomic(vaddr);
+--- a/arch/mips/mm/init.c
++++ b/arch/mips/mm/init.c
+@@ -155,7 +155,7 @@ void copy_user_highpage(struct page *to,
+ void *vfrom, *vto;
+
+ vto = kmap_atomic(to);
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ page_mapped(from) && !Page_dcache_dirty(from)) {
+ vfrom = kmap_coherent(from, vaddr);
+ copy_page(vto, vfrom);
+@@ -177,7 +177,7 @@ void copy_to_user_page(struct vm_area_st
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
+ {
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ page_mapped(page) && !Page_dcache_dirty(page)) {
+ void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ memcpy(vto, src, len);
+@@ -195,7 +195,7 @@ void copy_from_user_page(struct vm_area_
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
+ {
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ page_mapped(page) && !Page_dcache_dirty(page)) {
+ void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ memcpy(dst, vfrom, len);
--- /dev/null
+From b36f694256f41bc71571f467646d015dda128d14 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Sat, 9 Nov 2013 17:03:59 +0100
+Subject: [PATCH 210/210] b44: register adm switch
+
+---
+ drivers/net/ethernet/broadcom/b44.c | 57 +++++++++++++++++++++++++++++++++++
+ drivers/net/ethernet/broadcom/b44.h | 3 ++
+ 2 files changed, 60 insertions(+)
+
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -31,6 +31,8 @@
+ #include <linux/ssb/ssb.h>
+ #include <linux/slab.h>
+ #include <linux/phy.h>
++#include <linux/platform_device.h>
++#include <linux/platform_data/adm6996-gpio.h>
+
+ #include <asm/uaccess.h>
+ #include <asm/io.h>
+@@ -2240,6 +2242,70 @@ static void b44_adjust_link(struct net_d
+ }
+ }
+
++#ifdef CONFIG_BCM47XX
++static int b44_register_adm_switch(struct b44 *bp)
++{
++ int gpio;
++ struct platform_device *pdev;
++ struct adm6996_gpio_platform_data adm_data = {0};
++ struct platform_device_info info = {0};
++
++ adm_data.model = ADM6996L;
++ gpio = bcm47xx_nvram_gpio_pin("adm_eecs");
++ if (gpio >= 0)
++ adm_data.eecs = gpio;
++ else
++ adm_data.eecs = 2;
++
++ gpio = bcm47xx_nvram_gpio_pin("adm_eesk");
++ if (gpio >= 0)
++ adm_data.eesk = gpio;
++ else
++ adm_data.eesk = 3;
++
++ gpio = bcm47xx_nvram_gpio_pin("adm_eedi");
++ if (gpio >= 0)
++ adm_data.eedi = gpio;
++ else
++ adm_data.eedi = 4;
++
++ gpio = bcm47xx_nvram_gpio_pin("adm_rc");
++ if (gpio >= 0)
++ adm_data.eerc = gpio;
++ else
++ adm_data.eerc = 5;
++
++ info.parent = bp->sdev->dev;
++ info.name = "adm6996_gpio";
++ info.id = -1;
++ info.data = &adm_data;
++ info.size_data = sizeof(adm_data);
++
++ if (!bp->adm_switch) {
++ pdev = platform_device_register_full(&info);
++ if (IS_ERR(pdev))
++ return PTR_ERR(pdev);
++
++ bp->adm_switch = pdev;
++ }
++ return 0;
++}
++static void b44_unregister_adm_switch(struct b44 *bp)
++{
++ if (bp->adm_switch)
++ platform_device_unregister(bp->adm_switch);
++}
++#else
++static int b44_register_adm_switch(struct b44 *bp)
++{
++ return 0;
++}
++static void b44_unregister_adm_switch(struct b44 *bp)
++{
++
++}
++#endif /* CONFIG_BCM47XX */
++
+ static int b44_register_phy_one(struct b44 *bp)
+ {
+ struct mii_bus *mii_bus;
+@@ -2283,6 +2349,9 @@ static int b44_register_phy_one(struct b
+ if (!bp->mii_bus->phy_map[bp->phy_addr] &&
+ (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
+
++ if (sprom->boardflags_lo & B44_BOARDFLAG_ADM)
++ b44_register_adm_switch(bp);
++
+ dev_info(sdev->dev,
+ "could not find PHY at %i, use fixed one\n",
+ bp->phy_addr);
+@@ -2478,6 +2547,7 @@ static void b44_remove_one(struct ssb_de
+ unregister_netdev(dev);
+ if (bp->flags & B44_FLAG_EXTERNAL_PHY)
+ b44_unregister_phy_one(bp);
++ b44_unregister_adm_switch(bp);
+ ssb_device_disable(sdev, 0);
+ ssb_bus_may_powerdown(sdev->bus);
+ free_netdev(dev);
+--- a/drivers/net/ethernet/broadcom/b44.h
++++ b/drivers/net/ethernet/broadcom/b44.h
+@@ -404,6 +404,9 @@ struct b44 {
+ struct mii_bus *mii_bus;
+ int old_link;
+ struct mii_if_info mii_if;
++
++ /* platform device for associated switch */
++ struct platform_device *adm_switch;
+ };
+
+ #endif /* _B44_H */
--- /dev/null
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -431,10 +431,34 @@ static void b44_wap54g10_workaround(stru
+ error:
+ pr_warn("PHY: cannot reset MII transceiver isolate bit\n");
+ }
++
++static void b44_bcm47xx_workarounds(struct b44 *bp)
++{
++ char buf[20];
++ struct ssb_device *sdev = bp->sdev;
++
++ /* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */
++ if (sdev->bus->sprom.board_num == 100) {
++ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
++ } else {
++ /* WL-HDD */
++ if (bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf)) >= 0 &&
++ !strncmp(buf, "WL300-", strlen("WL300-"))) {
++ if (sdev->bus->sprom.et0phyaddr == 0 &&
++ sdev->bus->sprom.et1phyaddr == 1)
++ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
++ }
++ }
++ return;
++}
+ #else
+ static inline void b44_wap54g10_workaround(struct b44 *bp)
+ {
+ }
++
++static inline void b44_bcm47xx_workarounds(struct b44 *bp)
++{
++}
+ #endif
+
+ static int b44_setup_phy(struct b44 *bp)
+@@ -443,6 +467,7 @@ static int b44_setup_phy(struct b44 *bp)
+ int err;
+
+ b44_wap54g10_workaround(bp);
++ b44_bcm47xx_workarounds(bp);
+
+ if (bp->flags & B44_FLAG_EXTERNAL_PHY)
+ return 0;
+@@ -2170,6 +2195,8 @@ static int b44_get_invariants(struct b44
+ * valid PHY address. */
+ bp->phy_addr &= 0x1F;
+
++ b44_bcm47xx_workarounds(bp);
++
+ memcpy(bp->dev->dev_addr, addr, ETH_ALEN);
+
+ if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
--- /dev/null
+This prevents the options from being delete with make kernel_oldconfig.
+---
+ drivers/ssb/Kconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/bcma/Kconfig
++++ b/drivers/bcma/Kconfig
+@@ -39,6 +39,7 @@ config BCMA_DRIVER_PCI_HOSTMODE
+ config BCMA_HOST_SOC
+ bool "Support for BCMA in a SoC"
+ depends on BCMA
++ select USB_HCD_BCMA if USB_EHCI_HCD || USB_OHCI_HCD
+ help
+ Host interface for a Broadcom AIX bus directly mapped into
+ the memory. This only works with the Broadcom SoCs from the
+--- a/drivers/ssb/Kconfig
++++ b/drivers/ssb/Kconfig
+@@ -146,6 +146,7 @@ config SSB_SFLASH
+ config SSB_EMBEDDED
+ bool
+ depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
++ select USB_HCD_SSB if USB_EHCI_HCD || USB_OHCI_HCD
+ default y
+
+ config SSB_DRIVER_EXTIF
--- /dev/null
+--- a/arch/mips/include/asm/cacheflush.h
++++ b/arch/mips/include/asm/cacheflush.h
+@@ -32,7 +32,7 @@
+ extern void (*flush_cache_all)(void);
+ extern void (*__flush_cache_all)(void);
+ extern void (*flush_cache_mm)(struct mm_struct *mm);
+-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
++#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+ extern void (*flush_cache_range)(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end);
+ extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
--- /dev/null
+--- a/arch/mips/include/asm/page.h
++++ b/arch/mips/include/asm/page.h
+@@ -71,6 +71,7 @@ static inline unsigned int page_size_ftl
+ #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
+
+ #include <linux/pfn.h>
++#include <asm/cpu-features.h>
+
+ extern void build_clear_page(void);
+ extern void build_copy_page(void);
+@@ -105,13 +106,16 @@ static inline void clear_user_page(void
+ flush_data_cache_page((unsigned long)addr);
+ }
+
+-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+- struct page *to);
+-struct vm_area_struct;
+-extern void copy_user_highpage(struct page *to, struct page *from,
+- unsigned long vaddr, struct vm_area_struct *vma);
++static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
++ struct page *to)
++{
++ extern void (*flush_data_cache_page)(unsigned long addr);
+
+-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
++ copy_page(vto, vfrom);
++ if (!cpu_has_ic_fills_f_dc ||
++ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
++ flush_data_cache_page((unsigned long)vto);
++}
+
+ /*
+ * These are used to make use of C type-checking..
+--- a/arch/mips/mm/init.c
++++ b/arch/mips/mm/init.c
+@@ -149,30 +149,6 @@ void kunmap_coherent(void)
+ pagefault_enable();
+ }
+
+-void copy_user_highpage(struct page *to, struct page *from,
+- unsigned long vaddr, struct vm_area_struct *vma)
+-{
+- void *vfrom, *vto;
+-
+- vto = kmap_atomic(to);
+- if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+- page_mapped(from) && !Page_dcache_dirty(from)) {
+- vfrom = kmap_coherent(from, vaddr);
+- copy_page(vto, vfrom);
+- kunmap_coherent();
+- } else {
+- vfrom = kmap_atomic(from);
+- copy_page(vto, vfrom);
+- kunmap_atomic(vfrom);
+- }
+- if ((!cpu_has_ic_fills_f_dc) ||
+- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+- flush_data_cache_page((unsigned long)vto);
+- kunmap_atomic(vto);
+- /* Make sure this page is cleared on other CPU's too before using it */
+- smp_wmb();
+-}
+-
+ void copy_to_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
--- /dev/null
+--- a/arch/mips/bcm47xx/board.c
++++ b/arch/mips/bcm47xx/board.c
+@@ -140,6 +140,7 @@ struct bcm47xx_board_type_list2 bcm47xx_
+ {{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"},
+ {{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"},
+ {{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"},
++ {{BCM47XX_BOARD_LINKSYS_WRT320N_V1, "Linksys WRT320N V1"}, "WRT320N", "1.0"},
+ {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
+ {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
+ {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
+--- a/arch/mips/bcm47xx/buttons.c
++++ b/arch/mips/bcm47xx/buttons.c
+@@ -270,6 +270,18 @@ bcm47xx_buttons_linksys_wrt310nv1[] __in
+ };
+
+ static const struct gpio_keys_button
++bcm47xx_buttons_linksys_wrt310n_v2[] __initconst = {
++ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
++ BCM47XX_GPIO_KEY(6, KEY_RESTART),
++};
++
++static const struct gpio_keys_button
++bcm47xx_buttons_linksys_wrt320n_v1[] __initconst = {
++ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
++ BCM47XX_GPIO_KEY(8, KEY_RESTART),
++};
++
++static const struct gpio_keys_button
+ bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = {
+ BCM47XX_GPIO_KEY(5, KEY_WIMAX),
+ BCM47XX_GPIO_KEY(6, KEY_RESTART),
+@@ -537,6 +549,12 @@ int __init bcm47xx_buttons_register(void
+ case BCM47XX_BOARD_LINKSYS_WRT310NV1:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
+ break;
++ case BCM47XX_BOARD_LINKSYS_WRT310NV2:
++ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2);
++ break;
++ case BCM47XX_BOARD_LINKSYS_WRT320N_V1:
++ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1);
++ break;
+ case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);
+ break;
+--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+@@ -71,6 +71,7 @@ enum bcm47xx_board {
+ BCM47XX_BOARD_LINKSYS_WRT300NV11,
+ BCM47XX_BOARD_LINKSYS_WRT310NV1,
+ BCM47XX_BOARD_LINKSYS_WRT310NV2,
++ BCM47XX_BOARD_LINKSYS_WRT320N_V1,
+ BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
+ BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
+ BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
+--- a/arch/mips/bcm47xx/leds.c
++++ b/arch/mips/bcm47xx/leds.c
+@@ -313,6 +313,13 @@ bcm47xx_leds_linksys_wrt310nv1[] __initc
+ };
+
+ static const struct gpio_led
++bcm47xx_leds_linksys_wrt320n_v1[] __initconst = {
++ BCM47XX_GPIO_LED(1, "blue", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
++ BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
++ BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
++};
++
++static const struct gpio_led
+ bcm47xx_leds_linksys_wrt54g_generic[] __initconst = {
+ BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
+ BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+@@ -601,6 +608,9 @@ void __init bcm47xx_leds_register(void)
+ case BCM47XX_BOARD_LINKSYS_WRT310NV1:
+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
+ break;
++ case BCM47XX_BOARD_LINKSYS_WRT320N_V1:
++ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt320n_v1);
++ break;
+ case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2);
+ break;
--- /dev/null
+--- a/drivers/mtd/bcm47xxpart.c
++++ b/drivers/mtd/bcm47xxpart.c
+@@ -97,6 +97,7 @@ static int bcm47xxpart_parse(struct mtd_
+ int trx_part = -1;
+ int last_trx_part = -1;
+ int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, };
++ bool found_nvram = false;
+
+ /*
+ * Some really old flashes (like AT45DB*) had smaller erasesize-s, but
+@@ -300,12 +301,23 @@ static int bcm47xxpart_parse(struct mtd_
+ if (buf[0] == NVRAM_HEADER) {
+ bcm47xxpart_add_part(&parts[curr_part++], "nvram",
+ master->size - blocksize, 0);
++ found_nvram = true;
+ break;
+ }
+ }
+
+ kfree(buf);
+
++ if (!found_nvram) {
++ pr_err("can not find a nvram partition reserve last block\n");
++ bcm47xxpart_add_part(&parts[curr_part++], "nvram_guess",
++ master->size - blocksize * 2, MTD_WRITEABLE);
++ for (i = 0; i < curr_part; i++) {
++ if (parts[i].size + parts[i].offset == master->size)
++ parts[i].offset -= blocksize * 2;
++ }
++ }
++
+ /*
+ * Assume that partitions end at the beginning of the one they are
+ * followed by.
--- /dev/null
+--- a/include/linux/ide.h
++++ b/include/linux/ide.h
+@@ -191,7 +191,11 @@ static inline void ide_std_init_ports(st
+ hw->io_ports.ctl_addr = ctl_addr;
+ }
+
++#if defined CONFIG_BCM47XX
++# define MAX_HWIFS 2
++#else
+ #define MAX_HWIFS 10
++#endif
+
+ /*
+ * Now for the data we need to maintain per-drive: ide_drive_t
--- /dev/null
+When the Ethernet controller is powered down and someone wants to
+access the mdio bus like the witch driver (b53) the system crashed if
+PCI_D3hot was set before. This patch deactivates this power sawing mode
+when a switch driver is in use.
+
+--- a/drivers/net/ethernet/broadcom/tg3.c
++++ b/drivers/net/ethernet/broadcom/tg3.c
+@@ -4263,7 +4263,8 @@ static int tg3_power_down_prepare(struct
+ static void tg3_power_down(struct tg3 *tp)
+ {
+ pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
+- pci_set_power_state(tp->pdev, PCI_D3hot);
++ if (!tg3_flag(tp, ROBOSWITCH))
++ pci_set_power_state(tp->pdev, PCI_D3hot);
+ }
+
+ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
--- /dev/null
+From 597715c61ae75a05ab3310a34ff3857a006f0f63 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Thu, 20 Nov 2014 21:32:42 +0100
+Subject: [PATCH] bcma: add table of serial flashes with smaller blocks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+ drivers/bcma/driver_chipcommon_sflash.c | 29 +++++++++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+--- a/drivers/bcma/driver_chipcommon_sflash.c
++++ b/drivers/bcma/driver_chipcommon_sflash.c
+@@ -9,6 +9,7 @@
+
+ #include <linux/platform_device.h>
+ #include <linux/bcma/bcma.h>
++#include <bcm47xx_board.h>
+
+ static struct resource bcma_sflash_resource = {
+ .name = "bcma_sflash",
+@@ -41,6 +42,13 @@ static const struct bcma_sflash_tbl_e bc
+ { NULL },
+ };
+
++/* Some devices use smaller blocks (and have more of them) */
++static const struct bcma_sflash_tbl_e bcma_sflash_st_shrink_tbl[] = {
++ { "M25P16", 0x14, 0x1000, 512, },
++ { "M25P32", 0x15, 0x1000, 1024, },
++ { NULL },
++};
++
+ static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
+ { "SST25WF512", 1, 0x1000, 16, },
+ { "SST25VF512", 0x48, 0x1000, 16, },
+@@ -84,6 +92,23 @@ static void bcma_sflash_cmd(struct bcma_
+ bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
+ }
+
++const struct bcma_sflash_tbl_e *bcma_sflash_shrink_flash(u32 id)
++{
++ enum bcm47xx_board board = bcm47xx_board_get();
++ const struct bcma_sflash_tbl_e *e;
++
++ switch (board) {
++ case BCM47XX_BOARD_NETGEAR_WGR614_V10:
++ for (e = bcma_sflash_st_shrink_tbl; e->name; e++) {
++ if (e->id == id)
++ return e;
++ }
++ return NULL;
++ default:
++ return NULL;
++ }
++}
++
+ /* Initialize serial flash access */
+ int bcma_sflash_init(struct bcma_drv_cc *cc)
+ {
+@@ -114,6 +139,10 @@ int bcma_sflash_init(struct bcma_drv_cc
+ case 0x13:
+ return -ENOTSUPP;
+ default:
++ e = bcma_sflash_shrink_flash(id);
++ if (e)
++ break;
++
+ for (e = bcma_sflash_st_tbl; e->name; e++) {
+ if (e->id == id)
+ break;
--- /dev/null
+The Netgear wgt634u uses a different format for storing the
+configuration. This patch is needed to read out the correct
+configuration. The cfe_env.c file uses a different method way to read
+out the configuration than the in kernel cfe config reader.
+
+--- a/arch/mips/bcm47xx/Makefile
++++ b/arch/mips/bcm47xx/Makefile
+@@ -5,3 +5,4 @@
+
+ obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
+ obj-y += board.o buttons.o leds.o workarounds.o
++obj-y += cfe_env.o
+--- /dev/null
++++ b/arch/mips/bcm47xx/cfe_env.c
+@@ -0,0 +1,228 @@
++/*
++ * CFE environment variable access
++ *
++ * Copyright 2001-2003, Broadcom Corporation
++ * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#define NVRAM_SIZE (0x1ff0)
++static char _nvdata[NVRAM_SIZE];
++static char _valuestr[256];
++
++/*
++ * TLV types. These codes are used in the "type-length-value"
++ * encoding of the items stored in the NVRAM device (flash or EEPROM)
++ *
++ * The layout of the flash/nvram is as follows:
++ *
++ * <type> <length> <data ...> <type> <length> <data ...> <type_end>
++ *
++ * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
++ * The "length" field marks the length of the data section, not
++ * including the type and length fields.
++ *
++ * Environment variables are stored as follows:
++ *
++ * <type_env> <length> <flags> <name> = <value>
++ *
++ * If bit 0 (low bit) is set, the length is an 8-bit value.
++ * If bit 0 (low bit) is clear, the length is a 16-bit value
++ *
++ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
++ * indicates the size of the length field.
++ *
++ * Flags are from the constants below:
++ *
++ */
++#define ENV_LENGTH_16BITS 0x00 /* for low bit */
++#define ENV_LENGTH_8BITS 0x01
++
++#define ENV_TYPE_USER 0x80
++
++#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
++#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
++
++/*
++ * The actual TLV types we support
++ */
++
++#define ENV_TLV_TYPE_END 0x00
++#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
++
++/*
++ * Environment variable flags
++ */
++
++#define ENV_FLG_NORMAL 0x00 /* normal read/write */
++#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
++#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
++
++#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
++#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
++
++
++/* *********************************************************************
++ * _nvram_read(buffer,offset,length)
++ *
++ * Read data from the NVRAM device
++ *
++ * Input parameters:
++ * buffer - destination buffer
++ * offset - offset of data to read
++ * length - number of bytes to read
++ *
++ * Return value:
++ * number of bytes read, or <0 if error occured
++ ********************************************************************* */
++static int
++_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
++{
++ int i;
++ if (offset > NVRAM_SIZE)
++ return -1;
++
++ for ( i = 0; i < length; i++) {
++ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
++ }
++ return length;
++}
++
++
++static char*
++_strnchr(const char *dest,int c,size_t cnt)
++{
++ while (*dest && (cnt > 0)) {
++ if (*dest == c) return (char *) dest;
++ dest++;
++ cnt--;
++ }
++ return NULL;
++}
++
++
++
++/*
++ * Core support API: Externally visible.
++ */
++
++/*
++ * Get the value of an NVRAM variable
++ * @param name name of variable to get
++ * @return value of variable or NULL if undefined
++ */
++
++char *cfe_env_get(unsigned char *nv_buf, const char *name)
++{
++ int size;
++ unsigned char *buffer;
++ unsigned char *ptr;
++ unsigned char *envval;
++ unsigned int reclen;
++ unsigned int rectype;
++ int offset;
++ int flg;
++
++ if (!strcmp(name, "nvram_type"))
++ return "cfe";
++
++ size = NVRAM_SIZE;
++ buffer = &_nvdata[0];
++
++ ptr = buffer;
++ offset = 0;
++
++ /* Read the record type and length */
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
++ goto error;
++ }
++
++ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
++
++ /* Adjust pointer for TLV type */
++ rectype = *(ptr);
++ offset++;
++ size--;
++
++ /*
++ * Read the length. It can be either 1 or 2 bytes
++ * depending on the code
++ */
++ if (rectype & ENV_LENGTH_8BITS) {
++ /* Read the record type and length - 8 bits */
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
++ goto error;
++ }
++ reclen = *(ptr);
++ size--;
++ offset++;
++ }
++ else {
++ /* Read the record type and length - 16 bits, MSB first */
++ if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
++ goto error;
++ }
++ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
++ size -= 2;
++ offset += 2;
++ }
++
++ if (reclen > size)
++ break; /* should not happen, bad NVRAM */
++
++ switch (rectype) {
++ case ENV_TLV_TYPE_ENV:
++ /* Read the TLV data */
++ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
++ goto error;
++ flg = *ptr++;
++ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
++ if (envval) {
++ *envval++ = '\0';
++ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
++ _valuestr[(reclen-1)-(envval-ptr)] = '\0';
++#if 0
++ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
++#endif
++ if(!strcmp(ptr, name)){
++ return _valuestr;
++ }
++ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
++ return _valuestr;
++ }
++ break;
++
++ default:
++ /* Unknown TLV type, skip it. */
++ break;
++ }
++
++ /*
++ * Advance to next TLV
++ */
++
++ size -= (int)reclen;
++ offset += reclen;
++
++ /* Read the next record type */
++ ptr = buffer;
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1)
++ goto error;
++ }
++
++error:
++ return NULL;
++
++}
++
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -36,6 +36,8 @@ struct nvram_header {
+
+ static char nvram_buf[NVRAM_SPACE];
+ static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
++static int cfe_env;
++extern char *cfe_env_get(char *nv_buf, const char *name);
+
+ static u32 find_nvram_size(void __iomem *end)
+ {
+@@ -65,6 +67,26 @@ static int nvram_find_and_copy(void __io
+ return -EEXIST;
+ }
+
++ cfe_env = 0;
++
++ /* XXX: hack for supporting the CFE environment stuff on WGT634U */
++ if (lim >= 8 * 1024 * 1024) {
++ src = (u32 *) iobase + 8 * 1024 * 1024 - 0x2000;
++ dst = (u32 *) nvram_buf;
++
++ if ((*src & 0xff00ff) == 0x000001) {
++ printk("early_nvram_init: WGT634U NVRAM found.\n");
++
++ for (i = 0; i < 0x1ff0; i++) {
++ if (*src == 0xFFFFFFFF)
++ break;
++ *dst++ = *src++;
++ }
++ cfe_env = 1;
++ return 0;
++ }
++ }
++
+ /* TODO: when nvram is on nand flash check for bad blocks first. */
+ off = FLASH_MIN;
+ while (off <= lim) {
+@@ -181,6 +203,13 @@ int bcm47xx_nvram_getenv(const char *nam
+ return err;
+ }
+
++ if (cfe_env) {
++ value = cfe_env_get(nvram_buf, name);
++ if (!value)
++ return -ENOENT;
++ return snprintf(val, val_len, "%s", value);
++ }
++
+ /* Look for name=value and return value */
+ var = &nvram_buf[sizeof(struct nvram_header)];
+ end = nvram_buf + sizeof(nvram_buf) - 2;
--- /dev/null
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -36,6 +36,7 @@
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
+ #include <linux/bcma/bcma_soc.h>
++#include <linux/old_gpio_wdt.h>
+ #include <asm/bootinfo.h>
+ #include <asm/idle.h>
+ #include <asm/prom.h>
+@@ -248,6 +249,33 @@ static struct fixed_phy_status bcm47xx_f
+ .duplex = DUPLEX_FULL,
+ };
+
++static struct gpio_wdt_platform_data gpio_wdt_data;
++
++static struct platform_device gpio_wdt_device = {
++ .name = "gpio-wdt",
++ .id = 0,
++ .dev = {
++ .platform_data = &gpio_wdt_data,
++ },
++};
++
++static int __init bcm47xx_register_gpio_watchdog(void)
++{
++ enum bcm47xx_board board = bcm47xx_board_get();
++
++ switch (board) {
++ case BCM47XX_BOARD_HUAWEI_E970:
++ pr_info("bcm47xx: detected Huawei E970 or similar, starting early gpio_wdt timer\n");
++ gpio_wdt_data.gpio = 7;
++ gpio_wdt_data.interval = HZ;
++ gpio_wdt_data.first_interval = HZ / 5;
++ return platform_device_register(&gpio_wdt_device);
++ default:
++ /* Nothing to do */
++ return 0;
++ }
++}
++
+ static int __init bcm47xx_register_bus_complete(void)
+ {
+ switch (bcm47xx_bus_type) {
+@@ -267,6 +295,7 @@ static int __init bcm47xx_register_bus_c
+ bcm47xx_workarounds();
+
+ fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
++ bcm47xx_register_gpio_watchdog();
+ return 0;
+ }
+ device_initcall(bcm47xx_register_bus_complete);
+--- a/arch/mips/configs/bcm47xx_defconfig
++++ b/arch/mips/configs/bcm47xx_defconfig
+@@ -67,6 +67,7 @@ CONFIG_HW_RANDOM=y
+ CONFIG_GPIO_SYSFS=y
+ CONFIG_WATCHDOG=y
+ CONFIG_BCM47XX_WDT=y
++CONFIG_GPIO_WDT=y
+ CONFIG_SSB_DEBUG=y
+ CONFIG_SSB_DRIVER_GIGE=y
+ CONFIG_BCMA_DRIVER_GMAC_CMN=y
+--- a/drivers/ssb/embedded.c
++++ b/drivers/ssb/embedded.c
+@@ -34,11 +34,36 @@ int ssb_watchdog_timer_set(struct ssb_bu
+ }
+ EXPORT_SYMBOL(ssb_watchdog_timer_set);
+
++#ifdef CONFIG_BCM47XX
++#include <bcm47xx_board.h>
++
++static bool ssb_watchdog_supported(void)
++{
++ enum bcm47xx_board board = bcm47xx_board_get();
++
++ /* The Huawei E970 has a hardware watchdog using a GPIO */
++ switch (board) {
++ case BCM47XX_BOARD_HUAWEI_E970:
++ return false;
++ default:
++ return true;
++ }
++}
++#else
++static bool ssb_watchdog_supported(void)
++{
++ return true;
++}
++#endif
++
+ int ssb_watchdog_register(struct ssb_bus *bus)
+ {
+ struct bcm47xx_wdt wdt = {};
+ struct platform_device *pdev;
+
++ if (!ssb_watchdog_supported())
++ return 0;
++
+ if (ssb_chipco_available(&bus->chipco)) {
+ wdt.driver_data = &bus->chipco;
+ wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
--- /dev/null
+From 5c81397a0147ea59c778d1de14ef54e2268221f6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 8 Apr 2015 06:58:11 +0200
+Subject: [PATCH] ssb: reject PCI writes setting CardBus bridge resources
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+If SoC has a CardBus we can set resources of device at slot 1 only. It's
+impossigle to set bridge resources as it simply overwrites device 1
+configuration and usually results in Data bus error-s.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+ drivers/ssb/driver_pcicore.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c
+index 15a7ee3..c603d19 100644
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -164,6 +164,10 @@ static int ssb_extpci_write_config(struct ssb_pcicore *pc,
+ SSB_WARN_ON(!pc->hostmode);
+ if (unlikely(len != 1 && len != 2 && len != 4))
+ goto out;
++ /* CardBus SoCs allow configuring dev 1 resources only */
++ if (extpci_core->cardbusmode && dev != 1 &&
++ off >= PCI_BASE_ADDRESS_0 && off <= PCI_BASE_ADDRESS_5)
++ goto out;
+ addr = get_cfgspace_addr(pc, bus, dev, func, off);
+ if (unlikely(!addr))
+ goto out;
+--
+1.8.4.5
+
--- /dev/null
+--- a/arch/mips/include/asm/r4kcache.h
++++ b/arch/mips/include/asm/r4kcache.h
+@@ -26,10 +26,28 @@ extern void (*r4k_blast_icache)(void);
+ #ifdef CONFIG_BCM47XX
+ #include <asm/paccess.h>
+ #include <linux/ssb/ssb.h>
+-#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
++#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
++
++static inline unsigned long bcm4710_dummy_rreg(void)
++{
++ return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
++}
++
++#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
++
++static inline unsigned long bcm4710_fill_tlb(void *addr)
++{
++ return *(unsigned long *)addr;
++}
++
++#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
++
++static inline void bcm4710_protected_fill_tlb(void *addr)
++{
++ unsigned long x;
++ get_dbe(x, (unsigned long *)addr);;
++}
+
+-#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
+-#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
+ #else
+ #define BCM4710_DUMMY_RREG()
+
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -941,6 +941,9 @@ build_get_pgde32(u32 **p, unsigned int t
+ uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
+ uasm_i_addu(p, ptr, tmp, ptr);
+ #else
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++#endif
+ UASM_i_LA_mostly(p, ptr, pgdc);
+ #endif
+ uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
+@@ -1286,12 +1289,12 @@ static void build_r4000_tlb_refill_handl
+ /* No need for uasm_i_nop */
+ }
+
+-#ifdef CONFIG_BCM47XX
+- uasm_i_nop(&p);
+-#endif
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
+ #else
++# ifdef CONFIG_BCM47XX
++ uasm_i_nop(&p);
++# endif
+ build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
+ #endif
+
+@@ -1303,6 +1306,9 @@ static void build_r4000_tlb_refill_handl
+ build_update_entries(&p, K0, K1);
+ build_tlb_write_entry(&p, &l, &r, tlb_random);
+ uasm_l_leave(&l, p);
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(&p);
++#endif
+ uasm_i_eret(&p); /* return from trap */
+ }
+ #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+@@ -1851,12 +1857,12 @@ build_r4000_tlbchange_handler_head(u32 *
+ {
+ struct work_registers wr = build_get_work_registers(p);
+
+-#ifdef CONFIG_BCM47XX
+- uasm_i_nop(p);
+-#endif
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
+ #else
++# ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++# endif
+ build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
+ #endif
+
+@@ -1903,6 +1909,9 @@ build_r4000_tlbchange_handler_tail(u32 *
+ build_tlb_write_entry(p, l, r, tlb_indexed);
+ uasm_l_leave(l, *p);
+ build_restore_work_registers(p);
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++#endif
+ uasm_i_eret(p); /* return from trap */
+
+ #ifdef CONFIG_64BIT
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
+@@ -21,6 +21,19 @@
+ #include <asm/war.h>
+ #include <asm/thread_info.h>
+
++#ifdef CONFIG_BCM47XX
++# ifdef eret
++# undef eret
++# endif
++# define eret \
++ .set push; \
++ .set noreorder; \
++ nop; \
++ nop; \
++ eret; \
++ .set pop;
++#endif
++
+ __INIT
+
+ /*
+@@ -34,7 +47,6 @@ NESTED(except_vec3_generic, 0, sp)
+ .set noat
+ #ifdef CONFIG_BCM47XX
+ nop
+- nop
+ #endif
+ #if R5432_CP0_INTERRUPT_WAR
+ mfc0 k0, CP0_INDEX
+@@ -59,6 +71,9 @@ NESTED(except_vec3_r4000, 0, sp)
+ .set push
+ .set arch=r4000
+ .set noat
++#ifdef CONFIG_BCM47XX
++ nop
++#endif
+ mfc0 k1, CP0_CAUSE
+ li k0, 31<<2
+ andi k1, k1, 0x7c
--- /dev/null
+--- a/drivers/pcmcia/yenta_socket.c
++++ b/drivers/pcmcia/yenta_socket.c
+@@ -920,6 +920,8 @@ static unsigned int yenta_probe_irq(stru
+ * Probe for usable interrupts using the force
+ * register to generate bogus card status events.
+ */
++#ifndef CONFIG_BCM47XX
++ /* WRT54G3G does not like this */
+ cb_writel(socket, CB_SOCKET_EVENT, -1);
+ cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
+ reg = exca_readb(socket, I365_CSCINT);
+@@ -935,6 +937,7 @@ static unsigned int yenta_probe_irq(stru
+ }
+ cb_writel(socket, CB_SOCKET_MASK, 0);
+ exca_writeb(socket, I365_CSCINT, reg);
++#endif
+
+ mask = probe_irq_mask(val) & 0xffff;
+
+@@ -1019,6 +1022,10 @@ static void yenta_get_socket_capabilitie
+ else
+ socket->socket.irq_mask = 0;
+
++ /* irq mask probing is broken for the WRT54G3G */
++ if (socket->socket.irq_mask == 0)
++ socket->socket.irq_mask = 0x6f8;
++
+ dev_printk(KERN_INFO, &socket->dev->dev,
+ "ISA IRQ mask 0x%04x, PCI irq %d\n",
+ socket->socket.irq_mask, socket->cb_irq);
+@@ -1257,6 +1264,15 @@ static int yenta_probe(struct pci_dev *d
+ dev_printk(KERN_INFO, &dev->dev,
+ "Socket status: %08x\n", cb_readl(socket, CB_SOCKET_STATE));
+
++ /* Generate an interrupt on card insert/remove */
++ config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);
++
++ /* Set up Multifunction Routing Status Register */
++ config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);
++
++ /* Switch interrupts to parallelized */
++ config_writeb(socket, 0x92, 0x64);
++
+ yenta_fixup_parent_bridge(dev->subordinate);
+
+ /* Register it with the pcmcia layer.. */
--- /dev/null
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -388,7 +388,7 @@ static void ssb_pcicore_init_hostmode(st
+ set_io_port_base(ssb_pcicore_controller.io_map_base);
+ /* Give some time to the PCI controller to configure itself with the new
+ * values. Not waiting at this point causes crashes of the machine. */
+- mdelay(10);
++ mdelay(300);
+ register_pci_controller(&ssb_pcicore_controller);
+ }
+
--- /dev/null
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -34,7 +34,8 @@ struct nvram_header {
+ u32 config_ncdl; /* ncdl values for memc */
+ };
+
+-static char nvram_buf[NVRAM_SPACE];
++char nvram_buf[NVRAM_SPACE];
++EXPORT_SYMBOL(nvram_buf);
+ static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
+ static int cfe_env;
+ extern char *cfe_env_get(char *nv_buf, const char *name);
+--- a/arch/mips/mm/cache.c
++++ b/arch/mips/mm/cache.c
+@@ -59,6 +59,7 @@ void (*_dma_cache_wback)(unsigned long s
+ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+
+ EXPORT_SYMBOL(_dma_cache_wback_inv);
++EXPORT_SYMBOL(_dma_cache_inv);
+
+ #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
+
projects / openwrt / staging / dangole.git / commitdiff