* and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */
struct iwl3945_shared {
__le32 tx_base_ptr[8];
- __le32 rx_read_ptr[3];
} __attribute__ ((packed));
struct iwl3945_tfd_frame_data {
}
iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
- iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
- priv->shared_phys +
- offsetof(struct iwl3945_shared, rx_read_ptr[0]));
+ iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
return 0;
}
-int iwl3945_hw_get_rx_read(struct iwl_priv *priv)
-{
- struct iwl3945_shared *shared_data = priv->shared_virt;
-
- return le32_to_cpu(shared_data->rx_read_ptr[0]);
-}
-
/**
* iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
*/
struct iwl3945_tx_queue *txq);
extern unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
struct iwl3945_frame *frame, u8 rate);
-extern int iwl3945_hw_get_rx_read(struct iwl_priv *priv);
void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
struct ieee80211_tx_info *info,
struct ieee80211_hdr *hdr,
u16 beacon_int;
struct ieee80211_vif *vif;
- /*Added for 3945 */
+ /*Added for 3945 */
void *shared_virt;
dma_addr_t shared_phys;
/*End*/
__le16 closed_fr_num;
__le16 finished_rb_num;
__le16 finished_fr_nam;
+ __le32 __unused; /* 3945 only */
} __attribute__ ((packed));
/* uCode's read index (stored in shared DRAM) indicates the last Rx
* buffer that the driver may process (last buffer filled by ucode). */
- r = iwl3945_hw_get_rx_read(priv);
+ r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
i = rxq->read;
if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))