octeontx2-af: Clear NPC MCAM entries before update

Writing into NPC MCAM1 and MCAM0 registers are suppressed if
they happened to form a reserved combination. Hence
clear and disable MCAM entries before update.

For HRM:
[CAM(1)]<n>=1, [CAM(0)]<n>=1: Reserved.
The reserved combination is not allowed. Hardware suppresses any
write to CAM(0) or CAM(1) that would result in the reserved combination for
any CAM bit.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
index ce4472915c984b6da7882426bf19b99a335b7979..a3b43159be38e1a48d314047354abb14769d68fa 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
@@ -120,6 +120,31 @@ static void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
        }
 }
 
+static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
+                                int blkaddr, int index)
+{
+       int bank = npc_get_bank(mcam, index);
+       int actbank = bank;
+
+       index &= (mcam->banksize - 1);
+       for (; bank < (actbank + mcam->banks_per_entry); bank++) {
+               rvu_write64(rvu, blkaddr,
+                           NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0);
+               rvu_write64(rvu, blkaddr,
+                           NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0);
+
+               rvu_write64(rvu, blkaddr,
+                           NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0);
+               rvu_write64(rvu, blkaddr,
+                           NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0);
+
+               rvu_write64(rvu, blkaddr,
+                           NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0);
+               rvu_write64(rvu, blkaddr,
+                           NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0);
+       }
+}
+
 static void npc_get_keyword(struct mcam_entry *entry, int idx,
                            u64 *cam0, u64 *cam1)
 {
@@ -211,6 +236,12 @@ static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
        actindex = index;
        index &= (mcam->banksize - 1);
 
+       /* Disable before mcam entry update */
+       npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
+
+       /* Clear mcam entry to avoid writes being suppressed by NPC */
+       npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex);
+
        /* CAM1 takes the comparison value and
         * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'.
         * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0
@@ -251,8 +282,6 @@ static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
        /* Enable the entry */
        if (enable)
                npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true);
-       else
-               npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
 }
 
 static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,