SUBTARGETS:=generic
KERNEL_PATCHVER:=5.10
+KERNEL_TESTING_PATCHVER:=5.15
KERNELNAME:=zImage Image dtbs
max-link-speed = <1>;
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
status = "okay";
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
status = "okay";
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
};
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
max-link-speed = <1>;
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
};
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
status = "okay";
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
};
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
};
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
};
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
status = "okay";
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
};
};
-&nand_controller {
+&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
-@@ -322,7 +322,7 @@ config ARCH_MULTIPLATFORM
+@@ -321,7 +321,7 @@ config ARCH_MULTIPLATFORM
select ARCH_SELECT_MEMORY_MODEL
select ARM_HAS_SG_CHAIN
select ARM_PATCH_PHYS_VIRT
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
-@@ -1781,6 +1781,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+@@ -1780,6 +1780,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property.
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
-@@ -907,8 +907,29 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+@@ -955,8 +955,29 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
+ qcom-ipq8064-wxr-2533dhp.dtb \
+ qcom-ipq8065-nbg6817.dtb \
+ qcom-ipq8065-r7800.dtb \
-+ qcom-ipq8065-rt4230w-rev6.dtb \
+ qcom-ipq8065-xr500.dtb \
++ qcom-ipq8065-rt4230w-rev6.dtb \
+ qcom-ipq8068-ecw5410.dtb \
+ qcom-ipq8068-mr42.dtb \
+ qcom-ipq8068-mr52.dtb \
+ qcom-msm8226-samsung-s3ve3g.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
- qcom-msm8974-fairphone-fp2.dtb \
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
-@@ -1275,6 +1275,7 @@ static const struct of_device_id qcom_sc
+@@ -1339,6 +1339,7 @@ static const struct of_device_id qcom_sc
SCM_HAS_BUS_CLK)
},
{ .compatible = "qcom,scm-ipq4019" },
+ { .compatible = "qcom,scm-ipq806x" },
- { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
- { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
- { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
+ { .compatible = "qcom,scm-mdm9607", .data = (void *)(SCM_HAS_CORE_CLK |
+ SCM_HAS_IFACE_CLK |
+ SCM_HAS_BUS_CLK) },
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -20,7 +20,7 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-- cpu@0 {
-+ cpu0: cpu@0 {
- compatible = "qcom,krait";
- enable-method = "qcom,kpss-acc-v1";
- device_type = "cpu";
-@@ -30,7 +30,7 @@
- qcom,saw = <&saw0>;
- };
-
-- cpu@1 {
-+ cpu1: cpu@1 {
- compatible = "qcom,krait";
- enable-method = "qcom,kpss-acc-v1";
- device_type = "cpu";
-@@ -67,7 +67,7 @@
- no-map;
- };
-
-- smem@41000000 {
-+ smem: smem@41000000 {
- reg = <0x41000000 0x200000>;
- no-map;
- };
-@@ -128,6 +128,7 @@
+@@ -352,6 +352,7 @@
gpio-ranges = <&qcom_pinmux 0 0 69>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-@@ -155,6 +156,7 @@
+@@ -379,6 +380,7 @@
function = "pcie3_rst";
drive-strength = <12>;
bias-disable;
};
};
-@@ -190,6 +192,7 @@
+@@ -411,12 +413,9 @@
+ };
+
+ nand_pins: nand_pins {
+- mux {
++ disable {
+ pins = "gpio34", "gpio35", "gpio36",
+- "gpio37", "gpio38", "gpio39",
+- "gpio40", "gpio41", "gpio42",
+- "gpio43", "gpio44", "gpio45",
+- "gpio46", "gpio47";
++ "gpio37", "gpio38";
+ function = "nand";
+ drive-strength = <10>;
+ bias-disable;
+@@ -424,6 +423,8 @@
+
+ pullups {
+ pins = "gpio39";
++ function = "nand";
++ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+@@ -431,6 +432,8 @@
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
++ function = "nand";
++ drive-strength = <10>;
+ bias-bus-hold;
+ };
+ };
+@@ -439,6 +442,7 @@
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x02000000 0x1000>,
<0x02002000 0x1000>;
-@@ -219,21 +222,23 @@
+@@ -468,11 +472,13 @@
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu1_aux";
};
+ adm_dma: dma-controller@18300000 {
+@@ -496,13 +502,13 @@
+ };
+
saw0: regulator@2089000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
-@@ -251,7 +256,7 @@
-
- syscon-tcsr = <&tcsr>;
-
-- serial@12490000 {
-+ gsbi2_serial: serial@12490000 {
- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
- reg = <0x12490000 0x1000>,
- <0x12480000 0x1000>;
-@@ -261,7 +266,7 @@
+@@ -533,7 +533,7 @@
status = "disabled";
};
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
-@@ -326,7 +331,7 @@
-
- syscon-tcsr = <&tcsr>;
-
-- serial@1a240000 {
-+ gsbi5_serial: serial@1a240000 {
- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
- reg = <0x1a240000 0x1000>,
- <0x1a200000 0x1000>;
-@@ -397,7 +402,7 @@
- status = "disabled";
- };
-
-- sata@29000000 {
-+ sata: sata@29000000 {
- compatible = "qcom,ipq806x-ahci", "generic-ahci";
- reg = <0x29000000 0x180>;
-
-@@ -430,13 +435,35 @@
- reg = <0x00700000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-+
-+ tsens_calib: calib@400 {
-+ reg = <0x400 0xb>;
-+ };
-+ tsens_backup: backup@410 {
-+ reg = <0x410 0xb>;
-+ };
+@@ -676,9 +682,6 @@
+ compatible = "qcom,ipq806x-nand";
+ reg = <0x1ac00000 0x800>;
+
+- pinctrl-0 = <&nand_pins>;
+- pinctrl-names = "default";
+-
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+@@ -733,10 +736,13 @@
+ tsens_calib_backup: calib_backup@410 {
+ reg = <0x410 0xb>;
+ };
+ speedbin_efuse: speedbin@0c0 {
+ reg = <0x0c0 0x4>;
+ };
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
-+ #power-domain-cells = <1>;
+@@ -768,10 +774,45 @@
+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
+ clock-names = "ram";
+
++ #address-cells = <1>;
++ #size-cells = <0>;
++
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
++
++ regulators {
++ compatible = "qcom,rpm-smb208-regulators";
++
++ smb208_s1a: s1a {
++ regulator-min-microvolt = <1050000>;
++ regulator-max-microvolt = <1150000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
+
-+ tsens: thermal-sensor@900000 {
-+ compatible = "qcom,ipq8064-tsens";
++ smb208_s1b: s1b {
++ regulator-min-microvolt = <1050000>;
++ regulator-max-microvolt = <1150000>;
+
-+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
-+ nvmem-cell-names = "calib", "calib_backup";
-+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "uplow";
-+ #thermal-sensor-cells = <1>;
-+ #qcom,sensors = <11>;
++ qcom,switch-mode-frequency = <1200000>;
++ };
++
++ smb208_s2a: s2a {
++ regulator-min-microvolt = < 800000>;
++ regulator-max-microvolt = <1250000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
++
++ smb208_s2b: s2b {
++ regulator-min-microvolt = < 800000>;
++ regulator-max-microvolt = <1250000>;
++
++ qcom,switch-mode-frequency = <1200000>;
++ };
+ };
};
tcsr: syscon@1a400000 {
-@@ -622,7 +649,7 @@
+@@ -965,7 +1006,7 @@
gmac0: ethernet@37000000 {
device_type = "network";
reg = <0x37000000 0x200000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
-@@ -645,7 +672,7 @@
+@@ -989,7 +1030,7 @@
gmac1: ethernet@37200000 {
device_type = "network";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
-@@ -668,7 +695,7 @@
+@@ -1013,7 +1054,7 @@
gmac2: ethernet@37400000 {
device_type = "network";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
-@@ -691,7 +718,7 @@
+@@ -1037,7 +1078,7 @@
gmac3: ethernet@37600000 {
device_type = "network";
reg = <0x37600000 0x200000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
-@@ -740,13 +767,13 @@
- qcom,ee = <0>;
+@@ -1050,8 +1050,6 @@
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+-
+- status = "disabled";
+ };
+
+ ss_phy_0: usb3phy@100f8830 {
+@@ -1055,8 +1055,6 @@
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+-
+- status = "disabled";
};
-- amba {
+ usb3_0: usb3@100f8800 {
+@@ -1176,7 +1217,7 @@
+ };
+
+ amba: amba {
- compatible = "simple-bus";
-+ amba: amba {
+ compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
-
-- sdcc@12400000 {
-+ sdcc1: sdcc@12400000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
-@@ -760,13 +787,12 @@
+@@ -1195,7 +1236,6 @@
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
dma-names = "tx", "rx";
- };
-
-- sdcc@12180000 {
-+ sdcc3: sdcc@12180000 {
- compatible = "arm,pl18x", "arm,primecell";
- arm,primecell-periphid = <0x00051180>;
- status = "disabled";
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -8,6 +8,8 @@
+@@ -10,6 +10,8 @@
#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <1>;
-@@ -28,6 +30,16 @@
+@@ -30,6 +32,16 @@
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
};
cpu1: cpu@1 {
-@@ -38,14 +50,350 @@
+@@ -40,11 +52,125 @@
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
};
};
-+ thermal-zones {
-+ tsens_tz_sensor0 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 0>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+
-+ tsens_tz_sensor1 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 1>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+
-+ tsens_tz_sensor2 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 2>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+
-+ tsens_tz_sensor3 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 3>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+
-+ tsens_tz_sensor4 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 4>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+
-+ tsens_tz_sensor5 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 5>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+
-+ tsens_tz_sensor6 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 6>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+
-+ tsens_tz_sensor7 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 7>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+
-+ tsens_tz_sensor8 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 8>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+
-+ tsens_tz_sensor9 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 9>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+
-+ tsens_tz_sensor10 {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsens 10>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <105000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu-hot {
-+ temperature = <95000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+ };
-+ };
-+ };
-+
- memory {
- device_type = "memory";
- reg = <0x0 0x0>;
-@@ -93,6 +441,15 @@
+@@ -317,6 +443,15 @@
};
};
firmware {
scm {
compatible = "qcom,scm-ipq806x", "qcom,scm";
-@@ -120,6 +477,78 @@
- reg-names = "lpass-lpaif";
- };
-
-+ L2: l2-cache {
-+ compatible = "qcom,krait-cache", "cache";
-+ cache-level = <2>;
-+ qcom,saw = <&saw_l2>;
-+
-+ clocks = <&kraitcc 4>;
-+ clock-names = "l2";
-+ l2-supply = <&smb208_s1a>;
-+ operating-points-v2 = <&opp_table_l2>;
-+ };
-+
-+ rpm: rpm@108000 {
-+ compatible = "qcom,rpm-ipq8064";
-+ reg = <0x108000 0x1000>;
-+ qcom,ipc = <&l2cc 0x8 2>;
-+
-+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "ack", "err", "wakeup";
-+
-+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
-+ clock-names = "ram";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rpmcc: clock-controller {
-+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
-+ #clock-cells = <1>;
-+ };
-+
-+ regulators {
-+ compatible = "qcom,rpm-smb208-regulators";
-+
-+ smb208_s1a: s1a {
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s1b: s1b {
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s2a: s2a {
-+ regulator-min-microvolt = < 800000>;
-+ regulator-max-microvolt = <1250000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s2b: s2b {
-+ regulator-min-microvolt = < 800000>;
-+ regulator-max-microvolt = <1250000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+ };
-+ };
-+
-+ rng@1a500000 {
-+ compatible = "qcom,prng";
-+ reg = <0x1a500000 0x200>;
-+ clocks = <&gcc PRNG_CLK>;
-+ clock-names = "core";
-+ };
-+
- qcom_pinmux: pinmux@800000 {
- compatible = "qcom,ipq8064-pinctrl";
- reg = <0x800000 0x4000>;
-@@ -160,6 +589,15 @@
+@@ -384,6 +519,15 @@
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
-@@ -169,6 +607,53 @@
+@@ -437,6 +581,27 @@
+ bias-bus-hold;
};
};
-
-+ nand_pins: nand_pins {
-+ disable {
-+ pins = "gpio34", "gpio35", "gpio36",
-+ "gpio37", "gpio38";
-+ function = "nand";
-+ drive-strength = <10>;
-+ bias-disable;
-+ };
-+
-+ pullups {
-+ pins = "gpio39";
-+ function = "nand";
-+ drive-strength = <10>;
-+ bias-pull-up;
-+ };
-+
-+ hold {
-+ pins = "gpio40", "gpio41", "gpio42",
-+ "gpio43", "gpio44", "gpio45",
-+ "gpio46", "gpio47";
-+ function = "nand";
-+ drive-strength = <10>;
-+ bias-bus-hold;
-+ };
-+ };
+
+ mdio0_pins: mdio0_pins {
+ mux {
+ bias-disable;
+ };
+ };
-+
- leds_pins: leds_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9",
-@@ -231,6 +716,17 @@
- clock-output-names = "acpu1_aux";
};
-+ l2cc: clock-controller@2011000 {
-+ compatible = "qcom,kpss-gcc", "syscon";
-+ reg = <0x2011000 0x1000>;
-+ clock-output-names = "acpu_l2_aux";
-+ };
-+
-+ kraitcc: clock-controller {
-+ compatible = "qcom,krait-cc-v1";
-+ #clock-cells = <1>;
-+ };
-+
- saw0: regulator@2089000 {
- compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
- reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-@@ -243,6 +739,52 @@
+ intc: interrupt-controller@2000000 {
+@@ -513,6 +678,17 @@
regulator;
};
+ compatible = "syscon";
+ reg = <0x12100000 0x10000>;
+ };
-+
-+ gsbi1: gsbi@12440000 {
-+ compatible = "qcom,gsbi-v1.0.0";
-+ cell-index = <1>;
-+ reg = <0x12440000 0x100>;
-+ clocks = <&gcc GSBI1_H_CLK>;
-+ clock-names = "iface";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+ status = "disabled";
-+
-+ syscon-tcsr = <&tcsr>;
-+
-+ gsbi1_serial: serial@12450000 {
-+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-+ reg = <0x12450000 0x100>,
-+ <0x12400000 0x03>;
-+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
-+ clock-names = "core", "iface";
-+ status = "disabled";
-+ };
-+
-+ gsbi1_i2c: i2c@12460000 {
-+ compatible = "qcom,i2c-qup-v1.1.1";
-+ reg = <0x12460000 0x1000>;
-+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
-+ clock-names = "core", "iface";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
-@@ -368,6 +910,33 @@
+@@ -568,6 +910,33 @@
};
};
gsbi7: gsbi@16600000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";
-@@ -389,6 +958,19 @@
+@@ -589,6 +958,19 @@
clock-names = "core", "iface";
status = "disabled";
};
};
sata_phy: sata-phy@1b400000 {
-@@ -478,6 +1060,95 @@
- #reset-cells = <1>;
+@@ -761,6 +937,17 @@
+ };
};
-+ sfpb_mutex_block: syscon@1200600 {
-+ compatible = "syscon";
-+ reg = <0x01200600 0x100>;
-+ };
-+
-+ hs_phy_0: hs_phy_0 {
-+ compatible = "qcom,ipq806x-usb-phy-hs";
-+ reg = <0x110f8800 0x30>;
-+ clocks = <&gcc USB30_0_UTMI_CLK>;
-+ clock-names = "ref";
-+ #phy-cells = <0>;
-+ };
-+
-+ ss_phy_0: ss_phy_0 {
-+ compatible = "qcom,ipq806x-usb-phy-ss";
-+ reg = <0x110f8830 0x30>;
-+ clocks = <&gcc USB30_0_MASTER_CLK>;
-+ clock-names = "ref";
-+ #phy-cells = <0>;
-+ };
-+
-+ usb3_0: usb3@110f8800 {
-+ compatible = "qcom,dwc3", "syscon";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ reg = <0x110f8800 0x8000>;
-+ clocks = <&gcc USB30_0_MASTER_CLK>;
-+ clock-names = "core";
-+
-+ ranges;
-+
-+ resets = <&gcc USB30_0_MASTER_RESET>;
-+ reset-names = "master";
-+
-+ status = "disabled";
-+
-+ dwc3_0: dwc3@11000000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x11000000 0xcd00>;
-+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-+ phys = <&hs_phy_0>, <&ss_phy_0>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ dr_mode = "host";
-+ snps,dis_u3_susphy_quirk;
-+ };
-+ };
++ L2: l2-cache {
++ compatible = "qcom,krait-cache", "cache";
++ cache-level = <2>;
++ qcom,saw = <&saw_l2>;
+
-+ hs_phy_1: hs_phy_1 {
-+ compatible = "qcom,ipq806x-usb-phy-hs";
-+ reg = <0x100f8800 0x30>;
-+ clocks = <&gcc USB30_1_UTMI_CLK>;
-+ clock-names = "ref";
-+ #phy-cells = <0>;
++ clocks = <&kraitcc 4>;
++ clock-names = "l2";
++ l2-supply = <&smb208_s1a>;
++ operating-points-v2 = <&opp_table_l2>;
+ };
+
-+ ss_phy_1: ss_phy_1 {
-+ compatible = "qcom,ipq806x-usb-phy-ss";
-+ reg = <0x100f8830 0x30>;
-+ clocks = <&gcc USB30_1_MASTER_CLK>;
-+ clock-names = "ref";
-+ #phy-cells = <0>;
+ rpm: rpm@108000 {
+ compatible = "qcom,rpm-ipq8064";
+ reg = <0x108000 0x1000>;
+@@ -828,6 +1015,11 @@
+ clock-output-names = "acpu_l2_aux";
+ };
+
++ kraitcc: clock-controller {
++ compatible = "qcom,krait-cc-v1";
++ #clock-cells = <1>;
+ };
+
-+ usb3_1: usb3@100f8800 {
-+ compatible = "qcom,dwc3", "syscon";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ reg = <0x100f8800 0x8000>;
-+ clocks = <&gcc USB30_1_MASTER_CLK>;
-+ clock-names = "core";
-+
-+ ranges;
-+
-+ resets = <&gcc USB30_1_MASTER_RESET>;
-+ reset-names = "master";
-+
-+ status = "disabled";
-+
-+ dwc3_1: dwc3@10000000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x10000000 0xcd00>;
-+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-+ phys = <&hs_phy_1>, <&ss_phy_1>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ dr_mode = "host";
-+ snps,dis_u3_susphy_quirk;
-+ };
+ lcc: clock-controller@28000000 {
+ compatible = "qcom,lcc-ipq8064";
+ reg = <0x28000000 0x1000>;
+@@ -835,6 +1027,11 @@
+ #reset-cells = <1>;
+ };
+
++ sfpb_mutex_block: syscon@1200600 {
++ compatible = "syscon";
++ reg = <0x01200600 0x100>;
+ };
+
pcie0: pci@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
-@@ -739,6 +1410,59 @@
- status = "disabled";
+@@ -1188,6 +1385,21 @@
+ };
};
-+ adm_dma: dma@18300000 {
-+ compatible = "qcom,adm";
-+ reg = <0x18300000 0x100000>;
-+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
-+ #dma-cells = <1>;
-+
-+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
-+ clock-names = "core", "iface";
-+
-+ resets = <&gcc ADM0_RESET>,
-+ <&gcc ADM0_PBUS_RESET>,
-+ <&gcc ADM0_C0_RESET>,
-+ <&gcc ADM0_C1_RESET>,
-+ <&gcc ADM0_C2_RESET>;
-+ reset-names = "clk", "pbus", "c0", "c1", "c2";
-+ qcom,ee = <0>;
-+
-+ status = "disabled";
-+ };
-+
-+ nand_controller: nand-controller@1ac00000 {
-+ compatible = "qcom,ipq806x-nand";
-+ reg = <0x1ac00000 0x800>;
-+
-+ clocks = <&gcc EBI2_CLK>,
-+ <&gcc EBI2_AON_CLK>;
-+ clock-names = "core", "aon";
-+
-+ dmas = <&adm_dma 3>;
-+ dma-names = "rxtx";
-+ qcom,cmd-crci = <15>;
-+ qcom,data-crci = <3>;
-+
-+ status = "disabled";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
+
+ mdio0: mdio@37000000 {
+ #address-cells = <1>;
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
-@@ -814,4 +1538,17 @@
+@@ -1262,4 +1474,17 @@
};
};
};
};
@@ -64,64 +54,5 @@
ports-implemented = <0x1>;
- status = "ok";
+ status = "okay";
};
-
- gpio_keys {
mdio1: mdio-1 {
status = "okay";
compatible = "virtual,mdio-gpio";
-@@ -216,6 +149,68 @@
- };
+@@ -220,6 +153,68 @@
+ status = "okay";
};
+&mdio0 {
+}
+
+static struct cpufreq_driver krait_cpufreq_driver = {
-+ .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
++ .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
+ CPUFREQ_IS_COOLING_DEV,
+ .verify = cpufreq_generic_frequency_table_verify,
+ .target_index = set_target,
};
/*
-@@ -460,12 +475,14 @@ struct qcom_nand_host {
- * @ecc_modes - ecc mode for NAND
+@@ -475,13 +490,15 @@ struct qcom_nand_host {
* @is_bam - whether NAND controller is using BAM
* @is_qpic - whether NAND CTRL is part of qpic IP
+ * @qpic_v2 - flag to indicate QPIC IP version 2
+ * @has_boot_pages - whether NAND has different ecc settings for boot pages
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
*/
u32 ecc_modes;
bool is_bam;
bool is_qpic;
+ bool qpic_v2;
+ bool has_boot_pages;
u32 dev_cmd_reg_start;
};
data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
oob_size1 = host->bbm_size;
-- if (cw == (ecc->steps - 1)) {
-+ if (cw == (ecc->steps - 1) && !host->boot_pages_conf) {
+- if (qcom_nandc_is_last_cw(ecc, cw)) {
++ if (qcom_nandc_is_last_cw(ecc, cw) && !host->boot_pages_conf) {
data_size2 = ecc->size - data_size1 -
((ecc->steps - 1) * 4);
oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw +
}
for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) {
-- if (cw == (ecc->steps - 1)) {
-+ if (cw == (ecc->steps - 1) && !host->boot_pages_conf) {
+- if (qcom_nandc_is_last_cw(ecc, cw)) {
++ if (qcom_nandc_is_last_cw(ecc, cw) && !host->boot_pages_conf) {
data_size = ecc->size - ((ecc->steps - 1) * 4);
oob_size = (ecc->steps * 4) + host->ecc_bytes_hw;
} else {
for (i = 0; i < ecc->steps; i++) {
int data_size, oob_size;
-- if (i == (ecc->steps - 1)) {
-+ if (i == (ecc->steps - 1) && !host->boot_pages_conf) {
+- if (qcom_nandc_is_last_cw(ecc, i)) {
++ if (qcom_nandc_is_last_cw(ecc, i) && !host->boot_pages_conf) {
data_size = ecc->size - ((ecc->steps - 1) << 2);
oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +
host->spare_bytes;
for (i = 0; i < ecc->steps; i++) {
int data_size, oob_size;
-- if (i == (ecc->steps - 1)) {
-+ if (i == (ecc->steps - 1) && !host->boot_pages_conf) {
+- if (qcom_nandc_is_last_cw(ecc, i)) {
++ if (qcom_nandc_is_last_cw(ecc, i) && !host->boot_pages_conf) {
data_size = ecc->size - ((ecc->steps - 1) << 2);
oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +
host->spare_bytes;
data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
oob_size1 = host->bbm_size;
-- if (i == (ecc->steps - 1)) {
-+ if (i == (ecc->steps - 1) && !host->boot_pages_conf) {
+- if (qcom_nandc_is_last_cw(ecc, i)) {
++ if (qcom_nandc_is_last_cw(ecc, i) && !host->boot_pages_conf) {
data_size2 = ecc->size - data_size1 -
((ecc->steps - 1) << 2);
oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
- Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 11 +++++++++++
+ Documentation/devicetree/bindings/mtd/qcom,nandc.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
---- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
-+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
-@@ -52,6 +52,15 @@ Optional properties:
- be used according to chip requirement and available
- OOB size.
-
-+EBI2 specific properties:
-+- nand-is-boot-medium: nand contains boot partitions and different ecc configuration
-+ should be used for these partitions.
-+- qcom,boot_pages_size: should contain the size of the total boot partitions
-+ where the boot layout read/write specific configuration
-+ should be used. The boot layout is considered from the
-+ start of the nand to the value set in this binding.
-+ Only used in combination with 'nand-is-boot-medium'.
+--- a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
++++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
+@@ -77,6 +77,14 @@ Optional properties:
+ description:
+ Must contain the ADM data type CRCI block instance number
+ specified for the NAND controller on the given platform
+
- Each nandcs device node may optionally contain a 'partitions' sub-node, which
- further contains sub-nodes describing the flash partition mapping. See
- partition.txt for more detail.
-@@ -80,6 +89,9 @@ nand-controller@1ac00000 {
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
++ qcom,boot_pages_size:
++ description:
++ Should contain the size of the total boot partitions
++ where the boot layout read/write specific configuration
++ should be used. The boot layout is considered from the
++ start of the nand to the value set in this binding.
++ Only used in combination with 'nand-is-boot-medium'.
+
+ - if:
+ properties:
+@@ -135,6 +135,9 @@ nand-controller@1ac00000 {
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
-+ nand-is-boot-medium;
-+ qcom,boot_pages_size: <0x58a0000>;
++ nand-is-boot-medium;
++ qcom,boot_pages_size: <0x58a0000>;
+
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
+ partitions {
+ compatible = "fixed-partitions";
--- /dev/null
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -689,6 +689,41 @@
+ reg = <0x12100000 0x10000>;
+ };
+
++ gsbi1: gsbi@12440000 {
++ compatible = "qcom,gsbi-v1.0.0";
++ cell-index = <1>;
++ reg = <0x12440000 0x100>;
++ clocks = <&gcc GSBI1_H_CLK>;
++ clock-names = "iface";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++ status = "disabled";
++
++ syscon-tcsr = <&tcsr>;
++
++ gsbi1_serial: serial@12450000 {
++ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
++ reg = <0x12450000 0x100>,
++ <0x12400000 0x03>;
++ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++ };
++
++ gsbi1_i2c: i2c@12460000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x12460000 0x1000>;
++ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
++ clock-names = "core", "iface";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ };
++
+ gsbi2: gsbi@12480000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <2>;
+++ /dev/null
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1794,6 +1794,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL
-
- endchoice
-
-+config CMDLINE_OVERRIDE
-+ bool "Use alternative cmdline from device tree"
-+ help
-+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+ be used, this is not a good option for kernels that are shared across
-+ devices. This setting enables using "chosen/cmdline-override" as the
-+ cmdline if it exists in the device tree.
-+
- config CMDLINE
- string "Default kernel command string"
- default ""
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -1059,6 +1059,17 @@ int __init early_init_dt_scan_chosen(uns
- if (p != NULL && l > 0)
- strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
-
-+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-+ * device tree option of chosen/bootargs-override. This is
-+ * helpful on boards where u-boot sets bootargs, and is unable
-+ * to be modified.
-+ */
-+#ifdef CONFIG_CMDLINE_OVERRIDE
-+ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+ if (p != NULL && l > 0)
-+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
-+#endif
-+
- /*
- * CONFIG_CMDLINE is meant to be a default in case nothing else
- * managed to set the command line, unless CONFIG_CMDLINE_FORCE
projects / openwrt / staging / hauke.git / commitdiff