drm/i915: remove ironlake bits from lpt_pch_enable

Since this function will only run on Haswell/LPT and newer.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 298fd73f481b7105c3e3f50e718a127499f2e41f..28b9d662109cecbe1353c1ed16446a10b12db72b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3170,7 +3170,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
-       u32 reg, temp;
 
        assert_transcoder_disabled(dev_priv, pipe);
 
@@ -3191,34 +3190,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
         * enable sequence. */
        intel_enable_pch_pll(intel_crtc);
 
-       if (HAS_PCH_LPT(dev)) {
-               DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
-               lpt_program_iclkip(crtc);
-       } else if (HAS_PCH_CPT(dev)) {
-               u32 sel;
-
-               temp = I915_READ(PCH_DPLL_SEL);
-               switch (pipe) {
-               default:
-               case 0:
-                       temp |= TRANSA_DPLL_ENABLE;
-                       sel = TRANSA_DPLLB_SEL;
-                       break;
-               case 1:
-                       temp |= TRANSB_DPLL_ENABLE;
-                       sel = TRANSB_DPLLB_SEL;
-                       break;
-               case 2:
-                       temp |= TRANSC_DPLL_ENABLE;
-                       sel = TRANSC_DPLLB_SEL;
-                       break;
-               }
-               if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
-                       temp |= sel;
-               else
-                       temp &= ~sel;
-               I915_WRITE(PCH_DPLL_SEL, temp);
-       }
+       lpt_program_iclkip(crtc);
 
        /* set transcoder timing, panel must allow it */
        assert_panel_unlocked(dev_priv, pipe);
@@ -3231,45 +3203,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
        I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
        I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
 
-       if (!IS_HASWELL(dev))
-               intel_fdi_normal_train(crtc);
-
-       /* For PCH DP, enable TRANS_DP_CTL */
-       if (HAS_PCH_CPT(dev) &&
-           (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
-            intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
-               u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
-               reg = TRANS_DP_CTL(pipe);
-               temp = I915_READ(reg);
-               temp &= ~(TRANS_DP_PORT_SEL_MASK |
-                         TRANS_DP_SYNC_MASK |
-                         TRANS_DP_BPC_MASK);
-               temp |= (TRANS_DP_OUTPUT_ENABLE |
-                        TRANS_DP_ENH_FRAMING);
-               temp |= bpc << 9; /* same format but at 11:9 */
-
-               if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
-                       temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
-               if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
-                       temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
-
-               switch (intel_trans_dp_port_sel(crtc)) {
-               case PCH_DP_B:
-                       temp |= TRANS_DP_PORT_SEL_B;
-                       break;
-               case PCH_DP_C:
-                       temp |= TRANS_DP_PORT_SEL_C;
-                       break;
-               case PCH_DP_D:
-                       temp |= TRANS_DP_PORT_SEL_D;
-                       break;
-               default:
-                       BUG();
-               }
-
-               I915_WRITE(reg, temp);
-       }
-
        intel_enable_transcoder(dev_priv, pipe);
 }