On popular request this now completes the Warren's work started for
TK1:
aeb3fcb35956461077804720b8a252d50758d7e0
ARM: tegra: Use mem size from MC rather than ODMDATA
In addition to the move of using the Tegra memory controller (MC)
register rather than ODMDATA for T20, T30 and T114 as well it further
uses the generic get_ram_size() function (see "common/memsize.c")
<supposed to be used in each and every U-Boot port>TM. Added benefit is
that it should <catch 99% of hardware related (i. e. reliably
reproducible) memory errors> as well.
Thoroughly tested on the various Toradex line of Tegra modules
available which unfortunately does not include T114 and T124 (yet at
least) plus on the Jetson TK1.
Based-on-work-by: Stephen Warren <swarren@nvidia.com>
Based-on-work-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
+#include <asm/arch/mc.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/pmc.h>
UART_COUNT = 5,
};
-#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
- defined(CONFIG_TEGRA114)
-/*
- * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
- * so we are using this value to identify memory size.
- */
-unsigned int query_sdram_size(void)
-{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- reg = readl(&pmc->pmc_scratch20);
- debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
-
-#if defined(CONFIG_TEGRA20)
- /* bits 30:28 in OdmData are used for RAM size on T20 */
- reg &= 0x70000000;
-
- switch ((reg) >> 28) {
- case 1:
- return 0x10000000; /* 256 MB */
- case 0:
- case 2:
- default:
- return 0x20000000; /* 512 MB */
- case 3:
- return 0x40000000; /* 1GB */
- }
-#else /* Tegra30/Tegra114 */
- /* bits 31:28 in OdmData are used for RAM size on T30 */
- switch ((reg) >> 28) {
- case 0:
- case 1:
- default:
- return 0x10000000; /* 256 MB */
- case 2:
- return 0x20000000; /* 512 MB */
- case 3:
- return 0x30000000; /* 768 MB */
- case 4:
- return 0x40000000; /* 1GB */
- case 8:
- return 0x7ff00000; /* 2GB - 1MB */
- }
-#endif
-}
-#else
-#include <asm/arch/mc.h>
-
/* Read the RAM size directly from the memory controller */
unsigned int query_sdram_size(void)
{
u32 size_mb;
size_mb = readl(&mc->mc_emem_cfg);
+#if defined(CONFIG_TEGRA20)
+ debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb);
+ size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024);
+#else
debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
+ size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024);
+#endif
- return size_mb * 1024 * 1024;
-}
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
+ /* External memory limited to 2047 MB due to IROM/HI-VEC */
+ if (size_mb == SZ_2G) size_mb -= SZ_1M;
#endif
+ return size_mb;
+}
+
int dram_init(void)
{
/* We do not initialise DRAM here. We just query the size */
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA114_MC_H_
+#define _TEGRA114_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+ u32 reserved0[4]; /* offset 0x00 - 0x0C */
+ u32 mc_smmu_config; /* offset 0x10 */
+ u32 mc_smmu_tlb_config; /* offset 0x14 */
+ u32 mc_smmu_ptc_config; /* offset 0x18 */
+ u32 mc_smmu_ptb_asid; /* offset 0x1C */
+ u32 mc_smmu_ptb_data; /* offset 0x20 */
+ u32 reserved1[3]; /* offset 0x24 - 0x2C */
+ u32 mc_smmu_tlb_flush; /* offset 0x30 */
+ u32 mc_smmu_ptc_flush; /* offset 0x34 */
+ u32 reserved2[6]; /* offset 0x38 - 0x4C */
+ u32 mc_emem_cfg; /* offset 0x50 */
+ u32 mc_emem_adr_cfg; /* offset 0x54 */
+ u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
+ u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
+ u32 reserved3[12]; /* offset 0x60 - 0x8C */
+ u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
+ u32 reserved4[338]; /* offset 0x100 - 0x644 */
+ u32 mc_video_protect_bom; /* offset 0x648 */
+ u32 mc_video_protect_size_mb; /* offset 0x64c */
+ u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
+};
+
+#endif /* _TEGRA114_MC_H_ */
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
+#define NV_PA_MC_BASE 0x70019000
#include <asm/arch-tegra/tegra.h>
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA20_MC_H_
+#define _TEGRA20_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+ u32 reserved0[3]; /* offset 0x00 - 0x08 */
+ u32 mc_emem_cfg; /* offset 0x0C */
+ u32 mc_emem_adr_cfg; /* offset 0x10 */
+ u32 mc_emem_arb_cfg0; /* offset 0x14 */
+ u32 mc_emem_arb_cfg1; /* offset 0x18 */
+ u32 mc_emem_arb_cfg2; /* offset 0x1C */
+ u32 reserved1; /* offset 0x20 */
+ u32 mc_gart_cfg; /* offset 0x24 */
+ u32 mc_gart_entry_addr; /* offset 0x28 */
+ u32 mc_gart_entry_data; /* offset 0x2C */
+ u32 mc_gart_error_req; /* offset 0x30 */
+ u32 mc_gart_error_addr; /* offset 0x34 */
+ u32 reserved2; /* offset 0x38 */
+ u32 mc_timeout_ctrl; /* offset 0x3C */
+ u32 reserved3[6]; /* offset 0x40 - 0x54 */
+ u32 mc_decerr_emem_others_status; /* offset 0x58 */
+ u32 mc_decerr_emem_others_adr; /* offset 0x5C */
+ u32 reserved4[40]; /* offset 0x60 - 0xFC */
+ u32 reserved5[93]; /* offset 0x100 - 0x270 */
+};
+
+#endif /* _TEGRA20_MC_H_ */
#define _TEGRA20_H_
#define NV_PA_SDRAM_BASE 0x00000000
+#define NV_PA_MC_BASE 0x7000F000
#include <asm/arch-tegra/tegra.h>
--- /dev/null
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA30_MC_H_
+#define _TEGRA30_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+ u32 reserved0[4]; /* offset 0x00 - 0x0C */
+ u32 mc_smmu_config; /* offset 0x10 */
+ u32 mc_smmu_tlb_config; /* offset 0x14 */
+ u32 mc_smmu_ptc_config; /* offset 0x18 */
+ u32 mc_smmu_ptb_asid; /* offset 0x1C */
+ u32 mc_smmu_ptb_data; /* offset 0x20 */
+ u32 reserved1[3]; /* offset 0x24 - 0x2C */
+ u32 mc_smmu_tlb_flush; /* offset 0x30 */
+ u32 mc_smmu_ptc_flush; /* offset 0x34 */
+ u32 mc_smmu_asid_security; /* offset 0x38 */
+ u32 reserved2[5]; /* offset 0x3C - 0x4C */
+ u32 mc_emem_cfg; /* offset 0x50 */
+ u32 mc_emem_adr_cfg; /* offset 0x54 */
+ u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
+ u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
+ u32 reserved3[12]; /* offset 0x60 - 0x8C */
+ u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
+ u32 reserved4[338]; /* offset 0x100 - 0x644 */
+ u32 mc_video_protect_bom; /* offset 0x648 */
+ u32 mc_video_protect_size_mb; /* offset 0x64c */
+ u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
+};
+
+#endif /* _TEGRA30_MC_H_ */
#ifndef _TEGRA30_H_
#define _TEGRA30_H_
+#define NV_PA_MC_BASE 0x7000F000
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
#include <asm/arch-tegra/tegra.h>
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