*/
#include <config.h>
-#ifdef CONFIG_AU1X00
+#ifdef CONFIG_SOC_AU1X00
#if defined(CFG_DISCOVER_PHY)
#error "PHY not supported yet"
/* I assume ethernet behaves like au1000 */
-#ifdef CONFIG_AU1000
+#ifdef CONFIG_SOC_AU1000
/* Base address differ between cpu:s */
#define ETH0_BASE AU1000_ETH0_BASE
#define MAC0_ENABLE AU1000_MAC0_ENABLE
#else
-#ifdef CONFIG_AU1100
+#ifdef CONFIG_SOC_AU1100
#define ETH0_BASE AU1100_ETH0_BASE
#define MAC0_ENABLE AU1100_MAC0_ENABLE
#else
-#ifdef CONFIG_AU1500
+#ifdef CONFIG_SOC_AU1500
#define ETH0_BASE AU1500_ETH0_BASE
#define MAC0_ENABLE AU1500_MAC0_ENABLE
#else
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
#define ETH0_BASE AU1550_ETH0_BASE
#define MAC0_ENABLE AU1550_MAC0_ENABLE
#else
return 1;
}
-#endif /* CONFIG_AU1X00 */
+#endif /* CONFIG_SOC_AU1X00 */
#include <config.h>
-#ifdef CONFIG_AU1X00
+#ifdef CONFIG_SOC_AU1X00
#include <common.h>
#include <asm/au1x00.h>
}
return 0;
}
-#endif /* CONFIG_SERIAL_AU1X00 */
+#endif /* CONFIG_SOC_AU1X00 */
#include <config.h>
-#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI)
+#if defined(CONFIG_SOC_AU1X00) && defined(CONFIG_USB_OHCI)
/* #include <pci.h> no PCI on the AU1x00 */
* Returns the uncached address of a sdram address
*/
#ifndef __ASSEMBLY__
-#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
+#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
/* We use a 36 bit physical address map here and
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
-#else /* !CONFIG_AU1X00 */
+#else /* !CONFIG_SOC_AU1X00 */
#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
-#endif /* CONFIG_AU1X00 */
+#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
/*
#define CP0_DEBUG $23
/* SDRAM Controller */
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
#define MEM_SDMODE0 0xB4000800
#define MEM_SDMODE1 0xB4000808
#define MEM_SDWRMD1 0xB4000888
#define MEM_SDWRMD2 0xB4000890
-#else /* CONFIG_AU1550 */
+#else /* CONFIG_SOC_AU1550 */
#define MEM_SDMODE0 0xB4000000
#define MEM_SDMODE1 0xB4000004
#define MEM_SDWRMD1 0xB4000028
#define MEM_SDWRMD2 0xB400002C
-#endif /* CONFIG_AU1550 */
+#endif /* CONFIG_SOC_AU1550 */
#define MEM_SDSLEEP 0xB4000030
#define MEM_SDSMCKE 0xB4000034
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_DBAU1X00 1
-#define CONFIG_AU1X00 1 /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
-#define CONFIG_AU1000 1
+#define CONFIG_SOC_AU1000 1
#else
#ifdef CONFIG_DBAU1100
-#define CONFIG_AU1100 1
+#define CONFIG_SOC_AU1100 1
#else
#ifdef CONFIG_DBAU1500
-#define CONFIG_AU1500 1
+#define CONFIG_SOC_AU1500 1
#else
#ifdef CONFIG_DBAU1550
/* Cabernet */
-#define CONFIG_AU1550 1
+#define CONFIG_SOC_AU1550 1
#else
#error "No valid board set"
#endif
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_GTH2 1
-#define CONFIG_AU1X00 1 /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-#define CONFIG_AU1000 1
+#define CONFIG_SOC_AU1000 1
#define CONFIG_MISC_INIT_R 1
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_PB1X00 1
-#define CONFIG_AU1X00 1 /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
#ifdef CONFIG_PB1000
-#define CONFIG_AU1000 1
+#define CONFIG_SOC_AU1000 1
#else
#ifdef CONFIG_PB1100
-#define CONFIG_AU1100 1
+#define CONFIG_SOC_AU1100 1
#else
#ifdef CONFIG_PB1500
-#define CONFIG_AU1500 1
+#define CONFIG_SOC_AU1500 1
#else
#error "No valid board set"
#endif