clk: samsung: Reorder MUX registration for mout_vpllsrc

While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the
"fout_vpll" (child), we found get rate was failing.

So this patch moves the mout_vpllsrc MUX out of the existing common list
and registers the mout_vpllsrc MUX before the PLL registrations.

Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 46a16362f9c9038e9aace16a2501d16d032d9815..7404084a3a1d63a15a4c1c9283bde61f695d23a1 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -233,6 +233,10 @@ static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initda
        FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
 };
 
+static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
+       MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
+};
+
 static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
        MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"),
        MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
@@ -240,7 +244,6 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
        MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
        MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
        MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
-       MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
        MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
        MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
        MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
@@ -532,6 +535,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
        samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
                        ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
                        ext_clk_match);
+       samsung_clk_register_mux(exynos5250_pll_pmux_clks,
+                               ARRAY_SIZE(exynos5250_pll_pmux_clks));
        samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),
                                        reg_base);
        samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,