drm/amd/display: used optimum VSTARTUP instead of MaxVStartup

[Description]
Features that are desirable for minimizing the Global Sync Period:
DRR and lateflip

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 9243f275d26584875efc5be09ed396e8a7ced26d..ca5a7791d0809c8d7575e59b27c65e41c36e2457 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1671,6 +1671,8 @@ int dcn20_populate_dml_pipes_from_context(
                        /* Unknown link capabilities, so assume max */
                        pipes[pipe_cnt].dout.dp_lanes = 4;
                }
+               pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
+               pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
 
                pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.display_color_depth;
                switch (res_ctx->pipe_ctx[i].stream->signal) {
@@ -1749,6 +1751,8 @@ int dcn20_populate_dml_pipes_from_context(
                        pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
                        pipes[pipe_cnt].pipe.src.is_hsplit = 0;
                        pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+                       pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
+                       pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
                } else {
                        struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
                        struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 21d90c6f3c8824bd1336e44a99a11d7c8ee9e737..649883777f62a6ff9e08c7154ea8204138f05afa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2698,8 +2698,12 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
                                        VStartupMargin = dml_min(VStartupMargin, Margin);
                }
 
-               if (mode_lib->vba.UseMaximumVStartup)
-                       mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
+               if (mode_lib->vba.UseMaximumVStartup) {
+                       if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) {
+                               //only use max vstart if it is not drr or lateflip.
+                               mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
+                       }
+               }
        }
 }
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 4e0183dd634a8b4a28c19eb964d0ddafb243612c..75028007095c191ea368c81bc3fb42a060f85e48 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -284,6 +284,8 @@ struct vba_vars_st {
        unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
        unsigned int HTotal[DC__NUM_DPP__MAX];
        unsigned int VTotal[DC__NUM_DPP__MAX];
+       unsigned int VTotal_Max[DC__NUM_DPP__MAX];
+       unsigned int VTotal_Min[DC__NUM_DPP__MAX];
        int DPPPerPlane[DC__NUM_DPP__MAX];
        double PixelClock[DC__NUM_DPP__MAX];
        double PixelClockBackEnd[DC__NUM_DPP__MAX];