MIPS: OCTEON: octeon-usb: use common gpio_bit definition

cvmx_gpio_bit_cfgx bitfields are indentical on cn70xx and cn73xx,
and also match the default definition. So use that instead.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org

diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c
index bfdfaf32d2c49742066329e800a6b535f363c3e1..1f730ded52245739e5aadcb404acdde23a10c573 100644 (file)
--- a/arch/mips/cavium-octeon/octeon-usb.c
+++ b/arch/mips/cavium-octeon/octeon-usb.c
@@ -253,17 +253,17 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base)
                    && gpio <= 31) {
                        gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
                        gpio_bit.s.tx_oe = 1;
-                       gpio_bit.cn73xx.output_sel = (index == 0 ? 0x14 : 0x15);
+                       gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15);
                        cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
                } else if (gpio <= 15) {
                        gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
                        gpio_bit.s.tx_oe = 1;
-                       gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19);
+                       gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
                        cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
                } else {
                        gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
                        gpio_bit.s.tx_oe = 1;
-                       gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19);
+                       gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
                        cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
                }