drm/amd/powerplay: move asic unrelated function to hwmgr.c.

It's generic and used by multiple asics.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index c94f9faa220a7ddadff3001aebf5d5da9996c43e..382223b2f047ba62f89c6554e962849e0b5df360 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -3573,46 +3573,11 @@ static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
-static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
-{
-       struct phm_ppt_v1_information *table_info =
-                       (struct phm_ppt_v1_information *)hwmgr->pptable;
-       struct phm_clock_voltage_dependency_table *table =
-                               table_info->vddc_dep_on_dal_pwrl;
-       struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
-       enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
-       uint32_t req_vddc = 0, req_volt, i;
-
-       if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
-                       dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
-               return;
-
-       for (i= 0; i < table->count; i++) {
-               if (dal_power_level == table->entries[i].clk) {
-                       req_vddc = table->entries[i].v;
-                       break;
-               }
-       }
-
-       vddc_table = table_info->vdd_dep_on_sclk;
-       for (i= 0; i < vddc_table->count; i++) {
-               if (req_vddc <= vddc_table->entries[i].vddc) {
-                       req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
-                                       << VDDC_SHIFT;
-                       smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-                                       PPSMC_MSG_VddC_Request, req_volt);
-                       return;
-               }
-       }
-       printk(KERN_ERR "DAL requested level can not"
-                       " found a available voltage in VDDC DPM Table \n");
-}
-
 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
 {
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 
-       fiji_apply_dal_min_voltage_request(hwmgr);
+       phm_apply_dal_min_voltage_request(hwmgr);
 
        if (!data->sclk_dpm_key_disabled) {
                if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 7d69ed635bc2071c0ff1c48a2b2b675e5d0145be..1c48917da3cf3712b39eb72aaf1511fc3936845c 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -30,6 +30,9 @@
 #include "pppcielanes.h"
 #include "pp_debug.h"
 #include "ppatomctrl.h"
+#include "ppsmc.h"
+
+#define VOLTAGE_SCALE               4
 
 extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
 extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
@@ -566,3 +569,38 @@ uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
 
        return level;
 }
+
+void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
+{
+       struct phm_ppt_v1_information *table_info =
+                       (struct phm_ppt_v1_information *)hwmgr->pptable;
+       struct phm_clock_voltage_dependency_table *table =
+                               table_info->vddc_dep_on_dal_pwrl;
+       struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
+       enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
+       uint32_t req_vddc = 0, req_volt, i;
+
+       if (!table || table->count <= 0
+               || dal_power_level < PP_DAL_POWERLEVEL_ULTRALOW
+               || dal_power_level > PP_DAL_POWERLEVEL_PERFORMANCE)
+               return;
+
+       for (i = 0; i < table->count; i++) {
+               if (dal_power_level == table->entries[i].clk) {
+                       req_vddc = table->entries[i].v;
+                       break;
+               }
+       }
+
+       vddc_table = table_info->vdd_dep_on_sclk;
+       for (i = 0; i < vddc_table->count; i++) {
+               if (req_vddc <= vddc_table->entries[i].vddc) {
+                       req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
+                       smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+                                       PPSMC_MSG_VddC_Request, req_volt);
+                       return;
+               }
+       }
+       printk(KERN_ERR "DAL requested level can not"
+                       " found a available voltage in VDDC DPM Table \n");
+}

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 4115dd8ec0515ed0e8d12754dcbf7299504248fb..4cef7a527696f1297c04d006216ac535bc884a14 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -189,42 +189,6 @@ int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
        return decode_pcie_lane_width(link_width);
 }
 
-void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
-{
-       struct phm_ppt_v1_information *table_info =
-                       (struct phm_ppt_v1_information *)hwmgr->pptable;
-       struct phm_clock_voltage_dependency_table *table =
-                               table_info->vddc_dep_on_dal_pwrl;
-       struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
-       enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
-       uint32_t req_vddc = 0, req_volt, i;
-
-       if (!table || table-count <= 0
-               || dal_power_level < PP_DAL_POWERLEVEL_ULTRALOW
-               || dal_power_level > PP_DAL_POWERLEVEL_PERFORMANCE)
-               return;
-
-       for (i = 0; i < table->count; i++) {
-               if (dal_power_level == table->entries[i].clk) {
-                       req_vddc = table->entries[i].v;
-                       break;
-               }
-       }
-
-       vddc_table = table_info->vdd_dep_on_sclk;
-       for (i = 0; i < vddc_table->count; i++) {
-               if (req_vddc <= vddc_table->entries[i].vddc) {
-                       req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
-                                       << VDDC_SHIFT;
-                       smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-                                       PPSMC_MSG_VddC_Request, req_volt);
-                       return;
-               }
-       }
-       printk(KERN_ERR "DAL requested level can not"
-                       " found a available voltage in VDDC DPM Table \n");
-}
-
 /**
 * Enable voltage control
 *

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index fd4ce7aaeee9a1a5b52ca165058966c8bdd3814b..28f571449495d6e639c6135d4394d8eedaea7587 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -673,7 +673,7 @@ extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_volta
 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
 extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
-
+extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
 
 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU