return ret;
}
-int smu_update_table_with_arg(struct smu_context *smu, uint16_t table_id, uint16_t exarg,
+int smu_update_table(struct smu_context *smu, uint32_t table_index,
void *table_data, bool drv2smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *table = NULL;
int ret = 0;
- uint32_t table_index;
+ int table_id = table_index & 0xffff;
if (!table_data || table_id >= smu_table->table_count)
return -EINVAL;
- table_index = (exarg << 16) | table_id;
-
table = &smu_table->tables[table_id];
if (drv2smu)
extern int smu_feature_set_supported(struct smu_context *smu,
enum smu_feature_mask mask, bool enable);
-int smu_update_table_with_arg(struct smu_context *smu, uint16_t table_id, uint16_t exarg,
+int smu_update_table(struct smu_context *smu, uint32_t table_index,
void *table_data, bool drv2smu);
-#define smu_update_table(smu, table_id, table_data, drv2smu) \
- smu_update_table_with_arg((smu), (table_id), 0, (table_data), (drv2smu))
bool is_support_sw_smu(struct amdgpu_device *adev);
int smu_reset(struct smu_context *smu);