iwlwifi: move D3_CFG_COMPLETE handling into DVM

The MVM firmware doesn't communicate this way, it instead
assumes D3 configuration is complete after a specific host
command (which must be last) has been sent. Handling this
bit thus belongs into the firmware API code, i.e. DVM.

Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>

diff --git a/drivers/net/wireless/iwlwifi/dvm/mac80211.c b/drivers/net/wireless/iwlwifi/dvm/mac80211.c
index cab23af0be9e604051e0c2a5d4b8b0a87073a7ca..700215324af89c6bada01fe820be2ad918eb58c7 100644 (file)
--- a/drivers/net/wireless/iwlwifi/dvm/mac80211.c
+++ b/drivers/net/wireless/iwlwifi/dvm/mac80211.c
@@ -426,6 +426,10 @@ static int iwlagn_mac_suspend(struct ieee80211_hw *hw,
        if (ret)
                goto error;
 
+       /* let the ucode operate on its own */
+       iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
+                   CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
+
        iwl_trans_d3_suspend(priv->trans);
 
        goto out;
@@ -509,6 +513,10 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
                goto out_unlock;
        }
 
+       /* uCode is no longer operating by itself */
+       iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
+                   CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
+
        base = priv->device_pointers.error_event_table;
        if (!iwlagn_hw_valid_rtc_data_addr(base)) {
                IWL_WARN(priv, "Invalid error table during resume!\n");

diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index a785f49df9b1fa8efcabe3271baf53a64f2ca5b9..0b021305eedf121149072fecb6ad9f3d039bfd06 100644 (file)
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -580,10 +580,6 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 
 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans)
 {
-       /* let the ucode operate on its own */
-       iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
-                   CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
-
        iwl_disable_interrupts(trans);
        iwl_pcie_disable_ict(trans);
 
@@ -643,9 +639,6 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
                return ret;
        }
 
-       iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
-                   CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
-
        *status = IWL_D3_STATUS_ALIVE;
        return 0;
 }