drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR1

When any other value than EDP_PSR_TP4_TIME_0US is set, TPS1 and TPS4
will be used to do the link training when exiting PSR1.
Happily the eDP panels tested so far was able to sync with source
even without HBR3/TPS4 support but let use the right training
pattern.

TPS4 support was added to PSR1 registers because HBR3/PSR
specification was not closed when ICL was freezed so if HBR3 was
supported by PSR, ICL would already be ready but it was not added to
specification so lets always disable TPS4.

v3: Missed ";" SPANK SPANK SPANK!!!

BSpec: 17524

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190312195743.8829-3-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87123861e41e5665a9749adbb499ff58e588f4c3..9b69cec21f7b3182700a52400a17db65eb596565 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4205,6 +4205,7 @@ enum {
 #define   EDP_PSR_TP2_TP3_TIME_100us           (1 << 8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us          (2 << 8)
 #define   EDP_PSR_TP2_TP3_TIME_0us             (3 << 8)
+#define   EDP_PSR_TP4_TIME_0US                 (3 << 6) /* ICL+ */
 #define   EDP_PSR_TP1_TIME_500us               (0 << 4)
 #define   EDP_PSR_TP1_TIME_100us               (1 << 4)
 #define   EDP_PSR_TP1_TIME_2500us              (2 << 4)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 813be3b81bdc6954858c51e20f22a2a0208d5b68..7d570a45fc17d1fcf90b62fda73d534ea7f45a79 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -439,6 +439,9 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        u32 val = 0;
 
+       if (INTEL_GEN(dev_priv) >= 11)
+               val |= EDP_PSR_TP4_TIME_0US;
+
        if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
                val |= EDP_PSR_TP1_TIME_0us;
        else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)