clk: sunxi-ng: mux: Rename mux macro to be consistent
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Wed, 20 Jul 2016 21:45:35 +0000 (23:45 +0200)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Thu, 25 Aug 2016 20:25:53 +0000 (22:25 +0200)
Rename the internal mux macro to be consistent with the other internal
structure macros.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu_div.h
drivers/clk/sunxi-ng/ccu_mp.h
drivers/clk/sunxi-ng/ccu_mux.h
drivers/clk/sunxi-ng/ccu_nkm.h

index 653ade5769b32560f5f876f87a32999a0f972fc4..5d98549e23a64c914cd64b73fe651c4dffd4b8f8 100644 (file)
@@ -83,7 +83,7 @@ struct ccu_div {
        struct ccu_div _struct = {                                      \
                .enable = _gate,                                        \
                .div    = _SUNXI_CCU_DIV(_mshift, _mwidth),             \
-               .mux    = SUNXI_CLK_MUX(_muxshift, _muxwidth),          \
+               .mux    = _SUNXI_CCU_MUX(_muxshift, _muxwidth),         \
                .common = {                                             \
                        .reg            = _reg,                         \
                        .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
index 3cf12bf95962330e473340cbc38e511e54263f87..edf9215ea8ccdfacab996ac8117b635dfa379b4e 100644 (file)
@@ -44,7 +44,7 @@ struct ccu_mp {
                .enable = _gate,                                        \
                .m      = _SUNXI_CCU_DIV(_mshift, _mwidth),             \
                .p      = _SUNXI_CCU_DIV(_pshift, _pwidth),             \
-               .mux    = SUNXI_CLK_MUX(_muxshift, _muxwidth),          \
+               .mux    = _SUNXI_CCU_MUX(_muxshift, _muxwidth),         \
                .common = {                                             \
                        .reg            = _reg,                         \
                        .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
index d35ce5e93840b878380e52c7aa1dba0857c23cc9..83737c2facd4be0d8bd644b450ef4434004e4b23 100644 (file)
@@ -21,7 +21,7 @@ struct ccu_mux_internal {
        } variable_prediv;
 };
 
-#define SUNXI_CLK_MUX(_shift, _width)  \
+#define _SUNXI_CCU_MUX(_shift, _width)         \
        {                                       \
                .shift  = _shift,               \
                .width  = _width,               \
@@ -37,7 +37,7 @@ struct ccu_mux {
 
 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, _flags) \
        struct ccu_mux _struct = {                                      \
-               .mux    = SUNXI_CLK_MUX(_shift, _width),                \
+               .mux    = _SUNXI_CCU_MUX(_shift, _width),               \
                .common = {                                             \
                        .reg            = _reg,                         \
                        .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
@@ -51,7 +51,7 @@ struct ccu_mux {
                                _shift, _width, _gate, _flags)          \
        struct ccu_mux _struct = {                                      \
                .enable = _gate,                                        \
-               .mux    = SUNXI_CLK_MUX(_shift, _width),                \
+               .mux    = _SUNXI_CCU_MUX(_shift, _width),               \
                .common = {                                             \
                        .reg            = _reg,                         \
                        .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
index fcb152fc4eda7513e016e01b787860417d88e0d6..35493fddd8ab3f07a30388e5bd74eb3d70026395 100644 (file)
@@ -49,7 +49,7 @@ struct ccu_nkm {
                .k              = _SUNXI_CCU_MULT(_kshift, _kwidth),    \
                .n              = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
                .m              = _SUNXI_CCU_DIV(_mshift, _mwidth),     \
-               .mux            = SUNXI_CLK_MUX(_muxshift, _muxwidth),  \
+               .mux            = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
                .common         = {                                     \
                        .reg            = _reg,                         \
                        .hw.init        = CLK_HW_INIT_PARENTS(_name,    \