ramips: ramips_esw: use a private structure for the functions

SVN-Revision: 24329

diff --git a/target/linux/ramips/files/drivers/net/ramips_esw.c b/target/linux/ramips/files/drivers/net/ramips_esw.c
index f9d31c2fb422b28c0bd1f4ddc636fa1ba1ef83c0..e4c8ea3dbf2bd3ce503ae57df16521d5bf601ae4 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ramips_esw.c
+++ b/target/linux/ramips/files/drivers/net/ramips_esw.c
@@ -8,18 +8,22 @@
 #define RT305X_ESW_PHY_CONTROL_0       0xC0
 #define RT305X_ESW_PHY_CONTROL_1       0xC4
 
-static void __iomem *ramips_esw_base = 0;
+struct rt305x_esw {
+       void __iomem *base;
+};
+
+static struct rt305x_esw rt305x_esw;
 
 static inline void
-ramips_esw_wr(u32 val, unsigned reg)
+ramips_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
 {
-       __raw_writel(val, ramips_esw_base + reg);
+       __raw_writel(val, esw->base + reg);
 }
 
 static inline u32
-ramips_esw_rr(unsigned reg)
+ramips_esw_rr(struct rt305x_esw *esw, unsigned reg)
 {
-       return __raw_readl(ramips_esw_base + reg);
+       return __raw_readl(esw->base + reg);
 }
 
 static void
@@ -34,7 +38,8 @@ ramips_enable_mdio(int s)
 }
 
 u32
-mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
+mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
+             u32 write_data)
 {
        unsigned long volatile t_start = jiffies;
        int ret = 0;
@@ -42,7 +47,7 @@ mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
        ramips_enable_mdio(1);
        while(1)
        {
-               if(!(ramips_esw_rr(RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0)))
+               if(!(ramips_esw_rr(esw, RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0)))
                        break;
                if(time_after(jiffies, t_start + RT305X_ESW_PHY_TOUT))
                {
@@ -50,12 +55,12 @@ mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
                        goto out;
                }
        }
-       ramips_esw_wr(((write_data & 0xFFFF) << 16) | (phy_register << 8) |
+       ramips_esw_wr(esw, ((write_data & 0xFFFF) << 16) | (phy_register << 8) |
                (phy_addr) | RT305X_ESW_PHY_WRITE, RT305X_ESW_PHY_CONTROL_0);
        t_start = jiffies;
        while(1)
        {
-               if(ramips_esw_rr(RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0))
+               if(ramips_esw_rr(esw, RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0))
                        break;
                if(time_after(jiffies, t_start + RT305X_ESW_PHY_TOUT))
                {
@@ -73,41 +78,43 @@ out:
 static int
 rt305x_esw_init(void)
 {
+       struct rt305x_esw *esw;
        int i;
 
-       ramips_esw_base = ioremap_nocache(RT305X_SWITCH_BASE, PAGE_SIZE);
-       if(!ramips_esw_base)
+       esw = &rt305x_esw;
+       esw->base = ioremap_nocache(RT305X_SWITCH_BASE, PAGE_SIZE);
+       if(!esw->base)
                return -ENOMEM;
 
        /* vodoo from original driver */
-       ramips_esw_wr(0xC8A07850, 0x08);
-       ramips_esw_wr(0x00000000, 0xe4);
-       ramips_esw_wr(0x00405555, 0x14);
-       ramips_esw_wr(0x00002001, 0x50);
-       ramips_esw_wr(0x00007f7f, 0x90);
-       ramips_esw_wr(0x00007f3f, 0x98);
-       ramips_esw_wr(0x00d6500c, 0xcc);
-       ramips_esw_wr(0x0008a301, 0x9c);
-       ramips_esw_wr(0x02404040, 0x8c);
-       ramips_esw_wr(0x00001002, 0x48);
-       ramips_esw_wr(0x3f502b28, 0xc8);
-       ramips_esw_wr(0x00000000, 0x84);
+       ramips_esw_wr(esw, 0xC8A07850, 0x08);
+       ramips_esw_wr(esw, 0x00000000, 0xe4);
+       ramips_esw_wr(esw, 0x00405555, 0x14);
+       ramips_esw_wr(esw, 0x00002001, 0x50);
+       ramips_esw_wr(esw, 0x00007f7f, 0x90);
+       ramips_esw_wr(esw, 0x00007f3f, 0x98);
+       ramips_esw_wr(esw, 0x00d6500c, 0xcc);
+       ramips_esw_wr(esw, 0x0008a301, 0x9c);
+       ramips_esw_wr(esw, 0x02404040, 0x8c);
+       ramips_esw_wr(esw, 0x00001002, 0x48);
+       ramips_esw_wr(esw, 0x3f502b28, 0xc8);
+       ramips_esw_wr(esw, 0x00000000, 0x84);
 
-       mii_mgr_write(0, 31, 0x8000);
+       mii_mgr_write(esw, 0, 31, 0x8000);
        for(i = 0; i < 5; i++)
        {
-               mii_mgr_write(i, 0, 0x3100);   //TX10 waveform coefficient
-               mii_mgr_write(i, 26, 0x1601);   //TX10 waveform coefficient
-               mii_mgr_write(i, 29, 0x7058);   //TX100/TX10 AD/DA current bias
-               mii_mgr_write(i, 30, 0x0018);   //TX100 slew rate control
+               mii_mgr_write(esw, i, 0, 0x3100);   //TX10 waveform coefficient
+               mii_mgr_write(esw, i, 26, 0x1601);   //TX10 waveform coefficient
+               mii_mgr_write(esw, i, 29, 0x7058);   //TX100/TX10 AD/DA current bias
+               mii_mgr_write(esw, i, 30, 0x0018);   //TX100 slew rate control
        }
        /* PHY IOT */
-       mii_mgr_write(0, 31, 0x0);      //select global register
-       mii_mgr_write(0, 22, 0x052f);   //tune TP_IDL tail and head waveform
-       mii_mgr_write(0, 17, 0x0fe0);   //set TX10 signal amplitude threshold to minimum
-       mii_mgr_write(0, 18, 0x40ba);   //set squelch amplitude to higher threshold
-       mii_mgr_write(0, 14, 0x65);     //longer TP_IDL tail length
-       mii_mgr_write(0, 31, 0x8000);   //select local register
+       mii_mgr_write(esw, 0, 31, 0x0);      //select global register
+       mii_mgr_write(esw, 0, 22, 0x052f);   //tune TP_IDL tail and head waveform
+       mii_mgr_write(esw, 0, 17, 0x0fe0);   //set TX10 signal amplitude threshold to minimum
+       mii_mgr_write(esw, 0, 18, 0x40ba);   //set squelch amplitude to higher threshold
+       mii_mgr_write(esw, 0, 14, 0x65);     //longer TP_IDL tail length
+       mii_mgr_write(esw, 0, 31, 0x8000);   //select local register
 
        /* Port 5 Disabled */
        rt305x_sysc_wr(rt305x_sysc_rr(0x60) | (1 << 9), 0x60); //set RGMII to GPIO mode (GPIO41-GPIO50)
@@ -115,8 +122,8 @@ rt305x_esw_init(void)
        rt305x_sysc_wr(0x0, 0x670); //GPIO41-GPIO50 output low
 
        /* set default vlan */
-       ramips_esw_wr(0x2001, 0x50);
-       ramips_esw_wr(0x504f, 0x70);
+       ramips_esw_wr(esw, 0x2001, 0x50);
+       ramips_esw_wr(esw, 0x504f, 0x70);
 
        return 0;
 }