plat/arm: Fix misra warnings in platform code

Change-Id: Ica944acc474a099219d50b041cfaeabd4f3d362f
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

diff --git a/include/common/interrupt_props.h b/include/common/interrupt_props.h
index 9786b40c8102e8513dbf54ca41d62db2f7610bd8..4ac698dfc89ab0f7eb79ea419b91c33bf33d0f40 100644 (file)
--- a/include/common/interrupt_props.h
+++ b/include/common/interrupt_props.h
@@ -12,10 +12,10 @@
 /* Create an interrupt property descriptor from various interrupt properties */
 #define INTR_PROP_DESC(num, pri, grp, cfg) \
        { \
-               .intr_num = num, \
-               .intr_pri = pri, \
-               .intr_grp = grp, \
-               .intr_cfg = cfg, \
+               .intr_num = (num), \
+               .intr_pri = (pri), \
+               .intr_grp = (grp), \
+               .intr_cfg = (cfg), \
        }
 
 typedef struct interrupt_prop {

diff --git a/include/drivers/arm/tzc_common.h b/include/drivers/arm/tzc_common.h
index 9411b73107f82e77d087a499ff39f25673bca540..bb64b008ff9f1887c58b580261d88f17a8cb5bcc 100644 (file)
--- a/include/drivers/arm/tzc_common.h
+++ b/include/drivers/arm/tzc_common.h
@@ -46,10 +46,10 @@
 
 /* Macros for allowing Non-Secure access to a region based on NSAID */
 #define TZC_REGION_ACCESS_RD(nsaid)                            \
-       ((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) <<          \
+       ((1 << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) <<        \
         TZC_REGION_ACCESS_RD_EN_SHIFT)
 #define TZC_REGION_ACCESS_WR(nsaid)                            \
-       ((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) <<          \
+       ((1 << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) <<        \
         TZC_REGION_ACCESS_WR_EN_SHIFT)
 #define TZC_REGION_ACCESS_RDWR(nsaid)                          \
        (TZC_REGION_ACCESS_RD(nsaid) |                          \

diff --git a/plat/arm/board/fvp/fvp_security.c b/plat/arm/board/fvp/fvp_security.c
index a6c92278f564762bb133324d42ca3ef9b41b4cdc..028522cfefd9ceb31aa4d8c61d5e645036c1d933 100644 (file)
--- a/plat/arm/board/fvp/fvp_security.c
+++ b/plat/arm/board/fvp/fvp_security.c
@@ -21,6 +21,6 @@ void plat_arm_security_setup(void)
         * configurations, those would be configured here.
         */
 
-       if (get_arm_config()->flags & ARM_CONFIG_HAS_TZC)
+       if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U)
                arm_tzc400_setup(NULL);
 }

diff --git a/plat/arm/board/fvp/fvp_topology.c b/plat/arm/board/fvp/fvp_topology.c
index a1e3f7f4bf9f2cc79adbe40f9be119f2e96d4cc8..e21b9d28c7245b9624e19be608ce5755614352c4 100644 (file)
--- a/plat/arm/board/fvp/fvp_topology.c
+++ b/plat/arm/board/fvp/fvp_topology.c
@@ -16,7 +16,8 @@
 static unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2];
 
 
-CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluster_count);
+CASSERT(((FVP_CLUSTER_COUNT > 0) && (FVP_CLUSTER_COUNT <= 256)),
+                       assert_invalid_fvp_cluster_count);
 
 /*******************************************************************************
  * This function dynamically constructs the topology according to
@@ -24,7 +25,7 @@ CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluste
  ******************************************************************************/
 const unsigned char *plat_get_power_domain_tree_desc(void)
 {
-       unsigned int i;
+       int i;
 
        /*
         * The highest level is the system level. The next level is constituted
@@ -60,7 +61,7 @@ int plat_core_pos_by_mpidr(u_register_t mpidr)
        unsigned int clus_id, cpu_id, thread_id;
 
        /* Validate affinity fields */
-       if (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) {
+       if ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) {
                thread_id = MPIDR_AFFLVL0_VAL(mpidr);
                cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
                clus_id = MPIDR_AFFLVL2_VAL(mpidr);
@@ -90,5 +91,5 @@ int plat_core_pos_by_mpidr(u_register_t mpidr)
         * bit set.
         */
        mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
-       return plat_arm_calc_core_pos(mpidr);
+       return (int) plat_arm_calc_core_pos(mpidr);
 }

diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index e4df227d75568e01aeab94d10e1c924eafa168b4..8f1a0cda94d5c18fb2054242e53d7d130b172a71 100644 (file)
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -52,7 +52,7 @@
 #define PLAT_ARM_TRUSTED_DRAM_SIZE     0x02000000      /* 32 MB */
 
 /* virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME   0xc0000000
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME   UL(0xc0000000)
 
 /* No SCP in FVP */
 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE    ULL(0x0)
@@ -215,9 +215,9 @@
  */
 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \
        ARM_G1S_IRQ_PROPS(grp), \
-       INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
+       INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \
                        GIC_INTR_CFG_LEVEL), \
-       INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+       INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
                        GIC_INTR_CFG_LEVEL)
 
 #define PLAT_ARM_G0_IRQ_PROPS(grp)     ARM_G0_IRQ_PROPS(grp)

diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index d130bebe8ee2da3936fee3c0676c5b4066b17ad7..ed78b461041e6b0e52303a3cc015bd07881c8e54 100644 (file)
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -60,7 +60,7 @@
 #define NSRAM_SIZE                     0x00008000      /* 32KB */
 
 /* virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME   0xc0000000
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME   UL(0xc0000000)
 
 /*
  * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB
@@ -236,21 +236,21 @@
        CSS_G1S_IRQ_PROPS(grp), \
        ARM_G1S_IRQ_PROPS(grp), \
        INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-               grp, GIC_INTR_CFG_LEVEL), \
+               (grp), GIC_INTR_CFG_LEVEL), \
        INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-               grp, GIC_INTR_CFG_LEVEL), \
+               (grp), GIC_INTR_CFG_LEVEL), \
        INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-               grp, GIC_INTR_CFG_LEVEL), \
+               (grp), GIC_INTR_CFG_LEVEL), \
        INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-               grp, GIC_INTR_CFG_LEVEL), \
+               (grp), GIC_INTR_CFG_LEVEL), \
        INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-               grp, GIC_INTR_CFG_LEVEL), \
+               (grp), GIC_INTR_CFG_LEVEL), \
        INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \
-               grp, GIC_INTR_CFG_LEVEL), \
+               (grp), GIC_INTR_CFG_LEVEL), \
        INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \
-               grp, GIC_INTR_CFG_LEVEL), \
+               (grp), GIC_INTR_CFG_LEVEL), \
        INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-               grp, GIC_INTR_CFG_LEVEL)
+               (grp), GIC_INTR_CFG_LEVEL)
 
 #define PLAT_ARM_G0_IRQ_PROPS(grp)     ARM_G0_IRQ_PROPS(grp)
 

diff --git a/plat/arm/board/juno/juno_topology.c b/plat/arm/board/juno/juno_topology.c
index 5f031c84ab10de6140f6152448850a4a1fa3c06f..72bb92e0054455d4cbb4d8586f25805f512264a9 100644 (file)
--- a/plat/arm/board/juno/juno_topology.c
+++ b/plat/arm/board/juno/juno_topology.c
@@ -50,8 +50,8 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
  ******************************************************************************/
 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
 {
-       return (((mpidr) & 0x100) ? JUNO_CLUSTER1_CORE_COUNT :\
-                               JUNO_CLUSTER0_CORE_COUNT);
+       return (((mpidr & (u_register_t) 0x100) != 0U) ?
+                       JUNO_CLUSTER1_CORE_COUNT : JUNO_CLUSTER0_CORE_COUNT);
 }
 
 /*

diff --git a/plat/arm/common/arm_nor_psci_mem_protect.c b/plat/arm/common/arm_nor_psci_mem_protect.c
index 1b0b1da66cc21090622ad624bb71a35a5c2e40f2..597bc509f8228a7bc15b46b14f4018fa65cd7374 100644 (file)
--- a/plat/arm/common/arm_nor_psci_mem_protect.c
+++ b/plat/arm/common/arm_nor_psci_mem_protect.c
@@ -51,14 +51,14 @@ int arm_psci_read_mem_protect(int *enabled)
  ******************************************************************************/
 int arm_nor_psci_write_mem_protect(int val)
 {
-       int enable = (val != 0) ? 1 : 0;
+       unsigned long enable = (val != 0) ? 1UL : 0UL;
 
        if (nor_unlock(PLAT_ARM_MEM_PROT_ADDR) != 0) {
                ERROR("unlocking memory protect variable\n");
                return -1;
        }
 
-       if (enable == 1) {
+       if (enable == 1UL) {
                /*
                 * If we want to write a value different than 0
                 * then we have to erase the full block because

diff --git a/plat/arm/common/arm_topology.c b/plat/arm/common/arm_topology.c
index c6d12dade4e9bf5eb77187388aefcfbf404a1e45..b0ad4d1c6a0f81cd238c820b78ff640ab5a4f840 100644 (file)
--- a/plat/arm/common/arm_topology.c
+++ b/plat/arm/common/arm_topology.c
@@ -29,12 +29,14 @@ int arm_check_mpidr(u_register_t mpidr)
        pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
 #else
        valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK);
-       cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
-       cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+       cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) &
+                                               MPIDR_AFFLVL_MASK);
+       cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) &
+                                               MPIDR_AFFLVL_MASK);
 #endif /* ARM_PLAT_MT */
 
        mpidr &= MPIDR_AFFINITY_MASK;
-       if (mpidr & valid_mask)
+       if ((mpidr & valid_mask) != 0U)
                return -1;
 
        if (cluster_id >= PLAT_ARM_CLUSTER_COUNT)