{
u32 i;
u32 val;
- u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
+ u32 is_BGA = (rt_sysc_r32(SYSC_REG_CHIP_REV_ID) >> 16) & 1;
+
+ /* Internal ethernet requires PCIe RC mode */
+ rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);
- rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
/* Enable MIB stats */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16),
GSW_REG_GPC1);
- fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
+ fe_reset(MT7620A_RESET_EPHY);
pr_info("gsw: ephy base address: %d\n", gsw->ephy_base);
}
#define SYSC_REG_CHIP_REV_ID 0x0c
#define SYSC_REG_CFG1 0x14
-#define RST_CTRL_MCM BIT(2)
+#define PCIE_RC_MODE BIT(8)
#define SYSC_PAD_RGMII2_MDIO 0x58
#define SYSC_GPIO_MODE 0x60
FE_FLAG_MAX
};
-#define MTK_FE_DRV_VERSION "0.1.2"
+#define MTK_FE_DRV_VERSION "0.2"
/* power of 2 to let NEXT_TX_DESP_IDX work */
#define NUM_DMA_DESC BIT(10)
#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
+#define MT7620A_RESET_FE BIT(21)
+#define MT7620A_RESET_ESW BIT(23)
+#define MT7620A_RESET_EPHY BIT(24)
+
#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
#define MT7620A_CDMA_CSG_CFG 0x400
#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
-#define MT7620A_RESET_FE BIT(21)
-#define MT7620A_RESET_ESW BIT(23)
#define MT7620_L4_VALID BIT(23)
#define MT7620_TX_DMA_UDF BIT(15)