drm/amd/display: fix calculation of total_data_read_bandwidth

[why]
by adding fast_validate flag, we are skipping some portion of
dcn_validate_bandwidth code that is not necessary for mode validation.
However we have a bug where it does not calculate
v->total_data_read_bandwidth, which is one of the factors determines the
result of the validation, and therefore report false positive during
mode validation.

[how]
add calculation of v->total_data_read_bandwidth outside of the region
that is guarded by fast_validate flag

Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index d53306de2e163e2f518deb93853acfe3822fe133..0a336c80c7bb58566753346ee0272d7a94995e9b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -711,7 +711,7 @@ bool dcn_validate_bandwidth(
 
        const struct resource_pool *pool = dc->res_pool;
        struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
-       int i, input_idx;
+       int i, input_idx, k;
        int vesa_sync_start, asic_blank_end, asic_blank_start;
        bool bw_limit_pass;
        float bw_limit;
@@ -1022,6 +1022,43 @@ bool dcn_validate_bandwidth(
                mode_support_and_system_configuration(v);
        }
 
+       display_pipe_configuration(v);
+
+       for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+               if (v->source_scan[k] == dcn_bw_hor)
+                       v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
+               else
+                       v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
+       }
+       for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+               if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
+                       v->byte_per_pixel_dety[k] = 8.0;
+                       v->byte_per_pixel_detc[k] = 0.0;
+               } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
+                       v->byte_per_pixel_dety[k] = 4.0;
+                       v->byte_per_pixel_detc[k] = 0.0;
+               } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
+                       v->byte_per_pixel_dety[k] = 2.0;
+                       v->byte_per_pixel_detc[k] = 0.0;
+               } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
+                       v->byte_per_pixel_dety[k] = 1.0;
+                       v->byte_per_pixel_detc[k] = 2.0;
+               } else {
+                       v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
+                       v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
+               }
+       }
+
+       v->total_data_read_bandwidth = 0.0;
+       for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+               v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *
+                               dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
+               v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *
+                               dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
+               v->total_data_read_bandwidth = v->total_data_read_bandwidth +
+                               v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
+       }
+
        BW_VAL_TRACE_END_VOLTAGE_LEVEL();
 
        if (v->voltage_level != number_of_states_plus_one && !fast_validate) {