* after calling pcibios_enable_device().
*/
if (sb_coreid(sbh) == SB_USB) {
+ printk(KERN_INFO "SB USB 1.1 init\n");
sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
sb_core_reset(sbh, 1 << 29, 0);
}
* phy components out of reset.
*/
else if (sb_coreid(sbh) == SB_USB20H) {
+
+ uint corerev = sb_corerev(sbh);
+
+ printk(KERN_INFO "SB USB20H init\n");
+ printk(KERN_INFO "SB COREREV: %d\n", corerev);
+
if (!sb_iscoreup(sbh)) {
+
+ printk(KERN_INFO "SB USB20H resetting\n");
+
sb_core_reset(sbh, 0, 0);
writel(0x7FF, (ulong)regs + 0x200);
udelay(1);
}
/* PRxxxx: War for 5354 failures. */
- if (sb_corerev(sbh) == 1) {
+ if (corerev == 1 || corerev == 2) {
uint32 tmp;
/* Change Flush control reg */
tmp &= ~8;
writel(tmp, (uintptr)regs + 0x400);
tmp = readl((uintptr)regs + 0x400);
- printk("USB20H fcr: 0x%x\n", tmp);
+ printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp);
/* Change Shim control reg */
tmp = readl((uintptr)regs + 0x304);
tmp &= ~0x100;
writel(tmp, (uintptr)regs + 0x304);
tmp = readl((uintptr)regs + 0x304);
- printk("USB20H shim cr: 0x%x\n", tmp);
+ printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp);
}
} else