powerpc: PTRACE_PEEKUSR/PTRACE_POKEUSER of FPR registers in little endian builds

FPRs overlap the high 64bits of the first 32 VSX registers. The
ptrace FP read/write code assumes big endian ordering and grabs
the lowest 64 bits.

Fix this by using the TS_FPR macro which does the right thing.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 9a0d24c390a3535e16c934f80ec19695da04d095..8d5d4e921a5e71756df0df01cb306158b8b55bf5 100644 (file)
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1554,8 +1554,8 @@ long arch_ptrace(struct task_struct *child, long request,
 
                        flush_fp_to_thread(child);
                        if (fpidx < (PT_FPSCR - PT_FPR0))
-                               tmp = ((unsigned long *)child->thread.fpr)
-                                       [fpidx * TS_FPRWIDTH];
+                               memcpy(&tmp, &child->thread.TS_FPR(fpidx),
+                                      sizeof(long));
                        else
                                tmp = child->thread.fpscr.val;
                }
@@ -1587,8 +1587,8 @@ long arch_ptrace(struct task_struct *child, long request,
 
                        flush_fp_to_thread(child);
                        if (fpidx < (PT_FPSCR - PT_FPR0))
-                               ((unsigned long *)child->thread.fpr)
-                                       [fpidx * TS_FPRWIDTH] = data;
+                               memcpy(&child->thread.TS_FPR(fpidx), &data,
+                                      sizeof(long));
                        else
                                child->thread.fpscr.val = data;
                        ret = 0;