CPU_SUBTYPE:=vfp
MAINTAINER:=Felix Fietkau <nbd@openwrt.org>
-KERNEL_PATCHVER:=3.18
+KERNEL_PATCHVER:=4.4
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_CNS3XXX=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_NR_GPIO=0
-# CONFIG_ARCH_OMAP2 is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-# CONFIG_ARCH_WM8750 is not set
-CONFIG_ARM=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-# CONFIG_ATA_SFF is not set
-CONFIG_ATA_VERBOSE_ERROR=y
-# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CNS3XXX_ETH=y
-CONFIG_COMMON_CLK=y
-# CONFIG_COMMON_CLK_PXA is not set
-CONFIG_CPU_32v6=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_ABRT_EV6=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_V6K=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_UART_BCM63XX is not set
-# CONFIG_DEBUG_UART_PL01X is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DMA_CACHE_FIQ_BROADCAST=y
-CONFIG_DTC=y
-CONFIG_EEPROM_AT24=y
-CONFIG_FIQ=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_SCU=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HWMON=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_CNS3XXX=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_INTEL_SOC_PMIC is not set
-CONFIG_IOMMU_HELPER=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_TRIGGER_NETDEV is not set
-CONFIG_LIBFDT=y
-# CONFIG_MACH_CNS3420VB is not set
-CONFIG_MACH_GW2388=y
-CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MFD_AXP20X is not set
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_CNS3XXX=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_OF_PARTS is not set
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_OF is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_VENDOR_CAVIUM=y
-CONFIG_NLS=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NR_CPUS=2
-CONFIG_NTP_PPS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PHY_SAMSUNG_USB2 is not set
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_PL310_ERRATA_727915=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_PPS=y
-CONFIG_PPS_CLIENT_GPIO=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_PROC_STRIPPED is not set
-CONFIG_RAID_ATTRS=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1672=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_SATA_AHCI=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-CONFIG_SENSORS_AD7418=y
-CONFIG_SENSORS_GSC=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_CNS3XXX=y
-CONFIG_SPI_MASTER=y
-# CONFIG_STAGING is not set
-CONFIG_STOP_MACHINE=y
-CONFIG_SWIOTLB=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TREE_RCU=y
-CONFIG_UID16=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_CNS3XXX_EHCI=y
-CONFIG_USB_CNS3XXX_OHCI=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC2=y
-# CONFIG_USB_DWC2_DEBUG is not set
-CONFIG_USB_DWC2_HOST=y
-# CONFIG_USB_DWC2_PCI is not set
-# CONFIG_USB_DWC2_PERIPHERAL is not set
-CONFIG_USB_DWC2_PLATFORM=y
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_EHCI_PCI=y
-# CONFIG_USB_ETH is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_XILINX is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_CNS3XXX=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_NR_GPIO=0
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_ARCH_WM8750 is not set
+CONFIG_ARM=y
+# CONFIG_ARM_CPU_SUSPEND is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+# CONFIG_ATA_SFF is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BCM_NET_PHYLIB=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CNS3XXX_ETH=y
+CONFIG_COMMON_CLK=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_ABRT_EV6=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_RMAP=y
+# CONFIG_CPU_SW_DOMAIN_PAN is not set
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_V6K=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DMA_CACHE_FIQ_BROADCAST=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_FIQ=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FRAME_POINTER=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HWMON=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_CNS3XXX=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IOMMU_HELPER=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_TRIGGER_NETDEV is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+# CONFIG_MACH_CNS3420VB is not set
+CONFIG_MACH_GW2388=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_CNS3XXX=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_OF_PARTS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_OF is not set
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NR_CPUS=2
+CONFIG_NTP_PPS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PPS=y
+CONFIG_PPS_CLIENT_GPIO=y
+# CONFIG_PROC_STRIPPED is not set
+CONFIG_RAID_ATTRS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1672=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SCHED_HRTICK=y
+# CONFIG_SCHED_INFO is not set
+CONFIG_SCSI=y
+CONFIG_SENSORS_AD7418=y
+CONFIG_SENSORS_GSC=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_CNS3XXX=y
+CONFIG_SPI_MASTER=y
+CONFIG_SRCU=y
+# CONFIG_STAGING is not set
+# CONFIG_SUNXI_SRAM is not set
+CONFIG_SWIOTLB=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_CNS3XXX_EHCI=y
+CONFIG_USB_CNS3XXX_OHCI=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_HOST=y
+# CONFIG_USB_DWC2_PCI is not set
+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_PCI=y
+# CONFIG_USB_ETH is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZONE_DMA_FLAG=0
/* one interrupt per GPIO controller (GPIOA/GPIOB)
* this is called in task context, with IRQs enabled
*/
-static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+static void cns3xxx_gpio_irq_handler(struct irq_desc *desc)
{
- struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq);
- struct irq_chip *chip = irq_get_chip(irq);
+ struct cns3xxx_gpio_chip *cchip = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
u16 i;
u32 reg;
spin_unlock_irqrestore(&cchip->lock, flags);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
- __irq_set_handler_locked(d->irq, handle_level_irq);
+ irq_set_handler_locked(d, handle_level_irq);
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
- __irq_set_handler_locked(d->irq, handle_edge_irq);
+ irq_set_handler_locked(d, handle_edge_irq);
return 0;
}
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -1,3 +1,5 @@
-+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-+
- obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
- cns3xxx-y += core.o pm.o
- cns3xxx-$(CONFIG_ATAGS) += devices.o
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -339,7 +339,7 @@ static struct usb_ohci_pdata cns3xxx_usb
- .power_off = csn3xxx_usb_power_off,
- };
-
--static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
-+static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
- { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
- { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
- { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
+++ /dev/null
---- a/arch/arm/include/asm/glue-cache.h
-+++ b/arch/arm/include/asm/glue-cache.h
-@@ -156,11 +156,19 @@ static inline void nop_dma_unmap_area(co
- #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
- #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
- #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
-+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
- #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
-
- #define dmac_map_area __glue(_CACHE,_dma_map_area)
- #define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
- #define dmac_flush_range __glue(_CACHE,_dma_flush_range)
-+#else
-+#define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area)
-+
-+#define dmac_map_area __glue(fiq,_dma_map_area)
-+#define dmac_unmap_area __glue(fiq,_dma_unmap_area)
-+#define dmac_flush_range __glue(fiq,_dma_flush_range)
-+#endif /* CONFIG_DMA_CACHE_FIQ_BROADCAST */
- #endif
-
- #endif
---- a/arch/arm/mm/Kconfig
-+++ b/arch/arm/mm/Kconfig
-@@ -844,6 +844,17 @@ config DMA_CACHE_RWFO
- in hardware, other workarounds are needed (e.g. cache
- maintenance broadcasting in software via FIQ).
-
-+config DMA_CACHE_FIQ_BROADCAST
-+ bool "Enable fiq broadcast DMA cache maintenance"
-+ depends on CPU_V6K && SMP
-+ select FIQ
-+ help
-+ The Snoop Control Unit on ARM11MPCore does not detect the
-+ cache maintenance operations and the dma_{map,unmap}_area()
-+ functions may leave stale cache entries on other CPUs. By
-+ enabling this option, fiq broadcast in the ARMv6
-+ DMA cache maintenance functions is performed.
-+
- config OUTER_CACHE
- bool
-
---- a/arch/arm/mm/flush.c
-+++ b/arch/arm/mm/flush.c
-@@ -304,6 +304,7 @@ void __sync_icache_dcache(pte_t pteval)
- void flush_dcache_page(struct page *page)
- {
- struct address_space *mapping;
-+ bool skip_broadcast = true;
-
- /*
- * The zero page is never written to, so never has any dirty
-@@ -314,7 +315,10 @@ void flush_dcache_page(struct page *page
-
- mapping = page_mapping(page);
-
-- if (!cache_ops_need_broadcast() &&
-+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
-+ skip_broadcast = !cache_ops_need_broadcast();
-+#endif
-+ if (skip_broadcast &&
- mapping && !page_mapped(page))
- clear_bit(PG_dcache_clean, &page->flags);
- else {
+++ /dev/null
-1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog
- since the CNS3xxx SOCs have ARM11 MPcore CPU.
-2. Enable mpcore_watchdog option as module to default configuration at
- arch/arm/configs/cns3420vb_defconfig.
-
-Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com>
-
----
-arch/arm/Kconfig | 1 +
- arch/arm/configs/cns3420vb_defconfig | 2 ++
- arch/arm/mach-cns3xxx/cns3420vb.c | 22 ++++++++++++++++++++++
- 3 files changed, 25 insertions(+), 0 deletions(-)
-
---- a/arch/arm/configs/cns3420vb_defconfig
-+++ b/arch/arm/configs/cns3420vb_defconfig
-@@ -56,6 +56,8 @@ CONFIG_LEGACY_PTY_COUNT=16
- # CONFIG_HW_RANDOM is not set
- # CONFIG_HWMON is not set
- # CONFIG_VGA_CONSOLE is not set
-+CONFIG_WATCHDOG=y
-+CONFIG_MPCORE_WATCHDOG=m
- # CONFIG_HID_SUPPORT is not set
- # CONFIG_USB_SUPPORT is not set
- CONFIG_MMC=y
---- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -206,10 +206,32 @@ static struct platform_device cns3xxx_us
- },
- };
-
-+/* Watchdog */
-+static struct resource cns3xxx_watchdog_resources[] = {
-+ [0] = {
-+ .start = CNS3XXX_TC11MP_TWD_BASE,
-+ .end = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_LOCALWDOG,
-+ .end = IRQ_LOCALWDOG,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device cns3xxx_watchdog_device = {
-+ .name = "mpcore_wdt",
-+ .id = -1,
-+ .num_resources = ARRAY_SIZE(cns3xxx_watchdog_resources),
-+ .resource = cns3xxx_watchdog_resources,
-+};
-+
- /*
- * Initialization
- */
- static struct platform_device *cns3420_pdevs[] __initdata = {
-+ &cns3xxx_watchdog_device,
- &cns3420_nor_pdev,
- &cns3xxx_usb_ehci_device,
- &cns3xxx_usb_ohci_device,
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -5,3 +5,5 @@ cns3xxx-y += core.o pm.o
- cns3xxx-$(CONFIG_ATAGS) += devices.o
- cns3xxx-$(CONFIG_PCI) += pcie.o
- cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
-+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
-+cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
---- a/arch/arm/mach-cns3xxx/Kconfig
-+++ b/arch/arm/mach-cns3xxx/Kconfig
-@@ -2,6 +2,9 @@ menuconfig ARCH_CNS3XXX
- bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
- select ARM_GIC
- select PCI_DOMAINS if PCI
-+ select HAVE_ARM_SCU if SMP
-+ select HAVE_ARM_TWD
-+ select HAVE_SMP
- help
- Support for Cavium Networks CNS3XXX platform.
-
---- a/arch/arm/mach-cns3xxx/core.h
-+++ b/arch/arm/mach-cns3xxx/core.h
-@@ -13,6 +13,7 @@
-
- #include <linux/reboot.h>
-
-+extern struct smp_operations cns3xxx_smp_ops;
- extern void cns3xxx_timer_init(void);
-
- #ifdef CONFIG_CACHE_L2X0
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -331,8 +331,6 @@ void __init cns3xxx_pcie_init_late(void)
- "imprecise external abort");
-
- for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
-- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
-- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
- cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
- cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
- pci_common_init(&cns3xxx_pcie[i].hw_pci);
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/laguna.c
-+++ b/arch/arm/mach-cns3xxx/laguna.c
-@@ -849,7 +849,6 @@ static struct map_desc laguna_io_desc[]
- static void __init laguna_map_io(void)
- {
- cns3xxx_map_io();
-- cns3xxx_pcie_iotable_init();
- iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
- laguna_early_serial_setup();
- }
-@@ -873,15 +872,6 @@ static int laguna_register_gpio(struct g
- return ret;
- }
-
--static int __init laguna_pcie_init(void)
--{
-- if (!machine_is_gw2388())
-- return 0;
--
-- return cns3xxx_pcie_init();
--}
--subsys_initcall(laguna_pcie_init);
--
- static int __init laguna_model_setup(void)
- {
- u32 __iomem *mem;
-@@ -1077,5 +1067,6 @@ MACHINE_START(GW2388, "Gateworks Corpora
- .init_irq = cns3xxx_init_irq,
- .init_time = cns3xxx_timer_init,
- .init_machine = laguna_init,
-+ .init_late = cns3xxx_pcie_init_late,
- .restart = cns3xxx_restart,
- MACHINE_END
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/Kconfig
-+++ b/arch/arm/mach-cns3xxx/Kconfig
-@@ -5,6 +5,7 @@ menuconfig ARCH_CNS3XXX
- select HAVE_ARM_SCU if SMP
- select HAVE_ARM_TWD
- select HAVE_SMP
-+ select FIQ
- help
- Support for Cavium Networks CNS3XXX platform.
-
---- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -5,5 +5,5 @@ cns3xxx-y += core.o pm.o
- cns3xxx-$(CONFIG_ATAGS) += devices.o
- cns3xxx-$(CONFIG_PCI) += pcie.o
- cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
--cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
-+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
- cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
---- a/arch/arm/mach-cns3xxx/cns3xxx.h
-+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
-@@ -267,6 +267,7 @@
- #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
- #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
-
-+#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4)
- /*
- * Power management and clock control
- */
---- a/arch/arm/mm/Kconfig
-+++ b/arch/arm/mm/Kconfig
-@@ -827,7 +827,7 @@ config KUSER_HELPERS
-
- config DMA_CACHE_RWFO
- bool "Enable read/write for ownership DMA cache maintenance"
-- depends on CPU_V6K && SMP
-+ depends on CPU_V6K && SMP && !ARCH_CNS3XXX
- default y
- help
- The Snoop Control Unit on ARM11MPCore does not detect the
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -17,6 +17,7 @@
- #include <linux/platform_device.h>
- #include <linux/usb/ehci_pdriver.h>
- #include <linux/usb/ohci_pdriver.h>
-+#include <asm/smp_twd.h>
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- #include <asm/mach/time.h>
-@@ -26,6 +27,8 @@
- #include "core.h"
- #include "pm.h"
-
-+#define IRQ_LOCALTIMER 29
-+
- static struct map_desc cns3xxx_io_desc[] __initdata = {
- {
- .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
-@@ -191,6 +194,15 @@ static struct irqaction cns3xxx_timer_ir
- .handler = cns3xxx_timer_interrupt,
- };
-
-+static void __init cns3xxx_init_twd(void)
-+{
-+ static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer,
-+ CNS3XXX_TC11MP_TWD_BASE,
-+ IRQ_LOCALTIMER);
-+
-+ twd_local_timer_register(&cns3xx_twd_local_timer);
-+}
-+
- /*
- * Set up the clock source and clock events devices
- */
-@@ -244,6 +256,7 @@ static void __init __cns3xxx_timer_init(
- setup_irq(timer_irq, &cns3xxx_timer_irq);
-
- cns3xxx_clockevents_init(timer_irq);
-+ cns3xxx_init_twd();
- }
-
- void __init cns3xxx_timer_init(void)
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -81,6 +81,16 @@ static struct map_desc cns3xxx_io_desc[]
- .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
- .length = SZ_16M,
- .type = MT_DEVICE,
-+ }, {
-+ .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT,
-+ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE),
-+ .length = SZ_16M,
-+ .type = MT_DEVICE,
-+ }, {
-+ .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT,
-+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
-+ .length = SZ_16M,
-+ .type = MT_DEVICE,
- #endif
- },
- };
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -88,6 +88,79 @@ static void __iomem *cns3xxx_pci_cfg_bas
- return base + (where & 0xffc) + (devfn << 12);
- }
-
-+static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where)
-+{
-+ struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
-+
-+ /* check PCI-compatible status register after access */
-+ if (cnspci->linked) {
-+ void __iomem *host_base;
-+ u32 sreg, ereg;
-+
-+ host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
-+ sreg = __raw_readw(host_base + 0x6) & 0xF900;
-+ ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
-+
-+ if (sreg | ereg) {
-+ /* SREG:
-+ * BIT15 - Detected Parity Error
-+ * BIT14 - Signaled System Error
-+ * BIT13 - Received Master Abort
-+ * BIT12 - Received Target Abort
-+ * BIT11 - Signaled Target Abort
-+ * BIT08 - Master Data Parity Error
-+ *
-+ * EREG:
-+ * BIT20 - Unsupported Request
-+ * BIT19 - ECRC
-+ * BIT18 - Malformed TLP
-+ * BIT17 - Receiver Overflow
-+ * BIT16 - Unexpected Completion
-+ * BIT15 - Completer Abort
-+ * BIT14 - Completion Timeout
-+ * BIT13 - Flow Control Protocol Error
-+ * BIT12 - Poisoned TLP
-+ * BIT04 - Data Link Protocol Error
-+ *
-+ * TODO: see Documentation/pci-error-recovery.txt
-+ * implement error_detected handler
-+ */
-+/*
-+ printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg);
-+ if (sreg & BIT(15)) printk(" <PERR");
-+ if (sreg & BIT(14)) printk(" >SERR");
-+ if (sreg & BIT(13)) printk(" <MABRT");
-+ if (sreg & BIT(12)) printk(" <TABRT");
-+ if (sreg & BIT(11)) printk(" >TABRT");
-+ if (sreg & BIT( 8)) printk(" MPERR");
-+
-+ if (ereg & BIT(20)) printk(" Unsup");
-+ if (ereg & BIT(19)) printk(" ECRC");
-+ if (ereg & BIT(18)) printk(" MTLP");
-+ if (ereg & BIT(17)) printk(" OFLOW");
-+ if (ereg & BIT(16)) printk(" Unex");
-+ if (ereg & BIT(15)) printk(" ABRT");
-+ if (ereg & BIT(14)) printk(" COMPTO");
-+ if (ereg & BIT(13)) printk(" FLOW");
-+ if (ereg & BIT(12)) printk(" PTLP");
-+ if (ereg & BIT( 4)) printk(" DLINK");
-+ printk("\n");
-+*/
-+ pr_debug("%s failed port%d sreg=0x%04x\n", __func__,
-+ cnspci->hw_pci.domain, sreg);
-+
-+ /* make sure the status bits are reset */
-+ __raw_writew(sreg, host_base + 6);
-+ __raw_writel(ereg, host_base + 0x104);
-+ return 1;
-+ }
-+ }
-+ else
-+ return 1;
-+
-+ return 0;
-+}
-+
- static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *val)
- {
-@@ -104,6 +177,11 @@ static int cns3xxx_pci_read_config(struc
-
- v = __raw_readl(base);
-
-+ if (check_master_abort(bus, devfn, where)) {
-+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ }
-+
- if (bus->number == 0 && devfn == 0 &&
- (where & 0xffc) == PCI_CLASS_REVISION) {
- /*
-@@ -133,11 +211,19 @@ static int cns3xxx_pci_write_config(stru
- return PCIBIOS_SUCCESSFUL;
-
- v = __raw_readl(base);
-+ if (check_master_abort(bus, devfn, where)) {
-+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ }
-
- v &= ~(mask << shift);
- v |= (val & mask) << shift;
-
- __raw_writel(v, base);
-+ if (check_master_abort(bus, devfn, where)) {
-+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on write\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ }
-
- return PCIBIOS_SUCCESSFUL;
- }
-@@ -315,8 +401,14 @@ static void __init cns3xxx_pcie_hw_init(
- static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
- struct pt_regs *regs)
- {
-+#if 0
-+/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE
-+ * ignore imprecise aborts and use PCI-compatible Status register to
-+ * determine errors instead
-+ */
- if (fsr & (1 << 10))
- regs->ARM_pc += 4;
-+#endif
- return 0;
- }
-
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -424,6 +424,8 @@ void __init cns3xxx_pcie_init_late(void)
-
- for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
- cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
-+ if (!cns3xxx_pcie[i].linked)
-+ continue;
- cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
- pci_common_init(&cns3xxx_pcie[i].hw_pci);
- }
+++ /dev/null
---- a/drivers/i2c/busses/Kconfig
-+++ b/drivers/i2c/busses/Kconfig
-@@ -417,6 +417,18 @@ config I2C_CBUS_GPIO
- This driver can also be built as a module. If so, the module
- will be called i2c-cbus-gpio.
-
-+config I2C_CNS3XXX
-+ tristate "Cavium CNS3xxx I2C driver"
-+ depends on ARCH_CNS3XXX
-+ help
-+ Support for Cavium CNS3xxx I2C controller driver.
-+
-+ This driver can also be built as a module. If so, the module
-+ will be called i2c-cns3xxx.
-+
-+ Please note that this driver might be needed to bring up other
-+ devices such as Cavium CNS3xxx Ethernet.
-+
- config I2C_CPM
- tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)"
- depends on CPM1 || CPM2
---- a/drivers/i2c/busses/Makefile
-+++ b/drivers/i2c/busses/Makefile
-@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-
- obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
- obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
- obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
-+obj-$(CONFIG_I2C_CNS3XXX) += i2c-cns3xxx.o
- obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
-
- ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
+++ /dev/null
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -171,6 +171,13 @@ config SPI_CLPS711X
- This enables dedicated general purpose SPI/Microwire1-compatible
- master mode interface (SSI1) for CLPS711X-based CPUs.
-
-+config SPI_CNS3XXX
-+ tristate "CNS3XXX SPI controller"
-+ depends on ARCH_CNS3XXX && SPI_MASTER
-+ select SPI_BITBANG
-+ help
-+ This enables using the CNS3XXX SPI controller in master mode.
-+
- config SPI_COLDFIRE_QSPI
- tristate "Freescale Coldfire QSPI controller"
- depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi-bitban
- obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
- obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o
- obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
-+obj-$(CONFIG_SPI_CNS3XXX) += spi-cns3xxx.o
- obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
- obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
- obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
---- a/drivers/spi/spi-bitbang.c
-+++ b/drivers/spi/spi-bitbang.c
-@@ -335,6 +335,10 @@ static int spi_bitbang_transfer_one(stru
- */
- if (!m->is_dma_mapped)
- t->rx_dma = t->tx_dma = 0;
-+
-+ t->last_in_message_list =
-+ list_is_last(&t->transfer_list, &m->transfers);
-+
- status = bitbang->txrx_bufs(spi, t);
- }
- if (status > 0)
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -630,6 +630,13 @@ struct spi_transfer {
- u32 speed_hz;
-
- struct list_head transfer_list;
-+
-+#ifdef CONFIG_ARCH_CNS3XXX
-+ unsigned last_in_message_list;
-+#ifdef CONFIG_SPI_CNS3XXX_2IOREAD
-+ u8 dio_read;
-+#endif
-+#endif
- };
-
- /**
+++ /dev/null
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -29,12 +29,23 @@ static const struct ata_port_info ahci_p
- .port_ops = &ahci_platform_ops,
- };
-
-+static const struct ata_port_info cns3xxx_port_info = {
-+ .flags = AHCI_FLAG_COMMON,
-+ .pio_mask = ATA_PIO4,
-+ .udma_mask = ATA_UDMA6,
-+ .port_ops = &ahci_pmp_retry_srst_ops,
-+};
-+
- static int ahci_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
- struct ahci_host_priv *hpriv;
-+ const struct ata_port_info *info = &ahci_port_info;
- int rc;
-
-+ if (IS_ENABLED(CONFIG_ARCH_CNS3XXX))
-+ info = &cns3xxx_port_info;
-+
- hpriv = ahci_platform_get_resources(pdev);
- if (IS_ERR(hpriv))
- return PTR_ERR(hpriv);
+++ /dev/null
---- a/drivers/net/ethernet/Kconfig
-+++ b/drivers/net/ethernet/Kconfig
-@@ -34,6 +34,7 @@ source "drivers/net/ethernet/adi/Kconfig
- source "drivers/net/ethernet/broadcom/Kconfig"
- source "drivers/net/ethernet/brocade/Kconfig"
- source "drivers/net/ethernet/calxeda/Kconfig"
-+source "drivers/net/ethernet/cavium/Kconfig"
- source "drivers/net/ethernet/chelsio/Kconfig"
- source "drivers/net/ethernet/cirrus/Kconfig"
- source "drivers/net/ethernet/cisco/Kconfig"
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -20,6 +20,7 @@ obj-$(CONFIG_NET_BFIN) += adi/
- obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/
- obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/
- obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/
-+obj-$(CONFIG_NET_VENDOR_CAVIUM) += cavium/
- obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/
- obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/
- obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -135,12 +135,13 @@ static void cns3xxx_timer_set_mode(enum
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
-- reload = pclk * 20 / (3 * HZ) * 0x25000;
-+ reload = pclk * 1000000 / HZ;
- writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
- ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
- break;
- case CLOCK_EVT_MODE_ONESHOT:
- /* period set, and timer enabled in 'next_event' hook */
-+ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
- ctrl |= (1 << 2) | (1 << 9);
- break;
- case CLOCK_EVT_MODE_UNUSED:
-@@ -168,7 +169,7 @@ static struct clock_event_device cns3xxx
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_mode = cns3xxx_timer_set_mode,
- .set_next_event = cns3xxx_timer_set_next_event,
-- .rating = 350,
-+ .rating = 300,
- .cpumask = cpu_all_mask,
- };
-
-@@ -213,6 +214,35 @@ static void __init cns3xxx_init_twd(void
- twd_local_timer_register(&cns3xx_twd_local_timer);
- }
-
-+static cycle_t cns3xxx_get_cycles(struct clocksource *cs)
-+{
-+ u64 val;
-+
-+ val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
-+ val &= 0xffff;
-+
-+ return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET));
-+}
-+
-+static struct clocksource clocksource_cns3xxx = {
-+ .name = "freerun",
-+ .rating = 200,
-+ .read = cns3xxx_get_cycles,
-+ .mask = CLOCKSOURCE_MASK(48),
-+ .shift = 16,
-+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-+};
-+
-+static void __init cns3xxx_clocksource_init(void)
-+{
-+ /* Reset the FreeRunning counter */
-+ writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
-+
-+ clocksource_cns3xxx.mult =
-+ clocksource_khz2mult(100, clocksource_cns3xxx.shift);
-+ clocksource_register(&clocksource_cns3xxx);
-+}
-+
- /*
- * Set up the clock source and clock events devices
- */
-@@ -230,13 +260,12 @@ static void __init __cns3xxx_timer_init(
- /* stop free running timer3 */
- writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
-
-- /* timer1 */
-- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
-- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
--
- writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
- writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
-
-+ val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ;
-+ writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
-+
- /* mask irq, non-mask timer1 overflow */
- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
- irq_mask &= ~(1 << 2);
-@@ -248,23 +277,9 @@ static void __init __cns3xxx_timer_init(
- val |= (1 << 9);
- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
-- /* timer2 */
-- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
-- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
--
-- /* mask irq */
-- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
-- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
-- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
--
-- /* down counter */
-- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-- val |= (1 << 10);
-- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
--
-- /* Make irqs happen for the system timer */
- setup_irq(timer_irq, &cns3xxx_timer_irq);
-
-+ cns3xxx_clocksource_init();
- cns3xxx_clockevents_init(timer_irq);
- cns3xxx_init_twd();
- }
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -245,6 +245,10 @@ static void __init cns3420_init(void)
-
- cns3xxx_ahci_init();
- cns3xxx_sdhci_init();
-+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
-+ NR_IRQS_CNS3XXX);
-+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
-+ NR_IRQS_CNS3XXX + 32);
-
- pm_power_off = cns3xxx_power_off;
- }
---- a/arch/arm/mach-cns3xxx/Kconfig
-+++ b/arch/arm/mach-cns3xxx/Kconfig
-@@ -1,6 +1,8 @@
- menuconfig ARCH_CNS3XXX
- bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
- select ARM_GIC
-+ select ARCH_REQUIRE_GPIOLIB
-+ select GENERIC_IRQ_CHIP
- select PCI_DOMAINS if PCI
- select HAVE_ARM_SCU if SMP
- select HAVE_ARM_TWD
---- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -1,7 +1,7 @@
- ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-
- obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
--cns3xxx-y += core.o pm.o
-+cns3xxx-y += core.o pm.o gpio.o
- cns3xxx-$(CONFIG_ATAGS) += devices.o
- cns3xxx-$(CONFIG_PCI) += pcie.o
- cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
---- a/arch/arm/mach-cns3xxx/cns3xxx.h
-+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
-@@ -68,8 +68,10 @@
- #define SMC_PCELL_ID_3_OFFSET 0xFFC
-
- #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
-+#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000
-
- #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
-+#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000
-
- #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
-
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[]
- .pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
-+ }, {
-+ .virtual = CNS3XXX_GPIOA_BASE_VIRT,
-+ .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE,
-+ }, {
-+ .virtual = CNS3XXX_GPIOB_BASE_VIRT,
-+ .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE,
- #ifdef CONFIG_PCI
- }, {
- .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -303,13 +303,26 @@ void __init cns3xxx_timer_init(void)
-
- #ifdef CONFIG_CACHE_L2X0
-
--void __init cns3xxx_l2x0_init(void)
-+static int cns3xxx_l2x0_enable = 1;
-+
-+static int __init cns3xxx_l2x0_disable(char *s)
-+{
-+ cns3xxx_l2x0_enable = 0;
-+ return 1;
-+}
-+__setup("nol2x0", cns3xxx_l2x0_disable);
-+
-+static int __init cns3xxx_l2x0_init(void)
- {
-- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
-+ void __iomem *base;
- u32 val;
-
-+ if (!cns3xxx_l2x0_enable)
-+ return 0;
-+
-+ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
- if (WARN_ON(!base))
-- return;
-+ return 0;
-
- /*
- * Tag RAM Control register
-@@ -339,7 +352,10 @@ void __init cns3xxx_l2x0_init(void)
-
- /* 32 KiB, 8-way, parity disable */
- l2x0_init(base, 0x00500000, 0xfe0f0fff);
-+
-+ return 0;
- }
-+arch_initcall(cns3xxx_l2x0_init);
-
- #endif /* CONFIG_CACHE_L2X0 */
-
---- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -239,8 +239,6 @@ static struct platform_device *cns3420_p
-
- static void __init cns3420_init(void)
- {
-- cns3xxx_l2x0_init();
--
- platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
-
- cns3xxx_ahci_init();
---- a/arch/arm/mach-cns3xxx/core.h
-+++ b/arch/arm/mach-cns3xxx/core.h
-@@ -16,12 +16,6 @@
- extern struct smp_operations cns3xxx_smp_ops;
- extern void cns3xxx_timer_init(void);
-
--#ifdef CONFIG_CACHE_L2X0
--void __init cns3xxx_l2x0_init(void);
--#else
--static inline void cns3xxx_l2x0_init(void) {}
--#endif /* CONFIG_CACHE_L2X0 */
--
- #ifdef CONFIG_PCI
- extern void __init cns3xxx_pcie_init_late(void);
- #else
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/Kconfig
-+++ b/arch/arm/mach-cns3xxx/Kconfig
-@@ -22,4 +22,12 @@ config MACH_CNS3420VB
- This is a platform with an on-board ARM11 MPCore and has support
- for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
-
-+config MACH_GW2388
-+ bool "Support for Gateworks Laguna Platform"
-+ help
-+ Include support for the Gateworks Laguna Platform
-+
-+ This is a platform with an on-board ARM11 MPCore and has support
-+ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
-+
- endif
---- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -7,3 +7,5 @@ cns3xxx-$(CONFIG_PCI) += pcie.o
- cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
- cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
- cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-+cns3xxx-$(CONFIG_MACH_GW2388) += laguna.o
-+
---- a/arch/arm/mach-cns3xxx/devices.c
-+++ b/arch/arm/mach-cns3xxx/devices.c
-@@ -16,6 +16,7 @@
- #include <linux/compiler.h>
- #include <linux/dma-mapping.h>
- #include <linux/platform_device.h>
-+#include <asm/mach-types.h>
- #include "cns3xxx.h"
- #include "pm.h"
- #include "core.h"
-@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void)
- u32 gpioa_pins = __raw_readl(gpioa);
-
- /* MMC/SD pins share with GPIOA */
-- gpioa_pins |= 0x1fff0004;
-+ if (machine_is_gw2388()) {
-+ gpioa_pins |= 0x1fff0000;
-+ } else {
-+ gpioa_pins |= 0x1fff0004;
-+ }
- __raw_writel(gpioa_pins, gpioa);
-
- cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
+++ /dev/null
---- a/drivers/mmc/host/sdhci-cns3xxx.c
-+++ b/drivers/mmc/host/sdhci-cns3xxx.c
-@@ -88,9 +88,9 @@ static const struct sdhci_pltfm_data sdh
- .ops = &sdhci_cns3xxx_ops,
- .quirks = SDHCI_QUIRK_BROKEN_DMA |
- SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
-- SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
- SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
-- SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
-+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
-+ SDHCI_QUIRK_BROKEN_CARD_DETECTION,
- };
-
- static int sdhci_cns3xxx_probe(struct platform_device *pdev)
+++ /dev/null
---- a/arch/arm/mach-cns3xxx/laguna.c
-+++ b/arch/arm/mach-cns3xxx/laguna.c
-@@ -21,6 +21,7 @@
- #include <linux/kernel.h>
- #include <linux/compiler.h>
- #include <linux/io.h>
-+#include <linux/irq.h>
- #include <linux/gpio.h>
- #include <linux/dma-mapping.h>
- #include <linux/serial_core.h>
-@@ -872,6 +873,47 @@ static int laguna_register_gpio(struct g
- return ret;
- }
-
-+/* allow disabling of external isolated PCIe IRQs */
-+static int cns3xxx_pciextirq = 1;
-+static int __init cns3xxx_pciextirq_disable(char *s)
-+{
-+ cns3xxx_pciextirq = 0;
-+ return 1;
-+}
-+__setup("noextirq", cns3xxx_pciextirq_disable);
-+
-+static int __init laguna_pcie_init_irq(void)
-+{
-+ u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
-+ u32 reg = (__raw_readl(mem) >> 26) & 0xf;
-+ int irqs[] = {
-+ IRQ_CNS3XXX_EXTERNAL_PIN0,
-+ IRQ_CNS3XXX_EXTERNAL_PIN1,
-+ IRQ_CNS3XXX_EXTERNAL_PIN2,
-+ 154,
-+ };
-+
-+ if (!machine_is_gw2388())
-+ return 0;
-+
-+ /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
-+ if (cns3xxx_pciextirq && reg != 1)
-+ cns3xxx_pciextirq = 0;
-+
-+ if (cns3xxx_pciextirq) {
-+ printk("laguna: using isolated PCI interrupts:"
-+ " irq%d/irq%d/irq%d/irq%d\n",
-+ irqs[0], irqs[1], irqs[2], irqs[3]);
-+ cns3xxx_pcie_set_irqs(0, irqs);
-+ } else {
-+ printk("laguna: using shared PCI interrupts: irq%d\n",
-+ IRQ_CNS3XXX_PCIE0_DEVICE);
-+ }
-+
-+ return 0;
-+}
-+subsys_initcall(laguna_pcie_init_irq);
-+
- static int __init laguna_model_setup(void)
- {
- u32 __iomem *mem;
-@@ -883,8 +925,33 @@ static int __init laguna_model_setup(voi
- printk("Running on Gateworks Laguna %s\n", laguna_info.model);
- cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
- NR_IRQS_CNS3XXX);
-- cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
-- NR_IRQS_CNS3XXX + 32);
-+
-+ /*
-+ * If pcie external interrupts are supported and desired
-+ * configure IRQ types and configure pin function.
-+ * Note that cns3xxx_pciextirq is enabled by default, but can be
-+ * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
-+ * the baseboard model does not support this hardware feature.
-+ */
-+ if (cns3xxx_pciextirq) {
-+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
-+ reg = __raw_readl(mem);
-+ /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
-+ reg &= ~0x3c000000;
-+ reg |= 0x38000000;
-+ __raw_writel(reg, mem);
-+
-+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
-+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
-+
-+ irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
-+ irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
-+ irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
-+ irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
-+ } else {
-+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
-+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
-+ }
-
- if (strncmp(laguna_info.model, "GW", 2) == 0) {
- if (laguna_info.config_bitmap & ETH0_LOAD)
---- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -18,6 +18,7 @@
- #include <linux/io.h>
- #include <linux/ioport.h>
- #include <linux/interrupt.h>
-+#include <linux/irq.h>
- #include <linux/ptrace.h>
- #include <asm/mach/map.h>
- #include "cns3xxx.h"
-@@ -27,7 +28,7 @@ struct cns3xxx_pcie {
- void __iomem *host_regs; /* PCI config registers for host bridge */
- void __iomem *cfg0_regs; /* PCI Type 0 config registers */
- void __iomem *cfg1_regs; /* PCI Type 1 config registers */
-- unsigned int irqs[2];
-+ unsigned int irqs[5];
- struct resource res_io;
- struct resource res_mem;
- struct hw_pci hw_pci;
-@@ -97,7 +98,7 @@ static inline int check_master_abort(str
- void __iomem *host_base;
- u32 sreg, ereg;
-
-- host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
-+ host_base = (void __iomem *) cnspci->host_regs;
- sreg = __raw_readw(host_base + 0x6) & 0xF900;
- ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
-
-@@ -251,7 +252,7 @@ static struct pci_ops cns3xxx_pcie_ops =
- static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
- {
- struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
-- int irq = cnspci->irqs[!!dev->bus->number];
-+ int irq = cnspci->irqs[!!dev->bus->number + pin - 1];
-
- pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
- pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
-@@ -277,7 +278,12 @@ static struct cns3xxx_pcie cns3xxx_pcie[
- .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
- .flags = IORESOURCE_MEM,
- },
-- .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
-+ .irqs = { IRQ_CNS3XXX_PCIE0_RC,
-+ IRQ_CNS3XXX_PCIE0_DEVICE,
-+ IRQ_CNS3XXX_PCIE0_DEVICE,
-+ IRQ_CNS3XXX_PCIE0_DEVICE,
-+ IRQ_CNS3XXX_PCIE0_DEVICE,
-+ },
- .hw_pci = {
- .domain = 0,
- .nr_controllers = 1,
-@@ -302,7 +308,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
- .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
- .flags = IORESOURCE_MEM,
- },
-- .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
-+ .irqs = {
-+ IRQ_CNS3XXX_PCIE1_RC,
-+ IRQ_CNS3XXX_PCIE1_DEVICE,
-+ IRQ_CNS3XXX_PCIE1_DEVICE,
-+ IRQ_CNS3XXX_PCIE1_DEVICE,
-+ IRQ_CNS3XXX_PCIE1_DEVICE,
-+ },
- .hw_pci = {
- .domain = 1,
- .nr_controllers = 1,
-@@ -412,6 +424,14 @@ static int cns3xxx_pcie_abort_handler(un
- return 0;
- }
-
-+void __init cns3xxx_pcie_set_irqs(int bus, int *irqs)
-+{
-+ int i;
-+
-+ for (i = 0; i < 4; i++)
-+ cns3xxx_pcie[bus].irqs[i + 1] = irqs[i];
-+}
-+
- void __init cns3xxx_pcie_init_late(void)
- {
- int i;
---- a/arch/arm/mach-cns3xxx/core.h
-+++ b/arch/arm/mach-cns3xxx/core.h
-@@ -18,8 +18,10 @@ extern void cns3xxx_timer_init(void);
-
- #ifdef CONFIG_PCI
- extern void __init cns3xxx_pcie_init_late(void);
-+extern void __init cns3xxx_pcie_set_irqs(int bus, int *irqs);
- #else
- static inline void __init cns3xxx_pcie_init_late(void) {}
-+static inline void cns3xxx_pcie_set_irqs(int bus, int *irqs) {}
- #endif
-
- void __init cns3xxx_map_io(void);
+++ /dev/null
---- a/drivers/net/phy/broadcom.c
-+++ b/drivers/net/phy/broadcom.c
-@@ -393,6 +393,11 @@ static int bcm5481_config_aneg(struct ph
- /* Write bits 14:0. */
- reg |= (1 << 15);
- phy_write(phydev, 0x18, reg);
-+ } else {
-+ phy_write(phydev, 0x18, 0xf1e7);
-+ phy_write(phydev, 0x1c, 0x8e00);
-+
-+ phy_write(phydev, 0x1c, 0xa41f);
- }
-
- return ret;
+++ /dev/null
---- a/drivers/usb/dwc2/platform.c
-+++ b/drivers/usb/dwc2/platform.c
-@@ -105,6 +105,34 @@ static const struct dwc2_core_params par
- .uframe_sched = -1,
- };
-
-+static const struct dwc2_core_params params_cns3xxx = {
-+ .otg_cap = 2, /* non-HNP/non-SRP capable */
-+ .otg_ver = 0, /* 1.3 */
-+ .dma_enable = 1,
-+ .dma_desc_enable = 0,
-+ .speed = 0, /* High Speed */
-+ .enable_dynamic_fifo = 1,
-+ .en_multiple_tx_fifo = 1,
-+ .host_rx_fifo_size = 658, /* 774 DWORDs */
-+ .host_nperio_tx_fifo_size = 128, /* 256 DWORDs */
-+ .host_perio_tx_fifo_size = 658, /* 512 DWORDs */
-+ .max_transfer_size = 65535,
-+ .max_packet_count = 511,
-+ .host_channels = 16,
-+ .phy_type = 1, /* UTMI */
-+ .phy_utmi_width = 16, /* 8 bits */
-+ .phy_ulpi_ddr = 0, /* Single */
-+ .phy_ulpi_ext_vbus = 0,
-+ .i2c_enable = 0,
-+ .ulpi_fs_ls = 0,
-+ .host_support_fs_ls_low_power = 0,
-+ .host_ls_low_power_phy_clk = 0, /* 48 MHz */
-+ .ts_dline = 0,
-+ .reload_ctl = 0,
-+ .ahbcfg = 0x10,
-+ .uframe_sched = 0,
-+};
-+
- /**
- * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
- * DWC_otg driver
-@@ -165,6 +193,9 @@ static int dwc2_driver_probe(struct plat
- /* Default all params to autodetect */
- dwc2_set_all_params(&defparams, -1);
- params = &defparams;
-+#ifdef CONFIG_ARCH_CNS3XXX
-+ params = ¶ms_cns3xxx;
-+#endif
-
- /*
- * Disable descriptor dma mode by default as the HW can support
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -1,3 +1,5 @@
++ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
++
+ obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
+ cns3xxx-y += core.o pm.o
+ cns3xxx-$(CONFIG_ATAGS) += devices.o
--- /dev/null
+--- a/arch/arm/include/asm/glue-cache.h
++++ b/arch/arm/include/asm/glue-cache.h
+@@ -156,9 +156,15 @@ static inline void nop_dma_unmap_area(co
+ #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
+ #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
+ #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
+-#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
+
+-#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
++# define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
++# define dmac_flush_range __glue(_CACHE,_dma_flush_range)
++#else
++# define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area)
++# define dmac_flush_range __glue(fiq,_dma_flush_range)
++#endif
++
+ #endif
+
+ #endif
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -866,6 +866,17 @@ config DMA_CACHE_RWFO
+ in hardware, other workarounds are needed (e.g. cache
+ maintenance broadcasting in software via FIQ).
+
++config DMA_CACHE_FIQ_BROADCAST
++ bool "Enable fiq broadcast DMA cache maintenance"
++ depends on CPU_V6K && SMP
++ select FIQ
++ help
++ The Snoop Control Unit on ARM11MPCore does not detect the
++ cache maintenance operations and the dma_{map,unmap}_area()
++ functions may leave stale cache entries on other CPUs. By
++ enabling this option, fiq broadcast in the ARMv6
++ DMA cache maintenance functions is performed.
++
+ config OUTER_CACHE
+ bool
+
+--- a/arch/arm/mm/flush.c
++++ b/arch/arm/mm/flush.c
+@@ -319,6 +319,7 @@ void __sync_icache_dcache(pte_t pteval)
+ void flush_dcache_page(struct page *page)
+ {
+ struct address_space *mapping;
++ bool skip_broadcast = true;
+
+ /*
+ * The zero page is never written to, so never has any dirty
+@@ -329,7 +330,10 @@ void flush_dcache_page(struct page *page
+
+ mapping = page_mapping(page);
+
+- if (!cache_ops_need_broadcast() &&
++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
++ skip_broadcast = !cache_ops_need_broadcast();
++#endif
++ if (skip_broadcast &&
+ mapping && !page_mapped(page))
+ clear_bit(PG_dcache_clean, &page->flags);
+ else {
+--- a/arch/arm/mm/dma.h
++++ b/arch/arm/mm/dma.h
+@@ -4,8 +4,13 @@
+ #include <asm/glue-cache.h>
+
+ #ifndef MULTI_CACHE
+-#define dmac_map_area __glue(_CACHE,_dma_map_area)
+-#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
++# define dmac_map_area __glue(_CACHE,_dma_map_area)
++# define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
++#else
++# define dmac_map_area __glue(fiq,_dma_map_area)
++# define dmac_unmap_area __glue(fiq,_dma_unmap_area)
++#endif
+
+ /*
+ * These are private to the dma-mapping API. Do not use directly.
--- /dev/null
+1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog
+ since the CNS3xxx SOCs have ARM11 MPcore CPU.
+2. Enable mpcore_watchdog option as module to default configuration at
+ arch/arm/configs/cns3420vb_defconfig.
+
+Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com>
+
+---
+arch/arm/Kconfig | 1 +
+ arch/arm/configs/cns3420vb_defconfig | 2 ++
+ arch/arm/mach-cns3xxx/cns3420vb.c | 22 ++++++++++++++++++++++
+ 3 files changed, 25 insertions(+), 0 deletions(-)
+
+--- a/arch/arm/configs/cns3420vb_defconfig
++++ b/arch/arm/configs/cns3420vb_defconfig
+@@ -56,6 +56,8 @@ CONFIG_LEGACY_PTY_COUNT=16
+ # CONFIG_HW_RANDOM is not set
+ # CONFIG_HWMON is not set
+ # CONFIG_VGA_CONSOLE is not set
++CONFIG_WATCHDOG=y
++CONFIG_MPCORE_WATCHDOG=m
+ # CONFIG_HID_SUPPORT is not set
+ # CONFIG_USB_SUPPORT is not set
+ CONFIG_MMC=y
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -206,10 +206,32 @@ static struct platform_device cns3xxx_us
+ },
+ };
+
++/* Watchdog */
++static struct resource cns3xxx_watchdog_resources[] = {
++ [0] = {
++ .start = CNS3XXX_TC11MP_TWD_BASE,
++ .end = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_LOCALWDOG,
++ .end = IRQ_LOCALWDOG,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device cns3xxx_watchdog_device = {
++ .name = "mpcore_wdt",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(cns3xxx_watchdog_resources),
++ .resource = cns3xxx_watchdog_resources,
++};
++
+ /*
+ * Initialization
+ */
+ static struct platform_device *cns3420_pdevs[] __initdata = {
++ &cns3xxx_watchdog_device,
+ &cns3420_nor_pdev,
+ &cns3xxx_usb_ehci_device,
+ &cns3xxx_usb_ohci_device,
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -5,3 +5,5 @@ cns3xxx-y += core.o pm.o
+ cns3xxx-$(CONFIG_ATAGS) += devices.o
+ cns3xxx-$(CONFIG_PCI) += pcie.o
+ cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
++cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
++cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -2,6 +2,9 @@ menuconfig ARCH_CNS3XXX
+ bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
+ select ARM_GIC
+ select PCI_DOMAINS if PCI
++ select HAVE_ARM_SCU if SMP
++ select HAVE_ARM_TWD
++ select HAVE_SMP
+ help
+ Support for Cavium Networks CNS3XXX platform.
+
+--- a/arch/arm/mach-cns3xxx/core.h
++++ b/arch/arm/mach-cns3xxx/core.h
+@@ -13,6 +13,7 @@
+
+ #include <linux/reboot.h>
+
++extern struct smp_operations cns3xxx_smp_ops;
+ extern void cns3xxx_timer_init(void);
+
+ #ifdef CONFIG_CACHE_L2X0
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -281,8 +281,6 @@ void __init cns3xxx_pcie_init_late(void)
+ "imprecise external abort");
+
+ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+ cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+ cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+ private_data = &cns3xxx_pcie[i];
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/laguna.c
++++ b/arch/arm/mach-cns3xxx/laguna.c
+@@ -849,7 +849,6 @@ static struct map_desc laguna_io_desc[]
+ static void __init laguna_map_io(void)
+ {
+ cns3xxx_map_io();
+- cns3xxx_pcie_iotable_init();
+ iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
+ laguna_early_serial_setup();
+ }
+@@ -873,15 +872,6 @@ static int laguna_register_gpio(struct g
+ return ret;
+ }
+
+-static int __init laguna_pcie_init(void)
+-{
+- if (!machine_is_gw2388())
+- return 0;
+-
+- return cns3xxx_pcie_init();
+-}
+-subsys_initcall(laguna_pcie_init);
+-
+ static int __init laguna_model_setup(void)
+ {
+ u32 __iomem *mem;
+@@ -1077,5 +1067,6 @@ MACHINE_START(GW2388, "Gateworks Corpora
+ .init_irq = cns3xxx_init_irq,
+ .init_time = cns3xxx_timer_init,
+ .init_machine = laguna_init,
++ .init_late = cns3xxx_pcie_init_late,
+ .restart = cns3xxx_restart,
+ MACHINE_END
--- /dev/null
+--- a/drivers/pci/pci.c
++++ b/drivers/pci/pci.c
+@@ -4772,7 +4772,10 @@ int pci_get_new_domain_nr(void)
+ void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
+ {
+ static int use_dt_domains = -1;
+- int domain = of_get_pci_domain_nr(parent->of_node);
++ int domain = -1;
++
++ if (parent && parent->of_node)
++ domain = of_get_pci_domain_nr(parent->of_node);
+
+ /*
+ * Check DT domain and use_dt_domains values.
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -5,6 +5,7 @@ menuconfig ARCH_CNS3XXX
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD
+ select HAVE_SMP
++ select FIQ
+ help
+ Support for Cavium Networks CNS3XXX platform.
+
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -5,5 +5,5 @@ cns3xxx-y += core.o pm.o
+ cns3xxx-$(CONFIG_ATAGS) += devices.o
+ cns3xxx-$(CONFIG_PCI) += pcie.o
+ cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
+-cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
++cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
+ cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+--- a/arch/arm/mach-cns3xxx/cns3xxx.h
++++ b/arch/arm/mach-cns3xxx/cns3xxx.h
+@@ -267,6 +267,7 @@
+ #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
+ #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
+
++#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4)
+ /*
+ * Power management and clock control
+ */
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -849,7 +849,7 @@ config VDSO
+
+ config DMA_CACHE_RWFO
+ bool "Enable read/write for ownership DMA cache maintenance"
+- depends on CPU_V6K && SMP
++ depends on CPU_V6K && SMP && !ARCH_CNS3XXX
+ default y
+ help
+ The Snoop Control Unit on ARM11MPCore does not detect the
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -17,6 +17,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/usb/ehci_pdriver.h>
+ #include <linux/usb/ohci_pdriver.h>
++#include <asm/smp_twd.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+ #include <asm/mach/time.h>
+@@ -26,6 +27,8 @@
+ #include "core.h"
+ #include "pm.h"
+
++#define IRQ_LOCALTIMER 29
++
+ static struct map_desc cns3xxx_io_desc[] __initdata = {
+ {
+ .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
+@@ -198,6 +201,15 @@ static struct irqaction cns3xxx_timer_ir
+ .handler = cns3xxx_timer_interrupt,
+ };
+
++static void __init cns3xxx_init_twd(void)
++{
++ static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer,
++ CNS3XXX_TC11MP_TWD_BASE,
++ IRQ_LOCALTIMER);
++
++ twd_local_timer_register(&cns3xx_twd_local_timer);
++}
++
+ /*
+ * Set up the clock source and clock events devices
+ */
+@@ -251,6 +263,7 @@ static void __init __cns3xxx_timer_init(
+ setup_irq(timer_irq, &cns3xxx_timer_irq);
+
+ cns3xxx_clockevents_init(timer_irq);
++ cns3xxx_init_twd();
+ }
+
+ void __init cns3xxx_timer_init(void)
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -81,6 +81,16 @@ static struct map_desc cns3xxx_io_desc[]
+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
+ .length = SZ_16M,
+ .type = MT_DEVICE,
++ }, {
++ .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT,
++ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE),
++ .length = SZ_16M,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT,
++ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
++ .length = SZ_16M,
++ .type = MT_DEVICE,
+ #endif
+ },
+ };
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -86,6 +86,79 @@ static void __iomem *cns3xxx_pci_map_bus
+ return base + (where & 0xffc) + (devfn << 12);
+ }
+
++static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where)
++{
++ struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
++
++ /* check PCI-compatible status register after access */
++ if (cnspci->linked) {
++ void __iomem *host_base;
++ u32 sreg, ereg;
++
++ host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
++ sreg = __raw_readw(host_base + 0x6) & 0xF900;
++ ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
++
++ if (sreg | ereg) {
++ /* SREG:
++ * BIT15 - Detected Parity Error
++ * BIT14 - Signaled System Error
++ * BIT13 - Received Master Abort
++ * BIT12 - Received Target Abort
++ * BIT11 - Signaled Target Abort
++ * BIT08 - Master Data Parity Error
++ *
++ * EREG:
++ * BIT20 - Unsupported Request
++ * BIT19 - ECRC
++ * BIT18 - Malformed TLP
++ * BIT17 - Receiver Overflow
++ * BIT16 - Unexpected Completion
++ * BIT15 - Completer Abort
++ * BIT14 - Completion Timeout
++ * BIT13 - Flow Control Protocol Error
++ * BIT12 - Poisoned TLP
++ * BIT04 - Data Link Protocol Error
++ *
++ * TODO: see Documentation/pci-error-recovery.txt
++ * implement error_detected handler
++ */
++/*
++ printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg);
++ if (sreg & BIT(15)) printk(" <PERR");
++ if (sreg & BIT(14)) printk(" >SERR");
++ if (sreg & BIT(13)) printk(" <MABRT");
++ if (sreg & BIT(12)) printk(" <TABRT");
++ if (sreg & BIT(11)) printk(" >TABRT");
++ if (sreg & BIT( 8)) printk(" MPERR");
++
++ if (ereg & BIT(20)) printk(" Unsup");
++ if (ereg & BIT(19)) printk(" ECRC");
++ if (ereg & BIT(18)) printk(" MTLP");
++ if (ereg & BIT(17)) printk(" OFLOW");
++ if (ereg & BIT(16)) printk(" Unex");
++ if (ereg & BIT(15)) printk(" ABRT");
++ if (ereg & BIT(14)) printk(" COMPTO");
++ if (ereg & BIT(13)) printk(" FLOW");
++ if (ereg & BIT(12)) printk(" PTLP");
++ if (ereg & BIT( 4)) printk(" DLINK");
++ printk("\n");
++*/
++ pr_debug("%s failed port%d sreg=0x%04x\n", __func__,
++ pci_domain_nr(bus), sreg);
++
++ /* make sure the status bits are reset */
++ __raw_writew(sreg, host_base + 6);
++ __raw_writel(ereg, host_base + 0x104);
++ return 1;
++ }
++ }
++ else
++ return 1;
++
++ return 0;
++}
++
+ static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+ {
+@@ -95,6 +168,11 @@ static int cns3xxx_pci_read_config(struc
+
+ ret = pci_generic_config_read32(bus, devfn, where, size, val);
+
++ if (check_master_abort(bus, devfn, where)) {
++ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
++ return PCIBIOS_DEVICE_NOT_FOUND;
++ }
++
+ if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
+ (where & 0xffc) == PCI_CLASS_REVISION)
+ /*
+@@ -257,8 +335,14 @@ static void __init cns3xxx_pcie_hw_init(
+ static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
+ struct pt_regs *regs)
+ {
++#if 0
++/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE
++ * ignore imprecise aborts and use PCI-compatible Status register to
++ * determine errors instead
++ */
+ if (fsr & (1 << 10))
+ regs->ARM_pc += 4;
++#endif
+ return 0;
+ }
+
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -366,6 +366,8 @@ void __init cns3xxx_pcie_init_late(void)
+
+ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+ cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
++ if (!cns3xxx_pcie[i].linked)
++ continue;
+ cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+ private_data = &cns3xxx_pcie[i];
+ pci_common_init(&hw_pci);
--- /dev/null
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -440,6 +440,18 @@ config I2C_CBUS_GPIO
+ This driver can also be built as a module. If so, the module
+ will be called i2c-cbus-gpio.
+
++config I2C_CNS3XXX
++ tristate "Cavium CNS3xxx I2C driver"
++ depends on ARCH_CNS3XXX
++ help
++ Support for Cavium CNS3xxx I2C controller driver.
++
++ This driver can also be built as a module. If so, the module
++ will be called i2c-cns3xxx.
++
++ Please note that this driver might be needed to bring up other
++ devices such as Cavium CNS3xxx Ethernet.
++
+ config I2C_CPM
+ tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)"
+ depends on CPM1 || CPM2
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -111,6 +111,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-vipe
+ obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o
+ obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o
+ obj-$(CONFIG_I2C_BRCMSTB) += i2c-brcmstb.o
++obj-$(CONFIG_I2C_CNS3XXX) += i2c-cns3xxx.o
+ obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o
+ obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
+ obj-$(CONFIG_I2C_OPAL) += i2c-opal.o
--- /dev/null
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -183,6 +183,13 @@ config SPI_CLPS711X
+ This enables dedicated general purpose SPI/Microwire1-compatible
+ master mode interface (SSI1) for CLPS711X-based CPUs.
+
++config SPI_CNS3XXX
++ tristate "CNS3XXX SPI controller"
++ depends on ARCH_CNS3XXX && SPI_MASTER
++ select SPI_BITBANG
++ help
++ This enables using the CNS3XXX SPI controller in master mode.
++
+ config SPI_COLDFIRE_QSPI
+ tristate "Freescale Coldfire QSPI controller"
+ depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -26,6 +26,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi-bitban
+ obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
+ obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o
+ obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
++obj-$(CONFIG_SPI_CNS3XXX) += spi-cns3xxx.o
+ obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
+ obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
+ obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -698,6 +698,10 @@ struct spi_transfer {
+ u32 speed_hz;
+
+ struct list_head transfer_list;
++
++#ifdef CONFIG_ARCH_CNS3XXX
++ unsigned last_in_message_list;
++#endif
+ };
+
+ /**
+--- a/drivers/spi/spi.c
++++ b/drivers/spi/spi.c
+@@ -933,6 +933,9 @@ static int spi_transfer_one_message(stru
+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
+ trace_spi_transfer_start(msg, xfer);
+
++ xfer->last_in_message_list =
++ list_is_last(&xfer->transfer_list, &msg->transfers);
++
+ spi_statistics_add_transfer_stats(statm, xfer, master);
+ spi_statistics_add_transfer_stats(stats, xfer, master);
+
--- /dev/null
+--- a/drivers/ata/ahci_platform.c
++++ b/drivers/ata/ahci_platform.c
+@@ -37,12 +37,23 @@ static struct scsi_host_template ahci_pl
+ AHCI_SHT(DRV_NAME),
+ };
+
++static const struct ata_port_info cns3xxx_port_info = {
++ .flags = AHCI_FLAG_COMMON,
++ .pio_mask = ATA_PIO4,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &ahci_pmp_retry_srst_ops,
++};
++
+ static int ahci_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
+ struct ahci_host_priv *hpriv;
++ const struct ata_port_info *info = &ahci_port_info;
+ int rc;
+
++ if (IS_ENABLED(CONFIG_ARCH_CNS3XXX))
++ info = &cns3xxx_port_info;
++
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -138,6 +138,7 @@ static int cns3xxx_set_oneshot(struct cl
+
+ /* period set, and timer enabled in 'next_event' hook */
+ ctrl |= (1 << 2) | (1 << 9);
++ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
+ writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+ return 0;
+ }
+@@ -148,7 +149,7 @@ static int cns3xxx_set_periodic(struct c
+ int pclk = cns3xxx_cpu_clock() / 8;
+ int reload;
+
+- reload = pclk * 20 / (3 * HZ) * 0x25000;
++ reload = pclk * 1000000 / HZ;
+ writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
+ ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
+ writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+@@ -175,7 +176,7 @@ static struct clock_event_device cns3xxx
+ .set_state_oneshot = cns3xxx_set_oneshot,
+ .tick_resume = cns3xxx_shutdown,
+ .set_next_event = cns3xxx_timer_set_next_event,
+- .rating = 350,
++ .rating = 300,
+ .cpumask = cpu_all_mask,
+ };
+
+@@ -220,6 +221,32 @@ static void __init cns3xxx_init_twd(void
+ twd_local_timer_register(&cns3xx_twd_local_timer);
+ }
+
++static cycle_t cns3xxx_get_cycles(struct clocksource *cs)
++{
++ u64 val;
++
++ val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
++ val &= 0xffff;
++
++ return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET));
++}
++
++static struct clocksource clocksource_cns3xxx = {
++ .name = "freerun",
++ .rating = 200,
++ .read = cns3xxx_get_cycles,
++ .mask = CLOCKSOURCE_MASK(48),
++ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
++};
++
++static void __init cns3xxx_clocksource_init(void)
++{
++ /* Reset the FreeRunning counter */
++ writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
++
++ clocksource_register_khz(&clocksource_cns3xxx, 100);
++}
++
+ /*
+ * Set up the clock source and clock events devices
+ */
+@@ -237,13 +264,12 @@ static void __init __cns3xxx_timer_init(
+ /* stop free running timer3 */
+ writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
+
+- /* timer1 */
+- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
+- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
+-
+ writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
+ writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
+
++ val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ;
++ writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
++
+ /* mask irq, non-mask timer1 overflow */
+ irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
+ irq_mask &= ~(1 << 2);
+@@ -255,23 +281,9 @@ static void __init __cns3xxx_timer_init(
+ val |= (1 << 9);
+ writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+
+- /* timer2 */
+- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
+- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
+-
+- /* mask irq */
+- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
+- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
+- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
+-
+- /* down counter */
+- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+- val |= (1 << 10);
+- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+-
+- /* Make irqs happen for the system timer */
+ setup_irq(timer_irq, &cns3xxx_timer_irq);
+
++ cns3xxx_clocksource_init();
+ cns3xxx_clockevents_init(timer_irq);
+ cns3xxx_init_twd();
+ }
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -245,6 +245,10 @@ static void __init cns3420_init(void)
+
+ cns3xxx_ahci_init();
+ cns3xxx_sdhci_init();
++ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
++ NR_IRQS_CNS3XXX);
++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
++ NR_IRQS_CNS3XXX + 32);
+
+ pm_power_off = cns3xxx_power_off;
+ }
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -1,6 +1,8 @@
+ menuconfig ARCH_CNS3XXX
+ bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
+ select ARM_GIC
++ select ARCH_REQUIRE_GPIOLIB
++ select GENERIC_IRQ_CHIP
+ select PCI_DOMAINS if PCI
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -1,7 +1,7 @@
+ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
+ obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
+-cns3xxx-y += core.o pm.o
++cns3xxx-y += core.o pm.o gpio.o
+ cns3xxx-$(CONFIG_ATAGS) += devices.o
+ cns3xxx-$(CONFIG_PCI) += pcie.o
+ cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
+--- a/arch/arm/mach-cns3xxx/cns3xxx.h
++++ b/arch/arm/mach-cns3xxx/cns3xxx.h
+@@ -68,8 +68,10 @@
+ #define SMC_PCELL_ID_3_OFFSET 0xFFC
+
+ #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
++#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000
+
+ #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
++#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000
+
+ #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
+
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[]
+ .pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
++ }, {
++ .virtual = CNS3XXX_GPIOA_BASE_VIRT,
++ .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = CNS3XXX_GPIOB_BASE_VIRT,
++ .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
++ .length = SZ_4K,
++ .type = MT_DEVICE,
+ #ifdef CONFIG_PCI
+ }, {
+ .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -307,13 +307,26 @@ void __init cns3xxx_timer_init(void)
+
+ #ifdef CONFIG_CACHE_L2X0
+
+-void __init cns3xxx_l2x0_init(void)
++static int cns3xxx_l2x0_enable = 1;
++
++static int __init cns3xxx_l2x0_disable(char *s)
++{
++ cns3xxx_l2x0_enable = 0;
++ return 1;
++}
++__setup("nol2x0", cns3xxx_l2x0_disable);
++
++static int __init cns3xxx_l2x0_init(void)
+ {
+- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
++ void __iomem *base;
+ u32 val;
+
++ if (!cns3xxx_l2x0_enable)
++ return 0;
++
++ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
+ if (WARN_ON(!base))
+- return;
++ return 0;
+
+ /*
+ * Tag RAM Control register
+@@ -343,7 +356,10 @@ void __init cns3xxx_l2x0_init(void)
+
+ /* 32 KiB, 8-way, parity disable */
+ l2x0_init(base, 0x00500000, 0xfe0f0fff);
++
++ return 0;
+ }
++arch_initcall(cns3xxx_l2x0_init);
+
+ #endif /* CONFIG_CACHE_L2X0 */
+
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -239,8 +239,6 @@ static struct platform_device *cns3420_p
+
+ static void __init cns3420_init(void)
+ {
+- cns3xxx_l2x0_init();
+-
+ platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
+
+ cns3xxx_ahci_init();
+--- a/arch/arm/mach-cns3xxx/core.h
++++ b/arch/arm/mach-cns3xxx/core.h
+@@ -16,12 +16,6 @@
+ extern struct smp_operations cns3xxx_smp_ops;
+ extern void cns3xxx_timer_init(void);
+
+-#ifdef CONFIG_CACHE_L2X0
+-void __init cns3xxx_l2x0_init(void);
+-#else
+-static inline void cns3xxx_l2x0_init(void) {}
+-#endif /* CONFIG_CACHE_L2X0 */
+-
+ #ifdef CONFIG_PCI
+ extern void __init cns3xxx_pcie_init_late(void);
+ #else
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -22,4 +22,12 @@ config MACH_CNS3420VB
+ This is a platform with an on-board ARM11 MPCore and has support
+ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
+
++config MACH_GW2388
++ bool "Support for Gateworks Laguna Platform"
++ help
++ Include support for the Gateworks Laguna Platform
++
++ This is a platform with an on-board ARM11 MPCore and has support
++ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
++
+ endif
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -7,3 +7,5 @@ cns3xxx-$(CONFIG_PCI) += pcie.o
+ cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
+ cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
+ cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
++cns3xxx-$(CONFIG_MACH_GW2388) += laguna.o
++
+--- a/arch/arm/mach-cns3xxx/devices.c
++++ b/arch/arm/mach-cns3xxx/devices.c
+@@ -16,6 +16,7 @@
+ #include <linux/compiler.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/platform_device.h>
++#include <asm/mach-types.h>
+ #include "cns3xxx.h"
+ #include "pm.h"
+ #include "core.h"
+@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void)
+ u32 gpioa_pins = __raw_readl(gpioa);
+
+ /* MMC/SD pins share with GPIOA */
+- gpioa_pins |= 0x1fff0004;
++ if (machine_is_gw2388()) {
++ gpioa_pins |= 0x1fff0000;
++ } else {
++ gpioa_pins |= 0x1fff0004;
++ }
+ __raw_writel(gpioa_pins, gpioa);
+
+ cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
--- /dev/null
+--- a/drivers/mmc/host/sdhci-cns3xxx.c
++++ b/drivers/mmc/host/sdhci-cns3xxx.c
+@@ -88,9 +88,9 @@ static const struct sdhci_pltfm_data sdh
+ .ops = &sdhci_cns3xxx_ops,
+ .quirks = SDHCI_QUIRK_BROKEN_DMA |
+ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
+- SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+- SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
++ SDHCI_QUIRK_BROKEN_CARD_DETECTION,
+ };
+
+ static int sdhci_cns3xxx_probe(struct platform_device *pdev)
--- /dev/null
+--- a/arch/arm/mach-cns3xxx/laguna.c
++++ b/arch/arm/mach-cns3xxx/laguna.c
+@@ -21,6 +21,7 @@
+ #include <linux/kernel.h>
+ #include <linux/compiler.h>
+ #include <linux/io.h>
++#include <linux/irq.h>
+ #include <linux/gpio.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/serial_core.h>
+@@ -872,6 +873,47 @@ static int laguna_register_gpio(struct g
+ return ret;
+ }
+
++/* allow disabling of external isolated PCIe IRQs */
++static int cns3xxx_pciextirq = 1;
++static int __init cns3xxx_pciextirq_disable(char *s)
++{
++ cns3xxx_pciextirq = 0;
++ return 1;
++}
++__setup("noextirq", cns3xxx_pciextirq_disable);
++
++static int __init laguna_pcie_init_irq(void)
++{
++ u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
++ u32 reg = (__raw_readl(mem) >> 26) & 0xf;
++ int irqs[] = {
++ IRQ_CNS3XXX_EXTERNAL_PIN0,
++ IRQ_CNS3XXX_EXTERNAL_PIN1,
++ IRQ_CNS3XXX_EXTERNAL_PIN2,
++ 154,
++ };
++
++ if (!machine_is_gw2388())
++ return 0;
++
++ /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
++ if (cns3xxx_pciextirq && reg != 1)
++ cns3xxx_pciextirq = 0;
++
++ if (cns3xxx_pciextirq) {
++ printk("laguna: using isolated PCI interrupts:"
++ " irq%d/irq%d/irq%d/irq%d\n",
++ irqs[0], irqs[1], irqs[2], irqs[3]);
++ cns3xxx_pcie_set_irqs(0, irqs);
++ } else {
++ printk("laguna: using shared PCI interrupts: irq%d\n",
++ IRQ_CNS3XXX_PCIE0_DEVICE);
++ }
++
++ return 0;
++}
++subsys_initcall(laguna_pcie_init_irq);
++
+ static int __init laguna_model_setup(void)
+ {
+ u32 __iomem *mem;
+@@ -883,8 +925,33 @@ static int __init laguna_model_setup(voi
+ printk("Running on Gateworks Laguna %s\n", laguna_info.model);
+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
+ NR_IRQS_CNS3XXX);
+- cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
+- NR_IRQS_CNS3XXX + 32);
++
++ /*
++ * If pcie external interrupts are supported and desired
++ * configure IRQ types and configure pin function.
++ * Note that cns3xxx_pciextirq is enabled by default, but can be
++ * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
++ * the baseboard model does not support this hardware feature.
++ */
++ if (cns3xxx_pciextirq) {
++ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
++ reg = __raw_readl(mem);
++ /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
++ reg &= ~0x3c000000;
++ reg |= 0x38000000;
++ __raw_writel(reg, mem);
++
++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
++ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
++
++ irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
++ irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
++ irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
++ irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
++ } else {
++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
++ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
++ }
+
+ if (strncmp(laguna_info.model, "GW", 2) == 0) {
+ if (laguna_info.config_bitmap & ETH0_LOAD)
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -18,6 +18,7 @@
+ #include <linux/io.h>
+ #include <linux/ioport.h>
+ #include <linux/interrupt.h>
++#include <linux/irq.h>
+ #include <linux/ptrace.h>
+ #include <asm/mach/map.h>
+ #include "cns3xxx.h"
+@@ -27,7 +28,7 @@ struct cns3xxx_pcie {
+ void __iomem *host_regs; /* PCI config registers for host bridge */
+ void __iomem *cfg0_regs; /* PCI Type 0 config registers */
+ void __iomem *cfg1_regs; /* PCI Type 1 config registers */
+- unsigned int irqs[2];
++ unsigned int irqs[5];
+ struct resource res_io;
+ struct resource res_mem;
+ int port;
+@@ -95,7 +96,7 @@ static inline int check_master_abort(str
+ void __iomem *host_base;
+ u32 sreg, ereg;
+
+- host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
++ host_base = (void __iomem *) cnspci->host_regs;
+ sreg = __raw_readw(host_base + 0x6) & 0xF900;
+ ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
+
+@@ -209,7 +210,7 @@ static struct pci_ops cns3xxx_pcie_ops =
+ static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ {
+ struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
+- int irq = cnspci->irqs[!!dev->bus->number];
++ int irq = cnspci->irqs[!!dev->bus->number + pin - 1];
+
+ pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
+ pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
+@@ -235,7 +236,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
+ .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
+ .flags = IORESOURCE_MEM,
+ },
+- .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
++ .irqs = {
++ IRQ_CNS3XXX_PCIE0_RC,
++ IRQ_CNS3XXX_PCIE0_DEVICE,
++ IRQ_CNS3XXX_PCIE0_DEVICE,
++ IRQ_CNS3XXX_PCIE0_DEVICE,
++ IRQ_CNS3XXX_PCIE0_DEVICE,
++ },
+ .port = 0,
+ },
+ [1] = {
+@@ -254,7 +261,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
+ .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
+ .flags = IORESOURCE_MEM,
+ },
+- .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
++ .irqs = {
++ IRQ_CNS3XXX_PCIE1_RC,
++ IRQ_CNS3XXX_PCIE1_DEVICE,
++ IRQ_CNS3XXX_PCIE1_DEVICE,
++ IRQ_CNS3XXX_PCIE1_DEVICE,
++ IRQ_CNS3XXX_PCIE1_DEVICE,
++ },
+ .port = 1,
+ },
+ };
+@@ -346,6 +359,14 @@ static int cns3xxx_pcie_abort_handler(un
+ return 0;
+ }
+
++void __init cns3xxx_pcie_set_irqs(int bus, int *irqs)
++{
++ int i;
++
++ for (i = 0; i < 4; i++)
++ cns3xxx_pcie[bus].irqs[i + 1] = irqs[i];
++}
++
+ void __init cns3xxx_pcie_init_late(void)
+ {
+ int i;
+--- a/arch/arm/mach-cns3xxx/core.h
++++ b/arch/arm/mach-cns3xxx/core.h
+@@ -18,8 +18,10 @@ extern void cns3xxx_timer_init(void);
+
+ #ifdef CONFIG_PCI
+ extern void __init cns3xxx_pcie_init_late(void);
++extern void __init cns3xxx_pcie_set_irqs(int bus, int *irqs);
+ #else
+ static inline void __init cns3xxx_pcie_init_late(void) {}
++static inline void cns3xxx_pcie_set_irqs(int bus, int *irqs) {}
+ #endif
+
+ void __init cns3xxx_map_io(void);
--- /dev/null
+--- a/drivers/net/phy/broadcom.c
++++ b/drivers/net/phy/broadcom.c
+@@ -332,6 +332,11 @@ static int bcm5481_config_aneg(struct ph
+ /* Write bits 14:0. */
+ reg |= (1 << 15);
+ phy_write(phydev, 0x18, reg);
++ } else {
++ phy_write(phydev, 0x18, 0xf1e7);
++ phy_write(phydev, 0x1c, 0x8e00);
++
++ phy_write(phydev, 0x1c, 0xa41f);
+ }
+
+ return ret;
--- /dev/null
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
+@@ -144,6 +144,34 @@ static int __dwc2_lowlevel_hw_enable(str
+ return ret;
+ }
+
++static const struct dwc2_core_params params_cns3xxx = {
++ .otg_cap = 2, /* non-HNP/non-SRP capable */
++ .otg_ver = 0, /* 1.3 */
++ .dma_enable = 1,
++ .dma_desc_enable = 0,
++ .speed = 0, /* High Speed */
++ .enable_dynamic_fifo = 1,
++ .en_multiple_tx_fifo = 1,
++ .host_rx_fifo_size = 658, /* 774 DWORDs */
++ .host_nperio_tx_fifo_size = 128, /* 256 DWORDs */
++ .host_perio_tx_fifo_size = 658, /* 512 DWORDs */
++ .max_transfer_size = 65535,
++ .max_packet_count = 511,
++ .host_channels = 16,
++ .phy_type = 1, /* UTMI */
++ .phy_utmi_width = 16, /* 8 bits */
++ .phy_ulpi_ddr = 0, /* Single */
++ .phy_ulpi_ext_vbus = 0,
++ .i2c_enable = 0,
++ .ulpi_fs_ls = 0,
++ .host_support_fs_ls_low_power = 0,
++ .host_ls_low_power_phy_clk = 0, /* 48 MHz */
++ .ts_dline = 0,
++ .reload_ctl = 0,
++ .ahbcfg = 0x10,
++ .uframe_sched = 0,
++};
++
+ /**
+ * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
+ * @hsotg: The driver state
+@@ -344,6 +372,9 @@ static int dwc2_driver_probe(struct plat
+ /* Default all params to autodetect */
+ dwc2_set_all_params(&defparams, -1);
+ params = &defparams;
++#ifdef CONFIG_ARCH_CNS3XXX
++ params = ¶ms_cns3xxx;
++#endif
+
+ /*
+ * Disable descriptor dma mode by default as the HW can support
projects / openwrt / staging / dangole.git / commitdiff