Update make target for ARM supported boards.
authorWolfgang Denk <wd@pollux.denx.de>
Thu, 6 Oct 2005 15:08:18 +0000 (17:08 +0200)
committerWolfgang Denk <wd@pollux.denx.de>
Thu, 6 Oct 2005 15:08:18 +0000 (17:08 +0200)
Use lowlevel_init() instead of platformsetup() [rename].
Patch by Peter Pearse, 06 Oct 2005

54 files changed:
CHANGELOG
MAINTAINERS
MAKEALL
Makefile
board/integratorap/Makefile
board/integratorap/integratorap.c
board/integratorap/lowlevel_init.S [new file with mode: 0644]
board/integratorap/platform.S [deleted file]
board/integratorap/split_by_variant.sh [new file with mode: 0644]
board/integratorap/u-boot.lds [deleted file]
board/integratorap/u-boot.lds.S [new file with mode: 0644]
board/integratorcp/Makefile
board/integratorcp/lowlevel_init.S [new file with mode: 0644]
board/integratorcp/platform.S [deleted file]
board/integratorcp/split_by_variant.sh [new file with mode: 0644]
board/integratorcp/u-boot.lds [deleted file]
board/integratorcp/u-boot.lds.S [new file with mode: 0644]
board/ns9750dev/Makefile
board/ns9750dev/lowlevel_init.S [new file with mode: 0644]
board/ns9750dev/platform.S [deleted file]
board/omap1510inn/Makefile
board/omap1510inn/lowlevel_init.S [new file with mode: 0644]
board/omap1510inn/platform.S [deleted file]
board/omap1610inn/Makefile
board/omap1610inn/lowlevel_init.S [new file with mode: 0644]
board/omap1610inn/platform.S [deleted file]
board/omap2420h4/Makefile
board/omap2420h4/lowlevel_init.S [new file with mode: 0644]
board/omap2420h4/platform.S [deleted file]
board/omap5912osk/Makefile
board/omap5912osk/lowlevel_init.S [new file with mode: 0644]
board/omap5912osk/platform.S [deleted file]
board/omap730p2/Makefile
board/omap730p2/lowlevel_init.S [new file with mode: 0644]
board/omap730p2/platform.S [deleted file]
board/sx1/Makefile
board/sx1/lowlevel_init.S [new file with mode: 0644]
board/sx1/platform.S [deleted file]
board/versatile/Makefile
board/versatile/lowlevel_init.S [new file with mode: 0644]
board/versatile/platform.S [deleted file]
board/versatile/split_by_variant.sh [new file with mode: 0644]
board/voiceblue/setup.S
cpu/arm1136/interrupts.c
cpu/arm1136/start.S
cpu/arm720t/cpu.c
cpu/arm720t/interrupts.c
cpu/arm720t/start.S
cpu/arm920t/start.S
cpu/arm925t/start.S
cpu/arm926ejs/start.S
cpu/arm946es/start.S
doc/README-integrator
include/asm-arm/arch-arm720t/hardware.h

index 802f5d30e6b632110e6b0a0fb7438a509d452c81..ce0a51f1e18877d64e33cce6e8e7ae8f49dd49cb 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,10 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Update make target for ARM supported boards.
+  Use lowlevel_init() instead of platformsetup() [rename].
+  Patch by Peter Pearse, 06 Oct 2005
+
 * Fix booting from serial dataflash on AT91RM9200
   Patch by Peter Menzebach, 29 Aug 2005
 
index d251cd8e5204cefb2935e213c1aeb0092f22833b..a9d433d8b8bad2cd8536f54ceafa927ed4153dfe 100644 (file)
@@ -249,11 +249,13 @@ Frank Panno <fpanno@delphintech.com>
        ep8260                  MPC8260
 
 Peter Pearse <peter.pearse@arm.com>
-
-       Integrator/AP           CM 926EJ-S, CM7x0T, CM9x0T
-       Integrator/CP           CM 926EJ-S  CM920T, CM940T, CM922T-XA10
-       Versatile/AB            ARM926EJ-S
-       Versatile/PB            ARM926EJ-S
+       integratorcp            All current ARM supplied &
+                               supported core modules
+                               - see http://www.arm.com
+                               /products/DevTools
+                               /Hardware_Platforms.html
+       versatile               ARM926EJ-S
+       versatile               ARM926EJ-S
 
 Denis Peter <d.peter@mpl.ch>
 
diff --git a/MAKEALL b/MAKEALL
index 7235b70e80e18816f63045b5514b3f6441e6e68e..0472cfb1a495f355393d8d7bfbbb7700dd9a6cfb 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -162,7 +162,7 @@ LIST_SA="assabet dnp1110 gcplus lart shannon"
 
 LIST_ARM7="    \
        armadillo       B2              ep7312          evb4510         \
-       impa7           integratorap_CM720T     integratorap_CM7TDMI    \
+       impa7           integratorap    ap7             ap720t          \
        modnet50                                                        \
 "
 
@@ -171,32 +171,28 @@ LIST_ARM7="       \
 #########################################################################
 
 LIST_ARM9="    \
-       at91rm9200dk    cmc_pu2         csb637                          \
-       integratorap_CM920T             integratorap_CM920T_ETM         \
-       integratorap_CM922T_XA10        integratorap_CM926EJ_S          \
-       integratorap_CM940T             integratorap_CM946E_S           \
-       integratorap_CM966E_S           integratorcp_CM920T             \
-       integratorcp_CM920T_ETM         integratorcp_CM922T_XA10        \
-       integratorcp_CM926EJ_S          integratorcp_CM940T             \
-       integratorcp_CM946E_S           integratorcp_CM966E_S           \
-       kb9202          lpd7a400        mp2usb          mx1ads          \
-       mx1fs2          omap1510inn     omap1610h2      omap1610inn     \
-       omap730p2       scb9328         smdk2400        smdk2410        \
-       trab            VCMA9           versatile       voiceblue       \
+       at91rm9200dk    cmc_pu2                                         \
+       ap920t          ap922_XA10      ap926ejs        ap946es         \
+       ap966           cp920t          cp922_XA10      cp926ejs        \
+       cp946es         cp966           lpd7a400        mp2usb          \
+       mx1ads          mx1fs2          omap1510inn     omap1610h2      \
+       omap1610inn     omap730p2       scb9328         smdk2400        \
+       smdk2410        trab            VCMA9           versatile       \
+       versatileab     versatilepb     voiceblue
 "
 
 #########################################################################
 ## ARM10 Systems
 #########################################################################
 LIST_ARM10="   \
-       integratorcp_CM10220E           integratorcp_CM1026EJ_S         \
+       integratorcp    cp1026                                          \
 "
 
 #########################################################################
 ## ARM11 Systems
 #########################################################################
 LIST_ARM11="   \
-       integratorcp_CM1136JF_S         omap2420h4                      \
+       cp1136          omap2420h4                                      \
 "
 
 #########################################################################
index c41e8f54df8caaa436ef3e86d0e0b077e16f7e83..023bcb5d15f68f517e8ccc8ba73b92728f44e56f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1396,178 +1396,34 @@ csb637_config  :       unconfig
 mp2usb_config  :       unconfig
        @./mkconfig $(@:_config=) arm arm920t mp2usb NULL at91rm9200
 
-########################################################################
-## ARM Integrator boards
-## There are two variants /AP && /CP
-## - many different core modules (CMs) can be used
-## - some share characteristics
-## Those without specific cpu support can still use U-Boot
-## provided the ARM boot monitor (or similar) runs before U-Boot
-## to set up the platform e.g. map writeable memory to 0x00000000
-## setup MMU, setup caches etc.
-## Ported cores are:-
-##     ARM926EJ-S
-##     ARM946E-S
-##
-########################################################################
-xtract_int_board = $(subst _$(subst integrator$1_,,$(subst _config,,$2)),,$(subst _config,,$2))
-xtract_int_cm    = $(subst integrator$1_,,$(subst _config,,$2))
-#########################################################################
-## Integrator/AP
-#########################################################################
-integratorap_config    :       unconfig
-       @echo -n "/* Integrator configuration implied " >  tmp.fil;     \
-        echo    " by Makefile target   */"             >> tmp.fil;     \
-        echo                                           >> tmp.fil
-       @echo -n "#define CONFIG_INTEGRATOR     1"      >> tmp.fil;     \
-       echo     "      /* Integrator board     */"     >> tmp.fil;     \
-       echo  -n "#define CONFIG_ARCH_INTEGRATOR"       >> tmp.fil;     \
-       echo     "      1       /* Integrator/AP */"    >> tmp.fil;     \
-       echo "/* Core module not defined        */"     >> tmp.fil;     \
-       echo -n "#define CONFIG_ARM_INTCM       1"      >> tmp.fil;     \
-       echo -n "       /* Integrator core module "     >> tmp.fil;     \
-       echo    "with unknown core      */"             >> tmp.fil;     \
-       cpu=arm_intcm;                                                  \
-       mv tmp.fil ./include/config.h;                                  \
-       ubootlds=board/integratorap/u-boot.lds;                         \
-       sed -e 's/cpu\/.*\/st/cpu\/'$$cpu'\/st/'                        \
-                                          $$ubootlds > $$ubootlds.tmp; \
-       mv -f $$ubootlds.tmp $$ubootlds;                                \
-       ./mkconfig -a integratorap arm arm_intcm integratorap;
-
-integratorap_CM720T_config             integratorap_CM7TDMI_config     \
-integratorap_CM920T_config             integratorap_CM920T_ETM_config  \
-integratorap_CM922T_XA10_config                integratorap_CM926EJ_S_config   \
-integratorap_CM940T_config             integratorap_CM946E_S_config    \
-integratorap_CM966E_S_config           integratorap_CM10200E_config    \
-integratorap_CM10220E_config           integratorap_CM1026EJ_S_config  \
-integratorap_CM1136JF_S_config :       unconfig
-       @echo -n "/* Integrator configuration implied " >  tmp.fil;     \
-        echo    " by Makefile target   */"             >> tmp.fil;     \
-        echo                                           >> tmp.fil
-       @echo -n "#define CONFIG_INTEGRATOR     1"      >>  tmp.fil;    \
-       echo     "      /* Integrator board     */"     >> tmp.fil;     \
-       echo  -n "#define CONFIG_ARCH_INTEGRATOR"       >> tmp.fil;     \
-       echo     "      1       /* Integrator/AP */"    >> tmp.fil;     \
-       cm=$(call xtract_int_cm,ap,$@);                                 \
-       echo  -n "#define CONFIG_$$cm           "       >> tmp.fil;     \
-       echo     "      /* core module */"              >> tmp.fil;     \
-       case $$cm in                                                    \
-       CM920T)                                                         \
-                       echo -n "#define CONFIG_ARM920" >> tmp.fil;     \
-                       echo -n "T      1       /* CPU" >> tmp.fil;     \
-                       echo -n " core is ARM920T"      >> tmp.fil;     \
-                       echo    "       */"             >> tmp.fil;     \
-                       cpu=arm920t;;                                   \
-       CM926EJ_S)      echo -n "#define CONFIG_ARM926" >> tmp.fil;     \
-                       echo -n "EJ_S   1       /* CPU" >> tmp.fil;     \
-                       echo -n " core is ARM926EJ-S"   >> tmp.fil;     \
-                       echo    "       */"             >> tmp.fil;     \
-                       cpu=arm926ejs;;                                 \
-       CM946E_S)       echo -n "#define CONFIG_ARM946" >> tmp.fil;     \
-                       echo -n "E_S    1       /* CPU" >> tmp.fil;     \
-                       echo -n " core is ARM946E-S"    >> tmp.fil;     \
-                       echo    "       */"             >> tmp.fil;     \
-                       cpu=arm946es;;                                  \
-       *)              echo -n "#define CONFIG_ARM_IN" >> tmp.fil;     \
-                       echo -n "TCM    1       /* Int" >> tmp.fil;     \
-                       echo -n "egrator core module w" >> tmp.fil;     \
-                       echo -n "ith unported core"     >> tmp.fil;     \
-                       echo    "       */"             >> tmp.fil;     \
-                       cpu=arm_intcm;;                                 \
-       esac;                                                           \
-       mv tmp.fil ./include/config.h;                                  \
-       ubootlds=board/$(call xtract_int_board,ap,$@)/u-boot.lds;       \
-       sed -e 's/cpu\/.*\/st/cpu\/'$$cpu'\/st/'                        \
-                                          $$ubootlds > $$ubootlds.tmp; \
-       mv -f $$ubootlds.tmp $$ubootlds;                                \
-       ./mkconfig -a $(call xtract_int_board,ap,$@) arm $$cpu          \
-                     $(call xtract_int_board,ap,$@);
 
-#########################################################################
-## Integrator/CP
-#########################################################################
-integratorcp_config    :       unconfig
-       @echo -n "/* Integrator configuration implied " >  tmp.fil;     \
-        echo    " by Makefile target   */"             >> tmp.fil;     \
-        echo                                           >> tmp.fil
-       @echo -n "#define CONFIG_INTEGRATOR     1"      >> tmp.fil;     \
-       echo     "      /* Integrator board     */"     >> tmp.fil;     \
-       echo  -n "#define CONFIG_ARCH_CINTEGRATOR"      >> tmp.fil;     \
-       echo     "      1       /* Integrator/CP */"    >> tmp.fil;     \
-       echo     "/* Core module not defined    */"     >> tmp.fil;     \
-       echo -n "#define CONFIG_ARM_INTCM       1"      >> tmp.fil;     \
-       echo -n "       /* Integrator core module "     >> tmp.fil;     \
-       echo    "with unknown core      */"             >> tmp.fil;     \
-       cpu=arm_intcm;                                                  \
-       echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM"       >> tmp.fil;     \
-       echo -n "               /* CM may not have "    >> tmp.fil;     \
-       echo    "multiple SSRAM mapping */"             >> tmp.fil;     \
-       echo -n "#undef CONFIG_CM_SPD_DETECT    "       >> tmp.fil;     \
-       echo -n "       /* CM may not support SPD "     >> tmp.fil;     \
-       echo    "query */"                              >> tmp.fil;     \
-       echo -n "#undef CONFIG_CM_REMAP         "       >> tmp.fil;     \
-       echo -n "       /* CM may not support "         >> tmp.fil;     \
-       echo    "remapping      */"                     >> tmp.fil;     \
-       echo -n "#undef CONFIG_CM_INIT          "       >> tmp.fil;     \
-       echo -n "       /* CM may not have  "           >> tmp.fil;     \
-       echo    "initialization reg     */"             >> tmp.fil;     \
-       echo -n "#undef CONFIG_CM_TCRAM         "       >> tmp.fil;     \
-       echo -n "       /* CM may not have TCRAM */"    >> tmp.fil;     \
-       mv tmp.fil ./include/config.h;                                  \
-       ubootlds=board/integratorcp/u-boot.lds;                         \
-       sed -e 's/cpu\/.*\/st/cpu\/'$$cpu'\/st/'                        \
-                                          $$ubootlds > $$ubootlds.tmp; \
-       mv -f $$ubootlds.tmp $$ubootlds;                                \
-       ./mkconfig -a integratorcp arm arm_intcm integratorcp;
-
-integratorcp_CM920T_config             integratorcp_CM920T_ETM_config  \
-integratorcp_CM922T_XA10_config                integratorcp_CM926EJ_S_config   \
-integratorcp_CM940T_config             integratorcp_CM946E_S_config    \
-integratorcp_CM966E_S_config           integratorcp_CM10200E_config    \
-integratorcp_CM10220E_config           integratorcp_CM1026EJ_S_config  \
-integratorcp_CM1136JF_S_config :       unconfig
-       @echo -n "/* Integrator configuration implied " >  tmp.fil;     \
-        echo    " by Makefile target   */"             >> tmp.fil;     \
-        echo                                           >> tmp.fil
-       @echo -n "#define CONFIG_INTEGRATOR     1"      >> tmp.fil;     \
-       echo     "      /* Integrator board     */"     >> tmp.fil;     \
-       echo  -n "#define CONFIG_ARCH_CINTEGRATOR"      >> tmp.fil;     \
-       echo     "      1       /* Integrator/CP */"    >> tmp.fil;     \
-       cm=$(call xtract_int_cm,cp,$@);                                 \
-       echo  -n "#define CONFIG_$$cm           "       >> tmp.fil;     \
-       echo     "      /* core module */"              >> tmp.fil;     \
-       echo "/* $$cm core module       */"             >> tmp.fil;     \
-       case $$cm in                                                    \
-       CM920T)         echo -n "#define CONFIG_ARM920" >> tmp.fil;     \
-                       echo -n "T      1       /* CPU" >> tmp.fil;     \
-                       echo -n " core is ARM920T"      >> tmp.fil;     \
-                       echo    "       */"             >> tmp.fil;     \
-                       cpu=arm920t;;                                   \
-       CM946E_S)       echo -n "#define CONFIG_ARM946" >> tmp.fil;     \
-                       echo -n "E_S    1       /* CPU" >> tmp.fil;     \
-                       echo -n " core is ARM946E-S"    >> tmp.fil;     \
-                       echo    "       */"             >> tmp.fil;     \
-                       cpu=arm946es;;                                  \
-       CM926EJ_S)      echo -n "#define CONFIG_ARM926" >> tmp.fil;     \
-                       echo -n "EJ_S   1       /* CPU" >> tmp.fil;     \
-                       echo -n " core is ARM926EJ-S"   >> tmp.fil;     \
-                       echo    "       */"             >> tmp.fil;     \
-                       cpu=arm926ejs;;                                 \
-       *)              echo -n "#define CONFIG_ARM_IN" >> tmp.fil;     \
-                       echo -n "TCM    1       /* Int" >> tmp.fil;     \
-                       echo -n "egrator core module w" >> tmp.fil;     \
-                       echo -n "ith unported core"     >> tmp.fil;     \
-                       echo    "       */"             >> tmp.fil;     \
-                       cpu=arm_intcm;;                                 \
-       esac;                                                           \
-       mv tmp.fil ./include/config.h;                                  \
-       ubootlds=board/$(call xtract_int_board,cp,$@)/u-boot.lds;       \
-       sed -e 's/cpu\/.*\/st/cpu\/'$$cpu'\/st/'                        \
-                                          $$ubootlds > $$ubootlds.tmp; \
-       mv -f $$ubootlds.tmp $$ubootlds;                                \
-       ./mkconfig -a $(call xtract_int_board,cp,$@) arm $$cpu          \
-                     $(call xtract_int_board,cp,$@);
+########################################################################
+## ARM Integrator boards - see doc/README-integrator for more info.
+integratorap_config    \
+ap_config              \
+ap966_config           \
+ap922_config           \
+ap922_XA10_config      \
+ap7_config             \
+ap720t_config                  \
+ap920t_config          \
+ap926ejs_config                \
+ap946es_config: unconfig
+       @chmod a+x board/integratorap/split_by_variant.sh 
+       @board/integratorap/split_by_variant.sh $@ $(CC)
+
+integratorcp_config    \
+cp_config              \
+cp920t_config          \
+cp926ejs_config                \
+cp946es_config         \
+cp1136_config          \
+cp966_config           \
+cp922_config           \
+cp922_XA10_config      \
+cp1026_config: unconfig
+       @chmod a+x board/integratorcp/split_by_variant.sh 
+       @board/integratorcp/split_by_variant.sh $@ $(CC)
 
 kb9202_config  :       unconfig
        @./mkconfig $(@:_config=) arm arm920t kb9202 NULL at91rm9200
@@ -1660,8 +1516,14 @@ trab_old_config: unconfig
 VCMA9_config   :       unconfig
        @./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0
 
-versatile_config :     unconfig
-       @./mkconfig $(@:_config=) arm arm926ejs versatile
+#========================================================================
+# ARM supplied Versatile development boards
+#========================================================================
+versatile_config       \
+versatileab_config     \
+versatilepb_config :   unconfig
+       @chmod a+x board/versatile/split_by_variant.sh 
+       @board/versatile/split_by_variant.sh $@ $(CC)
 
 voiceblue_smallflash_config    \
 voiceblue_config:      unconfig
@@ -1946,6 +1808,7 @@ clean:
        rm -f tools/env/fw_printenv tools/env/fw_setenv
        rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
        rm -f board/trab/trab_fkt board/voiceblue/eeprom
+       rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
 
 clobber:       clean
        find . -type f \( -name .depend \
index cf76dedb2da6e1b43f8bda84786ccc35b9090690..358df62519a52415411f0aa582c1f7362c74354c 100644 (file)
@@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk
 LIB    = lib$(BOARD).a
 
 OBJS   := integratorap.o flash.o
-SOBJS  := platform.o memsetup.o
+SOBJS  := lowlevel_init.o memsetup.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $^
index 4baf39a67780ee69d15b90005f557ea4b33f6932..d4f61d6403d530f7139196c6ee523d367f5cb79d 100644 (file)
@@ -649,8 +649,3 @@ ulong get_tbclk (void)
 {
        return CFG_HZ_CLOCK/div_clock;
 }
-
-/* The Integrator/AP timer1 is clocked at 24MHz
- * can be divided by 16 or 256
- * and is a 16-bit counter
- */
diff --git a/board/integratorap/lowlevel_init.S b/board/integratorap/lowlevel_init.S
new file mode 100644 (file)
index 0000000..1aacbf4
--- /dev/null
@@ -0,0 +1,213 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+       /* Reset using CM control register */
+.global reset_cpu
+reset_cpu:
+       mov     r0, #CM_BASE
+       ldr     r1,[r0,#OS_CTRL]
+       orr     r1,r1,#CMMASK_RESET
+       str     r1,[r0,#OS_CTRL]
+
+reset_failed:
+       b       reset_failed
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+       /* If U-Boot has been run after the ARM boot monitor
+        * then all the necessary actions have been done
+        * otherwise we are running from user flash mapped to 0x00000000
+        * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+        * Changes to the (possibly soft) reset defaults of the processor
+        * itself should be performed in cpu/arm<>/start.S
+        * This function affects only the core module or board settings
+        */
+
+#ifdef CONFIG_CM_INIT
+       /* CM has an initialization register
+        * - bits in it are wired into test-chip pins to force
+        *   reset defaults
+        * - may need to change its contents for U-Boot
+        */
+
+       /* set the desired CM specific value */
+       mov     r2,#CMMASK_LOWVEC       /* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+       orr     r2,r2,#CMMASK_INIT_102
+#else
+
+#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+     !defined (CONFIG_CM940T)
+
+#ifdef CONFIG_CM_MULTIPLE_SSRAM
+       /* set simple mapping             */
+       and     r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
+
+#ifdef CONFIG_CM_TCRAM
+       /* disable TCRAM                  */
+       and     r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM         */
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+           defined (CONFIG_CM1136JF_S)
+
+       and     r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+       orr     r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+       /* read CM_INIT    */
+       mov     r0, #CM_BASE
+       ldr     r1, [r0, #OS_INIT]
+       /* check against desired bit setting */
+       and     r3,r1,r2
+       cmp     r3,r2
+       beq     init_reg_OK
+
+       /* lock for change */
+       mov     r3, #CMVAL_LOCK1
+       add     r3,r3,#CMVAL_LOCK2
+       str     r3, [r0, #OS_LOCK]
+       /* set desired value */
+       orr     r1,r1,r2
+       /* write & relock CM_INIT */
+       str     r1, [r0, #OS_INIT]
+       mov     r1, #CMVAL_UNLOCK
+       str     r1, [r0, #OS_LOCK]
+
+       /* soft reset so new values used */
+       b       reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+       mov     pc, lr
+
+#ifdef CONFIG_CM_SPD_DETECT
+       /* Fast memory is available for the DRAM data
+        * - ensure it has been transferred, then summarize the data
+        *   into a CM register
+        */
+.globl dram_query
+dram_query:
+       stmfd   r13!,{r4-r6,lr}
+       /* set up SDRAM info                              */
+       /* - based on example code from the CM User Guide */
+       mov     r0, #CM_BASE
+
+readspdbit:
+       ldr     r1, [r0, #OS_SDRAM]     /* read the SDRAM register */
+       and     r1, r1, #0x20           /* mask SPD bit (5)        */
+       cmp     r1, #0x20               /* test if set             */
+       bne     readspdbit
+
+setupsdram:
+       add     r0, r0, #OS_SPD         /* address the copy of the SDP data */
+       ldrb    r1, [r0, #3]            /* number of row address lines      */
+       ldrb    r2, [r0, #4]            /* number of column address lines   */
+       ldrb    r3, [r0, #5]            /* number of banks                  */
+       ldrb    r4, [r0, #31]           /* module bank density              */
+       mul     r5, r4, r3              /* size of SDRAM (MB divided by 4)  */
+       mov     r5, r5, ASL#2           /* size in MB                       */
+       mov     r0, #CM_BASE            /* reload for later code            */
+       cmp     r5, #0x10               /* is it 16MB?                      */
+       bne     not16
+       mov     r6, #0x2                /* store size and CAS latency of 2  */
+       b       writesize
+
+not16:
+       cmp     r5, #0x20               /* is it  32MB? */
+       bne     not32
+       mov     r6, #0x6
+       b       writesize
+
+not32:
+       cmp     r5, #0x40               /* is it  64MB? */
+       bne     not64
+       mov     r6, #0xa
+       b       writesize
+
+not64:
+       cmp     r5, #0x80               /* is it 128MB? */
+       bne     not128
+       mov     r6, #0xe
+       b       writesize
+
+not128:
+       /* if it is none of these sizes then it is either 256MB, or
+        * there is no SDRAM fitted so default to 256MB
+        */
+       mov     r6, #0x12
+
+writesize:
+       mov     r1, r1, ASL#8           /* row addr lines from SDRAM reg */
+       orr     r2, r1, r2, ASL#12      /* OR in column address lines    */
+       orr     r3, r2, r3, ASL#16      /* OR in number of banks         */
+       orr     r6, r6, r3              /* OR in size and CAS latency    */
+       str     r6, [r0, #OS_SDRAM]     /* store SDRAM parameters        */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+       ldmfd   r13!,{r4-r6,pc}                 /* back to caller */
+
+#ifdef CONFIG_CM_REMAP
+       /* CM remap bit is operational
+        * - use it to map writeable memory at 0x00000000, in place of flash
+        */
+.globl cm_remap
+cm_remap:
+       stmfd   r13!,{r4-r10,lr}
+
+       mov     r0, #CM_BASE
+       ldr     r1, [r0, #OS_CTRL]
+       orr     r1, r1, #CMMASK_REMAP   /* set remap and led bits */
+       str     r1, [r0, #OS_CTRL]
+
+       /* Now 0x00000000 is writeable, replace the vectors  */
+       ldr     r0, =_start     /* r0 <- start of vectors           */
+       ldr     r2, =_armboot_start     /* r2 <- past vectors               */
+       sub     r1,r1,r1                /* destination 0x00000000           */
+
+copy_vec:
+       ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
+       stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
+       cmp     r0, r2                  /* until source end address [r2]    */
+       ble     copy_vec
+
+       ldmfd   r13!,{r4-r10,pc}        /* back to caller                   */
+
+#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/board/integratorap/platform.S b/board/integratorap/platform.S
deleted file mode 100644 (file)
index b208adb..0000000
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-       /* Reset using CM control register */
-.global reset_cpu
-reset_cpu:
-       mov     r0, #CM_BASE
-       ldr     r1,[r0,#OS_CTRL]
-       orr     r1,r1,#CMMASK_RESET
-       str     r1,[r0,#OS_CTRL]
-
-reset_failed:
-       b       reset_failed
-
-/* set up the platform, once the cpu has been initialized */
-.globl platformsetup
-platformsetup:
-       /* If U-Boot has been run after the ARM boot monitor
-        * then all the necessary actions have been done
-        * otherwise we are running from user flash mapped to 0x00000000
-        * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
-        * Changes to the (possibly soft) reset defaults of the processor
-        * itself should be performed in cpu/arm<>/start.S
-        * This function affects only the core module or board settings
-        */
-
-#ifdef CONFIG_CM_INIT
-       /* CM has an initialization register
-        * - bits in it are wired into test-chip pins to force
-        *   reset defaults
-        * - may need to change its contents for U-Boot
-        */
-
-       /* set the desired CM specific value */
-       mov     r2,#CMMASK_LOWVEC       /* Vectors at 0x00000000 for all */
-
-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
-       orr     r2,r2,#CMMASK_INIT_102
-#else
-
-#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
-     !defined (CONFIG_CM940T)
-
-#ifdef CONFIG_CM_MULTIPLE_SSRAM
-       /* set simple mapping             */
-       and     r2,r2,#CMMASK_MAP_SIMPLE
-#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
-
-#ifdef CONFIG_CM_TCRAM
-       /* disable TCRAM                  */
-       and     r2,r2,#CMMASK_TCRAM_DISABLE
-#endif /* #ifdef CONFIG_CM_TCRAM         */
-
-#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
-           defined (CONFIG_CM1136JF_S)
-
-       and     r2,r2,#CMMASK_LE
-
-#endif /* cpu with little endian initialization */
-
-       orr     r2,r2,#CMMASK_CMxx6_COMMON
-
-#endif /* CMxx6 code */
-
-#endif /* ARM102xxE value */
-
-       /* read CM_INIT    */
-       mov     r0, #CM_BASE
-       ldr     r1, [r0, #OS_INIT]
-       /* check against desired bit setting */
-       and     r3,r1,r2
-       cmp     r3,r2
-       beq     init_reg_OK
-
-       /* lock for change */
-       mov     r3, #CMVAL_LOCK1
-       add     r3,r3,#CMVAL_LOCK2
-       str     r3, [r0, #OS_LOCK]
-       /* set desired value */
-       orr     r1,r1,r2
-       /* write & relock CM_INIT */
-       str     r1, [r0, #OS_INIT]
-       mov     r1, #CMVAL_UNLOCK
-       str     r1, [r0, #OS_LOCK]
-
-       /* soft reset so new values used */
-       b       reset_cpu
-
-init_reg_OK:
-
-#endif /* CONFIG_CM_INIT */
-
-       mov     pc, lr
-
-#ifdef CONFIG_CM_SPD_DETECT
-       /* Fast memory is available for the DRAM data
-        * - ensure it has been transferred, then summarize the data
-        *   into a CM register
-        */
-.globl dram_query
-dram_query:
-       stmfd   r13!,{r4-r6,lr}
-       /* set up SDRAM info                              */
-       /* - based on example code from the CM User Guide */
-       mov     r0, #CM_BASE
-
-readspdbit:
-       ldr     r1, [r0, #OS_SDRAM]     /* read the SDRAM register */
-       and     r1, r1, #0x20           /* mask SPD bit (5)        */
-       cmp     r1, #0x20               /* test if set             */
-       bne     readspdbit
-
-setupsdram:
-       add     r0, r0, #OS_SPD         /* address the copy of the SDP data */
-       ldrb    r1, [r0, #3]            /* number of row address lines      */
-       ldrb    r2, [r0, #4]            /* number of column address lines   */
-       ldrb    r3, [r0, #5]            /* number of banks                  */
-       ldrb    r4, [r0, #31]           /* module bank density              */
-       mul     r5, r4, r3              /* size of SDRAM (MB divided by 4)  */
-       mov     r5, r5, ASL#2           /* size in MB                       */
-       mov     r0, #CM_BASE            /* reload for later code            */
-       cmp     r5, #0x10               /* is it 16MB?                      */
-       bne     not16
-       mov     r6, #0x2                /* store size and CAS latency of 2  */
-       b       writesize
-
-not16:
-       cmp     r5, #0x20               /* is it  32MB? */
-       bne     not32
-       mov     r6, #0x6
-       b       writesize
-
-not32:
-       cmp     r5, #0x40               /* is it  64MB? */
-       bne     not64
-       mov     r6, #0xa
-       b       writesize
-
-not64:
-       cmp     r5, #0x80               /* is it 128MB? */
-       bne     not128
-       mov     r6, #0xe
-       b       writesize
-
-not128:
-       /* if it is none of these sizes then it is either 256MB, or
-        * there is no SDRAM fitted so default to 256MB
-        */
-       mov     r6, #0x12
-
-writesize:
-       mov     r1, r1, ASL#8           /* row addr lines from SDRAM reg */
-       orr     r2, r1, r2, ASL#12      /* OR in column address lines    */
-       orr     r3, r2, r3, ASL#16      /* OR in number of banks         */
-       orr     r6, r6, r3              /* OR in size and CAS latency    */
-       str     r6, [r0, #OS_SDRAM]     /* store SDRAM parameters        */
-
-#endif /* #ifdef CONFIG_CM_SPD_DETECT */
-
-       ldmfd   r13!,{r4-r6,pc}                 /* back to caller */
-
-#ifdef CONFIG_CM_REMAP
-       /* CM remap bit is operational
-        * - use it to map writeable memory at 0x00000000, in place of flash
-        */
-.globl cm_remap
-cm_remap:
-       stmfd   r13!,{r4-r10,lr}
-
-       mov     r0, #CM_BASE
-       ldr     r1, [r0, #OS_CTRL]
-       orr     r1, r1, #CMMASK_REMAP   /* set remap and led bits */
-       str     r1, [r0, #OS_CTRL]
-
-       /* Now 0x00000000 is writeable, replace the vectors  */
-       ldr     r0, =_start     /* r0 <- start of vectors           */
-       ldr     r2, =_armboot_start     /* r2 <- past vectors               */
-       sub     r1,r1,r1                /* destination 0x00000000           */
-
-copy_vec:
-       ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
-       stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       ble     copy_vec
-
-       ldmfd   r13!,{r4-r10,pc}        /* back to caller                   */
-
-#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/board/integratorap/split_by_variant.sh b/board/integratorap/split_by_variant.sh
new file mode 100644 (file)
index 0000000..23fc7b3
--- /dev/null
@@ -0,0 +1,106 @@
+#!/bin/sh
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+echo -n "/* Integrator configuration implied "   > tmp.fil
+echo    " by Makefile target */"               >> tmp.fil
+echo -n "#define CONFIG_INTEGRATOR"            >> tmp.fil
+echo    " /* Integrator board */"              >> tmp.fil
+echo -n "#define CONFIG_ARCH_INTEGRATOR"       >> tmp.fil
+echo     " 1 /* Integrator/AP   */"            >> tmp.fil
+# ---------------------------------------------------------
+#  Set the core module defines according to Core Module
+# ---------------------------------------------------------
+CC=$(CROSS_COMPILE)gcc
+cpu="arm_intcm"
+
+if [ "$2" == "" ]
+then
+       echo "$0:: No preprocessor parameter - using $(CROSS_COMPILE)gcc"
+else
+       CC=$2
+fi
+
+
+if [ "$1" == "" ]
+then
+       echo "$0:: No parameters - using $(CROSS_COMPILE)gcc arm_intcm"
+else
+       case "$1" in
+       ap7_config              |       \
+       ap966_config            |       \
+       ap922_config            |       \
+       integratorap_config     |       \
+       ap_config)
+       cpu="arm_intcm"
+       ;;
+
+       ap720t_config)
+       cpu="arm720t"
+       echo -n "#define CONFIG_CM720T"         >> tmp.fil
+       echo    " 1 /* CPU core is ARM720T */ " >> tmp.fil
+       ;;
+
+       ap922_XA10_config)
+       echo -n "#define CONFIG_CM922T_XA10"            >> tmp.fil
+       echo    " 1 /* CPU core is ARM922T_XA10 */"     >> tmp.fil
+       cpu="arm_intcm"
+       ;;
+
+       ap920t_config)
+       cpu="arm920t"
+       echo -n "#define CONFIG_CM920T"                 >> tmp.fil
+       echo    " 1 /* CPU core is ARM920T */"          >> tmp.fil
+       ;;
+
+       ap926ejs_config)
+       cpu="arm926ejs"
+       echo -n "#define CONFIG_CM926EJ_S"              >> tmp.fil
+       echo    " 1 /* CPU core is ARM926EJ-S */ "      >> tmp.fil
+       ;;
+
+
+       ap946es_config)
+       cpu="arm946es"
+       echo -n "#define CONFIG_CM946E_S"               >> tmp.fil
+       echo    " 1 /* CPU core is ARM946E-S */ "       >> tmp.fil
+       ;;
+
+       *)
+       echo "$0:: Unrecognised target - using arm_intcm"
+       cpu="arm_intcm"
+       ;;
+
+       esac
+
+fi
+
+if [ "$cpu" == "arm_intcm" ]
+then
+       echo "/* Core module undefined/not ported */"   >> tmp.fil
+       echo "#define CONFIG_ARM_INTCM 1"               >> tmp.fil
+       echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM"       >> tmp.fil
+       echo -n "  /* CM may not have "                 >> tmp.fil
+       echo    "multiple SSRAM mapping */"             >> tmp.fil
+       echo -n "#undef CONFIG_CM_SPD_DETECT "          >> tmp.fil
+       echo -n " /* CM may not support SPD "           >> tmp.fil
+       echo    "query */"                              >> tmp.fil
+       echo -n "#undef CONFIG_CM_REMAP  "              >> tmp.fil
+       echo -n " /* CM may not support "               >> tmp.fil
+       echo    "remapping */"                          >> tmp.fil
+       echo -n "#undef CONFIG_CM_INIT  "               >> tmp.fil
+       echo -n " /* CM may not have  "                 >> tmp.fil
+       echo    "initialization reg */"                 >> tmp.fil
+       echo -n "#undef CONFIG_CM_TCRAM  "              >> tmp.fil
+       echo    " /* CM may not have TCRAM */"          >> tmp.fil
+fi
+mv tmp.fil ./include/config.h
+# ---------------------------------------------------------
+#  Ensure correct core object loaded first in U-Boot image
+# ---------------------------------------------------------
+$CC -E -P -C -D CPU_FILE=cpu/$cpu/start.o              \
+-o board/integratorap/u-boot.lds board/integratorap/u-boot.lds.S
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+./mkconfig -a integratorap arm $cpu integratorap;
diff --git a/board/integratorap/u-boot.lds b/board/integratorap/u-boot.lds
deleted file mode 100644 (file)
index cb6ee18..0000000
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-       . = 0x00000000;
-       . = ALIGN(4);
-       .text   :
-       {
-         cpu/arm926ejs/start.o (.text)
-         *(.text)
-       }
-       .rodata : { *(.rodata) }
-       . = ALIGN(4);
-       .data : { *(.data) }
-       . = ALIGN(4);
-       .got : { *(.got) }
-
-       . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
-
-       . = ALIGN(4);
-       __bss_start = .;
-       .bss : { *(.bss) }
-       _end = .;
-}
diff --git a/board/integratorap/u-boot.lds.S b/board/integratorap/u-boot.lds.S
new file mode 100644 (file)
index 0000000..486b5da
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* Preprocessed during configuration to emsure the core module processor code,
+   from CPU_FILE, is placed at the start of the image */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+       . = ALIGN(4);
+       .text   :
+       {
+         CPU_FILE (.text)
+         *(.text)
+       }
+       .rodata : { *(.rodata) }
+       . = ALIGN(4);
+       .data : { *(.data) }
+       . = ALIGN(4);
+       .got : { *(.got) }
+
+       . = .;
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}
index 71532d11367789ac240f08574cbdf3b99f65e38e..3d589fcd5ad5e824790bc1385b75323329fc4cca 100644 (file)
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    = lib$(BOARD).a
 
 OBJS   := integratorcp.o flash.o
-SOBJS  := platform.o memsetup.o
+SOBJS  := lowlevel_init.o memsetup.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $^
diff --git a/board/integratorcp/lowlevel_init.S b/board/integratorcp/lowlevel_init.S
new file mode 100644 (file)
index 0000000..e679215
--- /dev/null
@@ -0,0 +1,214 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Reset using CM control register */
+.global reset_cpu
+reset_cpu:
+       mov     r0, #CM_BASE
+       ldr     r1,[r0,#OS_CTRL]
+       orr     r1,r1,#CMMASK_RESET
+       str     r1,[r0,#OS_CTRL]
+
+reset_failed:
+       b       reset_failed
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+       /* If U-Boot has been run after the ARM boot monitor
+        * then all the necessary actions have been done
+        * otherwise we are running from user flash mapped to 0x00000000
+        * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+        * Changes to the (possibly soft) reset defaults of the processor
+        * itself should be performed in cpu/arm<>/start.S
+        * This function affects only the core module or board settings
+        */
+
+#ifdef CONFIG_CM_INIT
+       /* CM has an initialization register
+        * - bits in it are wired into test-chip pins to force
+        *   reset defaults
+        * - may need to change its contents for U-Boot
+        */
+
+       /* set the desired CM specific value */
+       mov     r2,#CMMASK_LOWVEC       /* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+       orr     r2,r2,#CMMASK_INIT_102
+#else
+
+#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+    !defined (CONFIG_CM940T)
+    /* CMxx6 code */
+
+#ifdef CONFIG_CM_MULTIPLE_SSRAM
+       /* set simple mapping             */
+       and     r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
+
+#ifdef CONFIG_CM_TCRAM
+       /* disable TCRAM                  */
+       and     r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM         */
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+           defined (CONFIG_CM1136JF_S)
+
+       and     r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+       orr     r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+       /* read CM_INIT    */
+       mov     r0, #CM_BASE
+       ldr     r1, [r0, #OS_INIT]
+       /* check against desired bit setting */
+       and     r3,r1,r2
+       cmp     r3,r2
+       beq     init_reg_OK
+
+       /* lock for change */
+       mov     r3, #CMVAL_LOCK1
+       and     r3, r3, #CMVAL_LOCK2
+       str     r3, [r0, #OS_LOCK]
+       /* set desired value */
+       orr     r1,r1,r2
+       /* write & relock CM_INIT */
+       str     r1, [r0, #OS_INIT]
+       mov     r1, #CMVAL_UNLOCK
+       str     r1, [r0, #OS_LOCK]
+
+       /* soft reset so new values used */
+       b       reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+       mov     pc, lr
+
+#ifdef CONFIG_CM_SPD_DETECT
+       /* Fast memory is available for the DRAM data
+        * - ensure it has been transferred, then summarize the data
+        *   into a CM register
+        */
+.globl dram_query
+dram_query:
+       stmfd   r13!,{r4-r6,lr}
+       /* set up SDRAM info                              */
+       /* - based on example code from the CM User Guide */
+       mov     r0, #CM_BASE
+
+readspdbit:
+       ldr     r1, [r0, #OS_SDRAM]     /* read the SDRAM register */
+       and     r1, r1, #0x20           /* mask SPD bit (5)        */
+       cmp     r1, #0x20               /* test if set             */
+       bne     readspdbit
+
+setupsdram:
+       add     r0, r0, #OS_SPD         /* address the copy of the SDP data */
+       ldrb    r1, [r0, #3]            /* number of row address lines      */
+       ldrb    r2, [r0, #4]            /* number of column address lines   */
+       ldrb    r3, [r0, #5]            /* number of banks                  */
+       ldrb    r4, [r0, #31]           /* module bank density              */
+       mul     r5, r4, r3              /* size of SDRAM (MB divided by 4)  */
+       mov     r5, r5, ASL#2           /* size in MB                       */
+       mov     r0, #CM_BASE            /* reload for later code            */
+       cmp     r5, #0x10               /* is it 16MB?                      */
+       bne     not16
+       mov     r6, #0x2                /* store size and CAS latency of 2  */
+       b       writesize
+
+not16:
+       cmp     r5, #0x20               /* is it  32MB? */
+       bne     not32
+       mov     r6, #0x6
+       b       writesize
+
+not32:
+       cmp     r5, #0x40               /* is it  64MB? */
+       bne     not64
+       mov     r6, #0xa
+       b       writesize
+
+not64:
+       cmp     r5, #0x80               /* is it 128MB? */
+       bne     not128
+       mov     r6, #0xe
+       b       writesize
+
+not128:
+       /* if it is none of these sizes then it is either 256MB, or
+        * there is no SDRAM fitted so default to 256MB
+        */
+       mov     r6, #0x12
+
+writesize:
+       mov     r1, r1, ASL#8           /* row addr lines from SDRAM reg */
+       orr     r2, r1, r2, ASL#12      /* OR in column address lines    */
+       orr     r3, r2, r3, ASL#16      /* OR in number of banks         */
+       orr     r6, r6, r3              /* OR in size and CAS latency    */
+       str     r6, [r0, #OS_SDRAM]     /* store SDRAM parameters        */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+       ldmfd   r13!,{r4-r6,pc}                 /* back to caller */
+
+#ifdef CONFIG_CM_REMAP
+       /* CM remap bit is operational
+        * - use it to map writeable memory at 0x00000000, in place of flash
+        */
+.globl cm_remap
+cm_remap:
+       stmfd   r13!,{r4-r10,lr}
+
+       mov     r0, #CM_BASE
+       ldr     r1, [r0, #OS_CTRL]
+       orr     r1, r1, #CMMASK_REMAP   /* set remap and led bits */
+       str     r1, [r0, #OS_CTRL]
+
+       /* Now 0x00000000 is writeable, replace the vectors  */
+       ldr     r0, =_start     /* r0 <- start of vectors           */
+       ldr     r2, =_armboot_start     /* r2 <- past vectors               */
+       sub     r1,r1,r1                /* destination 0x00000000           */
+
+copy_vec:
+       ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
+       stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
+       cmp     r0, r2                  /* until source end address [r2]    */
+       ble     copy_vec
+
+       ldmfd   r13!,{r4-r10,pc}        /* back to caller                   */
+
+#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/board/integratorcp/platform.S b/board/integratorcp/platform.S
deleted file mode 100644 (file)
index 612a2c4..0000000
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-/* Reset using CM control register */
-.global reset_cpu
-reset_cpu:
-       mov     r0, #CM_BASE
-       ldr     r1,[r0,#OS_CTRL]
-       orr     r1,r1,#CMMASK_RESET
-       str     r1,[r0,#OS_CTRL]
-
-reset_failed:
-       b       reset_failed
-
-/* set up the platform, once the cpu has been initialized */
-.globl platformsetup
-platformsetup:
-       /* If U-Boot has been run after the ARM boot monitor
-        * then all the necessary actions have been done
-        * otherwise we are running from user flash mapped to 0x00000000
-        * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
-        * Changes to the (possibly soft) reset defaults of the processor
-        * itself should be performed in cpu/arm<>/start.S
-        * This function affects only the core module or board settings
-        */
-
-#ifdef CONFIG_CM_INIT
-       /* CM has an initialization register
-        * - bits in it are wired into test-chip pins to force
-        *   reset defaults
-        * - may need to change its contents for U-Boot
-        */
-
-       /* set the desired CM specific value */
-       mov     r2,#CMMASK_LOWVEC       /* Vectors at 0x00000000 for all */
-
-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
-       orr     r2,r2,#CMMASK_INIT_102
-#else
-
-#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
-    !defined (CONFIG_CM940T)
-    /* CMxx6 code */
-
-#ifdef CONFIG_CM_MULTIPLE_SSRAM
-       /* set simple mapping             */
-       and     r2,r2,#CMMASK_MAP_SIMPLE
-#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
-
-#ifdef CONFIG_CM_TCRAM
-       /* disable TCRAM                  */
-       and     r2,r2,#CMMASK_TCRAM_DISABLE
-#endif /* #ifdef CONFIG_CM_TCRAM         */
-
-#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
-           defined (CONFIG_CM1136JF_S)
-
-       and     r2,r2,#CMMASK_LE
-
-#endif /* cpu with little endian initialization */
-
-       orr     r2,r2,#CMMASK_CMxx6_COMMON
-
-#endif /* CMxx6 code */
-
-#endif /* ARM102xxE value */
-
-       /* read CM_INIT    */
-       mov     r0, #CM_BASE
-       ldr     r1, [r0, #OS_INIT]
-       /* check against desired bit setting */
-       and     r3,r1,r2
-       cmp     r3,r2
-       beq     init_reg_OK
-
-       /* lock for change */
-       mov     r3, #CMVAL_LOCK1
-       and     r3, r3, #CMVAL_LOCK2
-       str     r3, [r0, #OS_LOCK]
-       /* set desired value */
-       orr     r1,r1,r2
-       /* write & relock CM_INIT */
-       str     r1, [r0, #OS_INIT]
-       mov     r1, #CMVAL_UNLOCK
-       str     r1, [r0, #OS_LOCK]
-
-       /* soft reset so new values used */
-       b       reset_cpu
-
-init_reg_OK:
-
-#endif /* CONFIG_CM_INIT */
-
-       mov     pc, lr
-
-#ifdef CONFIG_CM_SPD_DETECT
-       /* Fast memory is available for the DRAM data
-        * - ensure it has been transferred, then summarize the data
-        *   into a CM register
-        */
-.globl dram_query
-dram_query:
-       stmfd   r13!,{r4-r6,lr}
-       /* set up SDRAM info                              */
-       /* - based on example code from the CM User Guide */
-       mov     r0, #CM_BASE
-
-readspdbit:
-       ldr     r1, [r0, #OS_SDRAM]     /* read the SDRAM register */
-       and     r1, r1, #0x20           /* mask SPD bit (5)        */
-       cmp     r1, #0x20               /* test if set             */
-       bne     readspdbit
-
-setupsdram:
-       add     r0, r0, #OS_SPD         /* address the copy of the SDP data */
-       ldrb    r1, [r0, #3]            /* number of row address lines      */
-       ldrb    r2, [r0, #4]            /* number of column address lines   */
-       ldrb    r3, [r0, #5]            /* number of banks                  */
-       ldrb    r4, [r0, #31]           /* module bank density              */
-       mul     r5, r4, r3              /* size of SDRAM (MB divided by 4)  */
-       mov     r5, r5, ASL#2           /* size in MB                       */
-       mov     r0, #CM_BASE            /* reload for later code            */
-       cmp     r5, #0x10               /* is it 16MB?                      */
-       bne     not16
-       mov     r6, #0x2                /* store size and CAS latency of 2  */
-       b       writesize
-
-not16:
-       cmp     r5, #0x20               /* is it  32MB? */
-       bne     not32
-       mov     r6, #0x6
-       b       writesize
-
-not32:
-       cmp     r5, #0x40               /* is it  64MB? */
-       bne     not64
-       mov     r6, #0xa
-       b       writesize
-
-not64:
-       cmp     r5, #0x80               /* is it 128MB? */
-       bne     not128
-       mov     r6, #0xe
-       b       writesize
-
-not128:
-       /* if it is none of these sizes then it is either 256MB, or
-        * there is no SDRAM fitted so default to 256MB
-        */
-       mov     r6, #0x12
-
-writesize:
-       mov     r1, r1, ASL#8           /* row addr lines from SDRAM reg */
-       orr     r2, r1, r2, ASL#12      /* OR in column address lines    */
-       orr     r3, r2, r3, ASL#16      /* OR in number of banks         */
-       orr     r6, r6, r3              /* OR in size and CAS latency    */
-       str     r6, [r0, #OS_SDRAM]     /* store SDRAM parameters        */
-
-#endif /* #ifdef CONFIG_CM_SPD_DETECT */
-
-       ldmfd   r13!,{r4-r6,pc}                 /* back to caller */
-
-#ifdef CONFIG_CM_REMAP
-       /* CM remap bit is operational
-        * - use it to map writeable memory at 0x00000000, in place of flash
-        */
-.globl cm_remap
-cm_remap:
-       stmfd   r13!,{r4-r10,lr}
-
-       mov     r0, #CM_BASE
-       ldr     r1, [r0, #OS_CTRL]
-       orr     r1, r1, #CMMASK_REMAP   /* set remap and led bits */
-       str     r1, [r0, #OS_CTRL]
-
-       /* Now 0x00000000 is writeable, replace the vectors  */
-       ldr     r0, =_start     /* r0 <- start of vectors           */
-       ldr     r2, =_armboot_start     /* r2 <- past vectors               */
-       sub     r1,r1,r1                /* destination 0x00000000           */
-
-copy_vec:
-       ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
-       stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       ble     copy_vec
-
-       ldmfd   r13!,{r4-r10,pc}        /* back to caller                   */
-
-#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/board/integratorcp/split_by_variant.sh b/board/integratorcp/split_by_variant.sh
new file mode 100644 (file)
index 0000000..3f63633
--- /dev/null
@@ -0,0 +1,106 @@
+#!/bin/sh
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+echo -n "/* Integrator configuration implied "   > tmp.fil
+echo    " by Makefile target */"               >> tmp.fil
+echo -n "#define CONFIG_INTEGRATOR"            >> tmp.fil
+echo    " /* Integrator board */"              >> tmp.fil
+echo -n "#define CONFIG_ARCH_CINTEGRATOR"      >> tmp.fil
+echo     " 1 /* Integrator/CP   */"            >> tmp.fil
+# ---------------------------------------------------------
+#  Set the core module defines according to Core Module
+# ---------------------------------------------------------
+CC=$(CROSS_COMPILE)gcc
+cpu="arm_intcm"
+
+if [ "$2" == "" ]
+then
+       echo "$0:: No preprocessor parameter - using $(CROSS_COMPILE)gcc"
+else
+       CC=$2
+fi
+
+
+if [ "$1" == "" ]
+then
+       echo "$0:: No parameters - using $(CROSS_COMPILE)gcc arm_intcm"
+else
+       case "$1" in
+       cp966_config            |       \
+       cp922_config            |       \
+       cp1026_config           |       \
+       integratorcp_config     |       \
+       cp_config)
+       cpu="arm_intcm"
+       ;;
+
+       cp922_XA10_config)
+       echo -n "#define CONFIG_CM922T_XA10"            >> tmp.fil
+       echo    " 1 /* CPU core is ARM922T_XA10 */"     >> tmp.fil
+       cpu="arm_intcm"
+       ;;
+
+       cp920t_config)
+       cpu="arm920t"
+       echo -n "#define CONFIG_CM920T"                 >> tmp.fil
+       echo    " 1 /* CPU core is ARM920T */"          >> tmp.fil
+       ;;
+
+       cp926ejs_config)
+       cpu="arm926ejs"
+       echo -n "#define CONFIG_CM926EJ_S"              >> tmp.fil
+       echo    " 1 /* CPU core is ARM926EJ-S */ "      >> tmp.fil
+       ;;
+
+
+       cp946es_config)
+       cpu="arm946es"
+       echo -n "#define CONFIG_CM946E_S"               >> tmp.fil
+       echo    " 1 /* CPU core is ARM946E-S */ "       >> tmp.fil
+       ;;
+
+       cp1136_config)
+       cpu="arm1136"
+       echo -n "#define CONFIG_CM1136EJF_S"            >> tmp.fil
+       echo    " 1 /* CPU core is ARM1136JF-S */ "     >> tmp.fil
+       ;;
+
+       *)
+       echo "$0:: Unrecognised target - using arm_intcm"
+       cpu="arm_intcm"
+       ;;
+
+       esac
+
+fi
+
+if [ "$cpu" == "arm_intcm" ]
+then
+       echo "/* Core module undefined/not ported */"   >> tmp.fil
+       echo "#define CONFIG_ARM_INTCM 1"               >> tmp.fil
+       echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM"       >> tmp.fil
+       echo -n "  /* CM may not have "                 >> tmp.fil
+       echo    "multiple SSRAM mapping */"             >> tmp.fil
+       echo -n "#undef CONFIG_CM_SPD_DETECT "          >> tmp.fil
+       echo -n " /* CM may not support SPD "           >> tmp.fil
+       echo    "query */"                              >> tmp.fil
+       echo -n "#undef CONFIG_CM_REMAP  "              >> tmp.fil
+       echo -n " /* CM may not support "               >> tmp.fil
+       echo    "remapping */"                          >> tmp.fil
+       echo -n "#undef CONFIG_CM_INIT  "               >> tmp.fil
+       echo -n " /* CM may not have  "                 >> tmp.fil
+       echo    "initialization reg */"                 >> tmp.fil
+       echo -n "#undef CONFIG_CM_TCRAM  "              >> tmp.fil
+       echo    " /* CM may not have TCRAM */"          >> tmp.fil
+fi
+mv tmp.fil ./include/config.h
+# ---------------------------------------------------------
+#  Ensure correct core object loaded first in U-Boot image
+# ---------------------------------------------------------
+$CC -E -P -C -D CPU_FILE=cpu/$cpu/start.o              \
+-o board/integratorcp/u-boot.lds board/integratorcp/u-boot.lds.S
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+./mkconfig -a integratorcp arm $cpu integratorcp;
diff --git a/board/integratorcp/u-boot.lds b/board/integratorcp/u-boot.lds
deleted file mode 100644 (file)
index cb6ee18..0000000
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-       . = 0x00000000;
-       . = ALIGN(4);
-       .text   :
-       {
-         cpu/arm926ejs/start.o (.text)
-         *(.text)
-       }
-       .rodata : { *(.rodata) }
-       . = ALIGN(4);
-       .data : { *(.data) }
-       . = ALIGN(4);
-       .got : { *(.got) }
-
-       . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
-
-       . = ALIGN(4);
-       __bss_start = .;
-       .bss : { *(.bss) }
-       _end = .;
-}
diff --git a/board/integratorcp/u-boot.lds.S b/board/integratorcp/u-boot.lds.S
new file mode 100644 (file)
index 0000000..486b5da
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* Preprocessed during configuration to emsure the core module processor code,
+   from CPU_FILE, is placed at the start of the image */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+       . = ALIGN(4);
+       .text   :
+       {
+         CPU_FILE (.text)
+         *(.text)
+       }
+       .rodata : { *(.rodata) }
+       . = ALIGN(4);
+       .data : { *(.data) }
+       . = ALIGN(4);
+       .got : { *(.got) }
+
+       . = .;
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}
index d2718cc683a531e65e76935f717b482616043304..fb4333c19c0277522186687009ee6706fcb79c9a 100644 (file)
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    = lib$(BOARD).a
 
 OBJS   := ns9750dev.o flash.o led.o
-SOBJS  := platform.o
+SOBJS  := lowlevel_init.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $(OBJS) $(SOBJS)
diff --git a/board/ns9750dev/lowlevel_init.S b/board/ns9750dev/lowlevel_init.S
new file mode 100644 (file)
index 0000000..3a09786
--- /dev/null
@@ -0,0 +1,298 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for the NS9750 DevBoard by
+ * (C) Copyright 2004 by FS Forth-Systeme GmbH.
+ * Markus Pietrek <mpietrek@fsforth.de>
+ * @References: [1] NS9750 Hardware Reference/December 2003
+ *             [2] ns9750_a.cmd from MAJIC configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_NS9750DEV)
+# ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#  include <./ns9750_sys.h>
+#  include <./ns9750_mem.h>
+# endif
+#endif
+
+/***********************************************************************
+ * @Function: write_register_block
+ * @Return: nothing
+ * @Descr: Copies the register block of register_offset:register value to
+ *         the registers at base r0. The block is assumed to start in RAM at r1
+ *         and end at r2. The linked RAM base address of U-Boot is assumed to be
+ *        in r5 while the ROM base address we are running from is r6
+ *         Uses r3 and r4 as tempory registers
+ ***********************************************************************/
+
+.macro write_register_block
+       @@ map the addresses to high memory
+       sub     r1, r1, r5
+       add     r1, r1, r6
+       sub     r2, r2, r5
+       add     r2, r2, r6
+
+       @@ copy all
+1:
+       @@ Write register/value pair starting at [r1] to register base r0
+       ldr     r3, [r1], #4
+       ldr     r4, [r1], #4
+       str     r4, [r0,r3]
+       cmp     r1, r2
+       blt     1b
+.endm
+
+_TEXT_BASE:
+       .word   TEXT_BASE       @ sdram load addr from config.mk
+_PHYS_FLASH:
+       .word   PHYS_FLASH_1    @ real flash address (without mirroring)
+_CAS_LATENCY:
+       .word   0x00022000      @ for CAS2 latency
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl lowlevel_init
+lowlevel_init:
+
+       /* U-Boot may be linked to RAM at 0x780000. But this code will run in
+          flash from 0x0. But in order to enable RAM we have to disable the
+          mirror bit, therefore we have to jump to our real flash address
+          beginning at PHYS_FLASH_1 (CS4 Base). Therefore,
+          _run_at_real_flash_address may be 0x500003b0 while be linked to
+          0x7803b0. So we must modify our linked addresses */
+
+       @@ branch to high memory address, away from 0x0
+       ldr     r5, _TEXT_BASE
+       ldr     r6, _PHYS_FLASH
+       ldr     r0, =_run_at_real_flash_address
+       sub     r0, r0, r5
+       add     r0, r0, r6
+       mov     pc, r0
+       nop                     @ for pipelining
+
+_run_at_real_flash_address:
+       @@ now we are running > PHYS_FLASH_1, safe to enable memory controller
+
+       @@ Write Memory Configuration Registers
+
+       ldr     r0, _NS9750_MEM_MODULE_BASE
+       ldr     r1, =_MEM_CONFIG_START
+       ldr     r2, =_MEM_CONFIG_END
+
+       write_register_block
+
+       @@ Give SDRAM some time to settle
+       @@ @TODO. According to [2] it should be 2 AHB cycles. Check
+
+       ldr     r1, =0x50
+_sdram_settle:
+       subs    r1, r1, #1
+       bne     _sdram_settle
+
+_enable_mappings:
+       @@ Enable SDRAM Mode
+
+       ldr     r1, =_MEM_MODE_START
+       ldr     r2, =_MEM_MODE_END
+
+       write_register_block
+
+       ldr     r3, _CAS_LATENCY @ perform one read from SDRAM
+       ldr     r3, [r3]
+
+       @@ Enable SDRAM and memory mappings
+
+       ldr     r1, =_MEM_ENABLE_START
+       ldr     r2, =_MEM_ENABLE_END
+
+       write_register_block
+
+       @@ Activate AHB monitor
+
+       ldr     r0, =NS9750_SYS_MODULE_BASE
+       ldr     r1, =_AHB_MONITOR_START
+       ldr     r2, =_AHB_MONITOR_END
+
+       write_register_block
+_relocate_lr:
+       /* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to
+          PHYS_FLASH. */
+       mov     r1, ip
+       add     r1, r1, r6
+       mov     ip, r1
+
+       mov     r1, lr
+       add     r1, r1, r6
+       mov     lr, r1
+
+       @@ back to arch calling code
+       mov     pc,     lr
+
+       .ltorg
+
+_NS9750_MEM_MODULE_BASE:
+       .word   NS9750_MEM_MODULE_BASE
+
+_MEM_CONFIG_START:
+       /* Table of 2 32bit entries. First word is register address offset
+          relative to NS9750_MEM_MODULE_BASE, second one is value. They are
+          written in order of appearance */
+
+       @@ Register values taken from [2]
+       .word   NS9750_MEM_CTRL
+       .word   NS9750_MEM_CTRL_E
+
+       .word   NS9750_MEM_DYN_REFRESH
+       .word   (0x6 & NS9750_MEM_DYN_REFRESH_MA)
+
+       .word   NS9750_MEM_DYN_READ_CFG
+       .word   (0x1 & NS9750_MEM_DYN_READ_CFG_MA)
+
+       .word   NS9750_MEM_DYN_TRP
+       .word   (0x1 & NS9750_MEM_DYN_TRP_MA)
+
+       .word   NS9750_MEM_DYN_TRAS
+       .word   (0x4 & NS9750_MEM_DYN_TRAS_MA)
+
+       .word   NS9750_MEM_DYN_TAPR
+       .word   (0x1 & NS9750_MEM_DYN_TRAS_MA)
+
+       .word   NS9750_MEM_DYN_TDAL
+       .word   (0x5 & NS9750_MEM_DYN_TDAL_MA)
+
+       .word   NS9750_MEM_DYN_TWR
+       .word   (0x1 & NS9750_MEM_DYN_TWR_MA)
+
+       .word   NS9750_MEM_DYN_TRC
+       .word   (0x6 & NS9750_MEM_DYN_TRC_MA)
+
+       .word   NS9750_MEM_DYN_TRFC
+       .word   (0x6 & NS9750_MEM_DYN_TRFC_MA)
+
+       .word   NS9750_MEM_DYN_TRRD
+       .word   (0x1 & NS9750_MEM_DYN_TRRD_MA)
+
+       .word   NS9750_MEM_DYN_TMRD
+       .word   (0x1 & NS9750_MEM_DYN_TMRD_MA)
+
+       @@ CS 4
+       .word   NS9750_MEM_DYN_CFG(0)
+       .word   (NS9750_MEM_DYN_CFG_AM | \
+                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+       .word   NS9750_MEM_DYN_RAS_CAS(0)
+       .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+                (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+       @@ CS 5
+       .word   NS9750_MEM_DYN_CFG(1)
+       .word   (NS9750_MEM_DYN_CFG_AM | \
+                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+       .word   NS9750_MEM_DYN_RAS_CAS(1)
+       .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+                (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+       @@ CS 6
+       .word   NS9750_MEM_DYN_CFG(2)
+       .word   (NS9750_MEM_DYN_CFG_AM | \
+                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+       .word   NS9750_MEM_DYN_RAS_CAS(2)
+       .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+                (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+       @@ CS 7
+       .word   NS9750_MEM_DYN_CFG(3)
+       .word   (NS9750_MEM_DYN_CFG_AM | \
+                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+       .word   NS9750_MEM_DYN_RAS_CAS(3)
+       .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+                (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+       .word   NS9750_MEM_DYN_CTRL
+       .word   (NS9750_MEM_DYN_CTRL_I_PALL | \
+                NS9750_MEM_DYN_CTRL_SR | \
+                NS9750_MEM_DYN_CTRL_CE )
+
+       .word   NS9750_MEM_DYN_REFRESH
+       .word   (0x1 & NS9750_MEM_DYN_REFRESH_MA)
+       @@ No further register settings after refresh
+_MEM_CONFIG_END:
+
+_MEM_MODE_START:
+       .word   NS9750_MEM_DYN_REFRESH
+       .word   (0x30 & NS9750_MEM_DYN_REFRESH_MA)
+
+       .word   NS9750_MEM_DYN_CTRL
+       .word   (NS9750_MEM_DYN_CTRL_I_MODE | \
+                NS9750_MEM_DYN_CTRL_SR | \
+                NS9750_MEM_DYN_CTRL_CE )
+_MEM_MODE_END:
+
+_MEM_ENABLE_START:
+       .word   NS9750_MEM_DYN_CTRL
+       .word   (NS9750_MEM_DYN_CTRL_I_NORMAL | \
+                NS9750_MEM_DYN_CTRL_SR | \
+                NS9750_MEM_DYN_CTRL_CE )
+
+       @@ CS 4
+       .word   NS9750_MEM_DYN_CFG(0)
+       .word   (NS9750_MEM_DYN_CFG_BDMC | \
+                NS9750_MEM_DYN_CFG_AM | \
+                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+       @@ CS 5
+       .word   NS9750_MEM_DYN_CFG(1)
+       .word   (NS9750_MEM_DYN_CFG_BDMC | \
+                NS9750_MEM_DYN_CFG_AM | \
+                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+       @@ CS 6
+       .word   NS9750_MEM_DYN_CFG(2)
+       .word   (NS9750_MEM_DYN_CFG_BDMC | \
+                NS9750_MEM_DYN_CFG_AM | \
+                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+       @@ CS 7
+       .word   NS9750_MEM_DYN_CFG(3)
+       .word   (NS9750_MEM_DYN_CFG_BDMC | \
+                NS9750_MEM_DYN_CFG_AM | \
+                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+_MEM_ENABLE_END:
+
+_AHB_MONITOR_START:
+       .word   NS9750_SYS_AHB_TIMEOUT
+       .word   0x01000100      @ @TODO not calculated yet
+
+       .word   NS9750_SYS_AHB_MON
+       .word   (NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \
+                NS9750_SYS_AHB_MON_BATC_GEN_IRQ)
+_AHB_MONITOR_END:
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/board/ns9750dev/platform.S b/board/ns9750dev/platform.S
deleted file mode 100644 (file)
index afcad15..0000000
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for the NS9750 DevBoard by
- * (C) Copyright 2004 by FS Forth-Systeme GmbH.
- * Markus Pietrek <mpietrek@fsforth.de>
- * @References: [1] NS9750 Hardware Reference/December 2003
- *             [2] ns9750_a.cmd from MAJIC configuration
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_NS9750DEV)
-# ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#  include <./ns9750_sys.h>
-#  include <./ns9750_mem.h>
-# endif
-#endif
-
-/***********************************************************************
- * @Function: write_register_block
- * @Return: nothing
- * @Descr: Copies the register block of register_offset:register value to
- *         the registers at base r0. The block is assumed to start in RAM at r1
- *         and end at r2. The linked RAM base address of U-Boot is assumed to be
- *        in r5 while the ROM base address we are running from is r6
- *         Uses r3 and r4 as tempory registers
- ***********************************************************************/
-
-.macro write_register_block
-       @@ map the addresses to high memory
-       sub     r1, r1, r5
-       add     r1, r1, r6
-       sub     r2, r2, r5
-       add     r2, r2, r6
-
-       @@ copy all
-1:
-       @@ Write register/value pair starting at [r1] to register base r0
-       ldr     r3, [r1], #4
-       ldr     r4, [r1], #4
-       str     r4, [r0,r3]
-       cmp     r1, r2
-       blt     1b
-.endm
-
-_TEXT_BASE:
-       .word   TEXT_BASE       @ sdram load addr from config.mk
-_PHYS_FLASH:
-       .word   PHYS_FLASH_1    @ real flash address (without mirroring)
-_CAS_LATENCY:
-       .word   0x00022000      @ for CAS2 latency
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-.globl platformsetup
-platformsetup:
-
-       /* U-Boot may be linked to RAM at 0x780000. But this code will run in
-          flash from 0x0. But in order to enable RAM we have to disable the
-          mirror bit, therefore we have to jump to our real flash address
-          beginning at PHYS_FLASH_1 (CS4 Base). Therefore,
-          _run_at_real_flash_address may be 0x500003b0 while be linked to
-          0x7803b0. So we must modify our linked addresses */
-
-       @@ branch to high memory address, away from 0x0
-       ldr     r5, _TEXT_BASE
-       ldr     r6, _PHYS_FLASH
-       ldr     r0, =_run_at_real_flash_address
-       sub     r0, r0, r5
-       add     r0, r0, r6
-       mov     pc, r0
-       nop                     @ for pipelining
-
-_run_at_real_flash_address:
-       @@ now we are running > PHYS_FLASH_1, safe to enable memory controller
-
-       @@ Write Memory Configuration Registers
-
-       ldr     r0, _NS9750_MEM_MODULE_BASE
-       ldr     r1, =_MEM_CONFIG_START
-       ldr     r2, =_MEM_CONFIG_END
-
-       write_register_block
-
-       @@ Give SDRAM some time to settle
-       @@ @TODO. According to [2] it should be 2 AHB cycles. Check
-
-       ldr     r1, =0x50
-_sdram_settle:
-       subs    r1, r1, #1
-       bne     _sdram_settle
-
-_enable_mappings:
-       @@ Enable SDRAM Mode
-
-       ldr     r1, =_MEM_MODE_START
-       ldr     r2, =_MEM_MODE_END
-
-       write_register_block
-
-       ldr     r3, _CAS_LATENCY @ perform one read from SDRAM
-       ldr     r3, [r3]
-
-       @@ Enable SDRAM and memory mappings
-
-       ldr     r1, =_MEM_ENABLE_START
-       ldr     r2, =_MEM_ENABLE_END
-
-       write_register_block
-
-       @@ Activate AHB monitor
-
-       ldr     r0, =NS9750_SYS_MODULE_BASE
-       ldr     r1, =_AHB_MONITOR_START
-       ldr     r2, =_AHB_MONITOR_END
-
-       write_register_block
-_relocate_lr:
-       /* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to
-          PHYS_FLASH. */
-       mov     r1, ip
-       add     r1, r1, r6
-       mov     ip, r1
-
-       mov     r1, lr
-       add     r1, r1, r6
-       mov     lr, r1
-
-       @@ back to arch calling code
-       mov     pc,     lr
-
-       .ltorg
-
-_NS9750_MEM_MODULE_BASE:
-       .word   NS9750_MEM_MODULE_BASE
-
-_MEM_CONFIG_START:
-       /* Table of 2 32bit entries. First word is register address offset
-          relative to NS9750_MEM_MODULE_BASE, second one is value. They are
-          written in order of appearance */
-
-       @@ Register values taken from [2]
-       .word   NS9750_MEM_CTRL
-       .word   NS9750_MEM_CTRL_E
-
-       .word   NS9750_MEM_DYN_REFRESH
-       .word   (0x6 & NS9750_MEM_DYN_REFRESH_MA)
-
-       .word   NS9750_MEM_DYN_READ_CFG
-       .word   (0x1 & NS9750_MEM_DYN_READ_CFG_MA)
-
-       .word   NS9750_MEM_DYN_TRP
-       .word   (0x1 & NS9750_MEM_DYN_TRP_MA)
-
-       .word   NS9750_MEM_DYN_TRAS
-       .word   (0x4 & NS9750_MEM_DYN_TRAS_MA)
-
-       .word   NS9750_MEM_DYN_TAPR
-       .word   (0x1 & NS9750_MEM_DYN_TRAS_MA)
-
-       .word   NS9750_MEM_DYN_TDAL
-       .word   (0x5 & NS9750_MEM_DYN_TDAL_MA)
-
-       .word   NS9750_MEM_DYN_TWR
-       .word   (0x1 & NS9750_MEM_DYN_TWR_MA)
-
-       .word   NS9750_MEM_DYN_TRC
-       .word   (0x6 & NS9750_MEM_DYN_TRC_MA)
-
-       .word   NS9750_MEM_DYN_TRFC
-       .word   (0x6 & NS9750_MEM_DYN_TRFC_MA)
-
-       .word   NS9750_MEM_DYN_TRRD
-       .word   (0x1 & NS9750_MEM_DYN_TRRD_MA)
-
-       .word   NS9750_MEM_DYN_TMRD
-       .word   (0x1 & NS9750_MEM_DYN_TMRD_MA)
-
-       @@ CS 4
-       .word   NS9750_MEM_DYN_CFG(0)
-       .word   (NS9750_MEM_DYN_CFG_AM | \
-                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-       .word   NS9750_MEM_DYN_RAS_CAS(0)
-       .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
-                (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
-
-       @@ CS 5
-       .word   NS9750_MEM_DYN_CFG(1)
-       .word   (NS9750_MEM_DYN_CFG_AM | \
-                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-       .word   NS9750_MEM_DYN_RAS_CAS(1)
-       .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
-                (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
-
-       @@ CS 6
-       .word   NS9750_MEM_DYN_CFG(2)
-       .word   (NS9750_MEM_DYN_CFG_AM | \
-                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-       .word   NS9750_MEM_DYN_RAS_CAS(2)
-       .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
-                (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
-
-       @@ CS 7
-       .word   NS9750_MEM_DYN_CFG(3)
-       .word   (NS9750_MEM_DYN_CFG_AM | \
-                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-       .word   NS9750_MEM_DYN_RAS_CAS(3)
-       .word   ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
-                (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
-
-       .word   NS9750_MEM_DYN_CTRL
-       .word   (NS9750_MEM_DYN_CTRL_I_PALL | \
-                NS9750_MEM_DYN_CTRL_SR | \
-                NS9750_MEM_DYN_CTRL_CE )
-
-       .word   NS9750_MEM_DYN_REFRESH
-       .word   (0x1 & NS9750_MEM_DYN_REFRESH_MA)
-       @@ No further register settings after refresh
-_MEM_CONFIG_END:
-
-_MEM_MODE_START:
-       .word   NS9750_MEM_DYN_REFRESH
-       .word   (0x30 & NS9750_MEM_DYN_REFRESH_MA)
-
-       .word   NS9750_MEM_DYN_CTRL
-       .word   (NS9750_MEM_DYN_CTRL_I_MODE | \
-                NS9750_MEM_DYN_CTRL_SR | \
-                NS9750_MEM_DYN_CTRL_CE )
-_MEM_MODE_END:
-
-_MEM_ENABLE_START:
-       .word   NS9750_MEM_DYN_CTRL
-       .word   (NS9750_MEM_DYN_CTRL_I_NORMAL | \
-                NS9750_MEM_DYN_CTRL_SR | \
-                NS9750_MEM_DYN_CTRL_CE )
-
-       @@ CS 4
-       .word   NS9750_MEM_DYN_CFG(0)
-       .word   (NS9750_MEM_DYN_CFG_BDMC | \
-                NS9750_MEM_DYN_CFG_AM | \
-                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-       @@ CS 5
-       .word   NS9750_MEM_DYN_CFG(1)
-       .word   (NS9750_MEM_DYN_CFG_BDMC | \
-                NS9750_MEM_DYN_CFG_AM | \
-                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-       @@ CS 6
-       .word   NS9750_MEM_DYN_CFG(2)
-       .word   (NS9750_MEM_DYN_CFG_BDMC | \
-                NS9750_MEM_DYN_CFG_AM | \
-                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-
-       @@ CS 7
-       .word   NS9750_MEM_DYN_CFG(3)
-       .word   (NS9750_MEM_DYN_CFG_BDMC | \
-                NS9750_MEM_DYN_CFG_AM | \
-                (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
-_MEM_ENABLE_END:
-
-_AHB_MONITOR_START:
-       .word   NS9750_SYS_AHB_TIMEOUT
-       .word   0x01000100      @ @TODO not calculated yet
-
-       .word   NS9750_SYS_AHB_MON
-       .word   (NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \
-                NS9750_SYS_AHB_MON_BATC_GEN_IRQ)
-_AHB_MONITOR_END:
-
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
index bd6285cb2317b06a7c767dad4c99a905d6ab6f0d..902b24ea1acda603bb67e6267e805e072f2e5fdc 100644 (file)
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    = lib$(BOARD).a
 
 OBJS   := omap1510innovator.o
-SOBJS  := platform.o
+SOBJS  := lowlevel_init.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $^
diff --git a/board/omap1510inn/lowlevel_init.S b/board/omap1510inn/lowlevel_init.S
new file mode 100644 (file)
index 0000000..1c68e5b
--- /dev/null
@@ -0,0 +1,396 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * -- Some bits of code used from rrload's head_OMAP1510.s --
+ * Copyright (C) 2002 RidgeRun, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
+
+
+_TEXT_BASE:
+       .word   TEXT_BASE        /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+       /*
+        * Configure 1510 pins functions to match our board.
+        */
+       ldr     r0, REG_PULL_DWN_CTRL_0
+       ldr     r1, VAL_PULL_DWN_CTRL_0
+       str     r1, [r0]
+       ldr     r0, REG_PULL_DWN_CTRL_1
+       ldr     r1, VAL_PULL_DWN_CTRL_1
+       str     r1, [r0]
+       ldr     r0, REG_PULL_DWN_CTRL_2
+       ldr     r1, VAL_PULL_DWN_CTRL_2
+       str     r1, [r0]
+       ldr     r0, REG_PULL_DWN_CTRL_3
+       ldr     r1, VAL_PULL_DWN_CTRL_3
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_4
+       ldr     r1, VAL_FUNC_MUX_CTRL_4
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_5
+       ldr     r1, VAL_FUNC_MUX_CTRL_5
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_6
+       ldr     r1, VAL_FUNC_MUX_CTRL_6
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_7
+       ldr     r1, VAL_FUNC_MUX_CTRL_7
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_8
+       ldr     r1, VAL_FUNC_MUX_CTRL_8
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_9
+       ldr     r1, VAL_FUNC_MUX_CTRL_9
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_A
+       ldr     r1, VAL_FUNC_MUX_CTRL_A
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_B
+       ldr     r1, VAL_FUNC_MUX_CTRL_B
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_C
+       ldr     r1, VAL_FUNC_MUX_CTRL_C
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_D
+       ldr     r1, VAL_FUNC_MUX_CTRL_D
+       str     r1, [r0]
+       ldr     r0, REG_VOLTAGE_CTRL_0
+       ldr     r1, VAL_VOLTAGE_CTRL_0
+       str     r1, [r0]
+       ldr     r0, REG_TEST_DBG_CTRL_0
+       ldr     r1, VAL_TEST_DBG_CTRL_0
+       str     r1, [r0]
+       ldr     r0, REG_MOD_CONF_CTRL_0
+       ldr     r1, VAL_MOD_CONF_CTRL_0
+       str     r1, [r0]
+
+       /* Move to 1510 mode */
+       ldr     r0, REG_COMP_MODE_CTRL_0
+       ldr     r1, VAL_COMP_MODE_CTRL_0
+       str     r1, [r0]
+
+       /* Set up Traffic Ctlr*/
+       ldr r0, REG_TC_IMIF_PRIO
+       mov r1, #0x0
+       str r1, [r0]
+       ldr r0, REG_TC_EMIFS_PRIO
+       str r1, [r0]
+       ldr r0, REG_TC_EMIFF_PRIO
+       str r1, [r0]
+
+       ldr r0, REG_TC_EMIFS_CONFIG
+       ldr r1, [r0]
+       bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
+       bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
+       str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
+
+       /* Setup some clock domains */
+       ldr r1, =OMAP1510_CLKS
+       ldr r0, REG_ARM_IDLECT2
+       strh r1, [r0]  /* CLKM, Clock domain control. */
+
+       mov r1, #0x01  /* PER_EN bit */
+       ldr r0, REG_ARM_RSTCT2
+       strh r1, [r0]  /* CLKM; Peripheral reset. */
+
+       /* Set CLKM to Sync-Scalable  */
+       /* I supposidly need to enable the dsp clock before switching */
+       mov r1, #0x1000
+       ldr r0, REG_ARM_SYSST
+       strh r1, [r0]
+       mov r0, #0x400
+1:
+       subs r0, r0, #0x1   /* wait for any bubbles to finish */
+       bne 1b
+
+       ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
+       ldr r0, REG_ARM_CKCTL
+       strh r1, [r0]
+
+       /* setup DPLL 1 */
+       ldr r1, VAL_DPLL1_CTL
+       ldr r0, REG_DPLL1_CTL
+       strh r1, [r0]
+       ands r1, r1, #0x10  /* Check if PLL is enabled. */
+       beq lock_end        /* Do not look for lock if BYPASS selected */
+2:
+       ldrh r1, [r0]
+       ands r1, r1, #0x01  /* Check the LOCK bit. */
+       beq 2b              /* ...loop until bit goes hi. */
+lock_end:
+
+       /* Set memory timings corresponding to the new clock speed */
+
+       /* Check execution location to determine current execution location
+        * and branch to appropriate initialization code.
+        */
+       mov r0, #0x10000000                 /* Load physical SDRAM base. */
+       mov r1, pc                          /* Get current execution location. */
+       /* Zero all but top 6 bits of PC, as they alone detect whether an
+        * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
+        * valid range for SDRAM on the OMAP 1510/5910.
+        */
+       and r1, r1, #0xfc000000
+       cmp r1, r0                      /* Compare. */
+       beq skip_sdram                  /* Skip over EMIF-fast initialization
+                                        * if running from SDRAM.
+                                        */
+
+       /*
+        * Delay for SDRAM initialization.
+        */
+       mov r3, #0x1800                        /* value should be checked */
+3:
+       subs r3, r3, #0x1                     /* Decrement count */
+       bne 3b
+
+       /*
+        * Set SDRAM control values. Disable refresh before MRS command.
+        */
+       ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
+       bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
+       orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
+       orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
+       ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+       str r3, [r2]                        /* Store the passed value with AR disabled. */
+
+       ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
+       ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
+       str r1, [r2]                        /* Store the passed value.*/
+
+       ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+       str r0, [r2]                        /* Store the passed value. */
+
+       /*
+        * Delay for SDRAM initialization.
+        */
+       mov r3, #0x1800
+4:
+       subs r3, r3, #1                     /* Decrement count. */
+       bne 4b
+
+skip_sdram:
+
+       /* slow interface */
+       ldr r1, VAL_TC_EMIFS_CS0_CONFIG
+       ldr r0, REG_TC_EMIFS_CS0_CONFIG
+       str r1, [r0] /* Chip Select 0 */
+       ldr r1, VAL_TC_EMIFS_CS1_CONFIG
+       ldr r0, REG_TC_EMIFS_CS1_CONFIG
+       str r1, [r0] /* Chip Select 1 */
+       ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+       ldr r0, REG_TC_EMIFS_CS2_CONFIG
+       str r1, [r0] /* Chip Select 2 */
+       ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+       ldr r0, REG_TC_EMIFS_CS3_CONFIG
+       str r1, [r0] /* Chip Select 3 */
+
+ /* Next, Enable the RS232 Line Drivers in the FPGA. */
+ /* Also, power on the audio CODEC's amplifier here, */
+ /* which will make a noise on the audio output. */
+ /* This is done here instead of in the kernel so there */
+ /* isn't a loud popping noise at the start of each */
+ /* song. */
+ /* Also, disable the CODEC's clocks. */
+ /* omap1510-HelenP1 [specific] */
+
+       ldr r0, REG_FPGA_POWER
+       mov r1, #0
+       ldr r2, REG_FPGA_DIP_SWITCH
+       ldrb r3, [r2]
+       cmp r3, #0x8
+       movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
+       strb r1, [r0]
+       ldr r0, REG_FPGA_AUDIO
+       mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
+       strb r1, [r0]
+
+       /* back to arch calling code */
+       mov     pc, lr
+
+/* the literal pools origin */
+       .ltorg
+
+/* OMAP configuration registers */
+REG_FUNC_MUX_CTRL_0:           /* 32 bits */
+       .word 0xfffe1000
+REG_FUNC_MUX_CTRL_1:           /* 32 bits */
+       .word 0xfffe1004
+REG_FUNC_MUX_CTRL_2:           /* 32 bits */
+       .word 0xfffe1008
+REG_COMP_MODE_CTRL_0:          /* 32 bits */
+       .word 0xfffe100c
+REG_FUNC_MUX_CTRL_3:           /* 32 bits */
+       .word 0xfffe1010
+REG_FUNC_MUX_CTRL_4:           /* 32 bits */
+       .word 0xfffe1014
+REG_FUNC_MUX_CTRL_5:           /* 32 bits */
+       .word 0xfffe1018
+REG_FUNC_MUX_CTRL_6:           /* 32 bits */
+       .word 0xfffe101c
+REG_FUNC_MUX_CTRL_7:           /* 32 bits */
+       .word 0xfffe1020
+REG_FUNC_MUX_CTRL_8:           /* 32 bits */
+       .word 0xfffe1024
+REG_FUNC_MUX_CTRL_9:           /* 32 bits */
+       .word 0xfffe1028
+REG_FUNC_MUX_CTRL_A:           /* 32 bits */
+       .word 0xfffe102C
+REG_FUNC_MUX_CTRL_B:           /* 32 bits */
+       .word 0xfffe1030
+REG_FUNC_MUX_CTRL_C:           /* 32 bits */
+       .word 0xfffe1034
+REG_FUNC_MUX_CTRL_D:           /* 32 bits */
+       .word 0xfffe1038
+REG_PULL_DWN_CTRL_0:           /* 32 bits */
+       .word 0xfffe1040
+REG_PULL_DWN_CTRL_1:           /* 32 bits */
+       .word 0xfffe1044
+REG_PULL_DWN_CTRL_2:           /* 32 bits */
+       .word 0xfffe1048
+REG_PULL_DWN_CTRL_3:           /* 32 bits */
+       .word 0xfffe104c
+REG_VOLTAGE_CTRL_0:            /* 32 bits */
+       .word 0xfffe1060
+REG_TEST_DBG_CTRL_0:           /* 32 bits */
+       .word 0xfffe1070
+REG_MOD_CONF_CTRL_0:           /* 32 bits */
+       .word 0xfffe1080
+REG_TC_IMIF_PRIO:              /* 32 bits */
+       .word 0xfffecc00
+REG_TC_EMIFS_PRIO:             /* 32 bits */
+       .word 0xfffecc04
+REG_TC_EMIFF_PRIO:             /* 32 bits */
+       .word 0xfffecc08
+REG_TC_EMIFS_CONFIG:           /* 32 bits */
+       .word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
+       .word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
+       .word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
+       .word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
+       .word 0xfffecc1c
+REG_TC_EMIFF_SDRAM_CONFIG:     /* 32 bits */
+       .word 0xfffecc20
+REG_TC_EMIFF_MRS:              /* 32 bits */
+       .word 0xfffecc24
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:                 /* 16 bits */
+       .word 0xfffece00
+REG_ARM_IDLECT2:               /* 16 bits */
+       .word 0xfffece08
+REG_ARM_RSTCT2:                        /* 16 bits */
+       .word 0xfffece14
+REG_ARM_SYSST:                 /* 16 bits */
+       .word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:                 /* 16 bits */
+       .word 0xfffecf00
+/* identification code register */
+REG_IDCODE:                    /* 32 bits */
+       .word 0xfffed404
+
+/* Innovator specific */
+REG_FPGA_LED_DIGIT:            /* 8 bits (not used on Innovator) */
+       .word 0x08000003
+REG_FPGA_POWER:                        /* 8 bits */
+       .word 0x08000005
+REG_FPGA_AUDIO:                        /* 8 bits (not used on Innovator) */
+       .word 0x0800000c
+REG_FPGA_DIP_SWITCH:           /* 8 bits (not used on Innovator) */
+       .word 0x0800000e
+
+VAL_COMP_MODE_CTRL_0:
+       .word 0x0000eaef
+VAL_FUNC_MUX_CTRL_4:
+       .word 0x00000000
+VAL_FUNC_MUX_CTRL_5:
+       .word 0x00000000
+VAL_FUNC_MUX_CTRL_6:
+       .word 0x00000001
+VAL_FUNC_MUX_CTRL_7:
+       .word 0x00000000
+VAL_FUNC_MUX_CTRL_8:
+       .word 0x10001200
+VAL_FUNC_MUX_CTRL_9:
+       .word 0x01201012
+VAL_FUNC_MUX_CTRL_A:
+       .word 0x00000248
+VAL_FUNC_MUX_CTRL_B:
+       .word 0x00000248
+VAL_FUNC_MUX_CTRL_C:
+       .word 0x09000000
+VAL_FUNC_MUX_CTRL_D:
+       .word 0x00000000
+VAL_PULL_DWN_CTRL_0:
+       .word 0x11a10000
+VAL_PULL_DWN_CTRL_1:
+       .word 0x2e047fff
+VAL_PULL_DWN_CTRL_2:
+       .word 0xffd603a6
+VAL_PULL_DWN_CTRL_3:
+       .word 0x00003e03
+VAL_VOLTAGE_CTRL_0:
+       .word 0x00000007
+VAL_TEST_DBG_CTRL_0:
+       /*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
+        *   This slows down internal SRAM accesses.
+        */
+       .word 0x00000007
+VAL_MOD_CONF_CTRL_0:
+       .word 0x0b000008
+VAL_ARM_CKCTL:
+       .word 0x010f
+VAL_DPLL1_CTL:
+       .word 0x2710
+VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
+       .word 0x00001149
+VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
+       .word 0x00004158
+VAL_TC_EMIFS_CS0_CONFIG:
+       .word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+       .word 0x0000f559
+VAL_TC_EMIFS_CS2_CONFIG:
+       .word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+       .word 0x00003331
+VAL_TC_EMIFF_SDRAM_CONFIG:
+       .word 0x010290fc
+VAL_TC_EMIFF_MRS:
+       .word 0x00000027
diff --git a/board/omap1510inn/platform.S b/board/omap1510inn/platform.S
deleted file mode 100644 (file)
index 8045e84..0000000
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- *
- * -- Some bits of code used from rrload's head_OMAP1510.s --
- * Copyright (C) 2002 RidgeRun, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1510)
-#include <./configs/omap1510.h>
-#endif
-
-#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
-
-
-_TEXT_BASE:
-       .word   TEXT_BASE        /* sdram load addr from config.mk */
-
-.globl platformsetup
-platformsetup:
-
-       /*
-        * Configure 1510 pins functions to match our board.
-        */
-       ldr     r0, REG_PULL_DWN_CTRL_0
-       ldr     r1, VAL_PULL_DWN_CTRL_0
-       str     r1, [r0]
-       ldr     r0, REG_PULL_DWN_CTRL_1
-       ldr     r1, VAL_PULL_DWN_CTRL_1
-       str     r1, [r0]
-       ldr     r0, REG_PULL_DWN_CTRL_2
-       ldr     r1, VAL_PULL_DWN_CTRL_2
-       str     r1, [r0]
-       ldr     r0, REG_PULL_DWN_CTRL_3
-       ldr     r1, VAL_PULL_DWN_CTRL_3
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_4
-       ldr     r1, VAL_FUNC_MUX_CTRL_4
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_5
-       ldr     r1, VAL_FUNC_MUX_CTRL_5
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_6
-       ldr     r1, VAL_FUNC_MUX_CTRL_6
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_7
-       ldr     r1, VAL_FUNC_MUX_CTRL_7
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_8
-       ldr     r1, VAL_FUNC_MUX_CTRL_8
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_9
-       ldr     r1, VAL_FUNC_MUX_CTRL_9
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_A
-       ldr     r1, VAL_FUNC_MUX_CTRL_A
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_B
-       ldr     r1, VAL_FUNC_MUX_CTRL_B
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_C
-       ldr     r1, VAL_FUNC_MUX_CTRL_C
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_D
-       ldr     r1, VAL_FUNC_MUX_CTRL_D
-       str     r1, [r0]
-       ldr     r0, REG_VOLTAGE_CTRL_0
-       ldr     r1, VAL_VOLTAGE_CTRL_0
-       str     r1, [r0]
-       ldr     r0, REG_TEST_DBG_CTRL_0
-       ldr     r1, VAL_TEST_DBG_CTRL_0
-       str     r1, [r0]
-       ldr     r0, REG_MOD_CONF_CTRL_0
-       ldr     r1, VAL_MOD_CONF_CTRL_0
-       str     r1, [r0]
-
-       /* Move to 1510 mode */
-       ldr     r0, REG_COMP_MODE_CTRL_0
-       ldr     r1, VAL_COMP_MODE_CTRL_0
-       str     r1, [r0]
-
-       /* Set up Traffic Ctlr*/
-       ldr r0, REG_TC_IMIF_PRIO
-       mov r1, #0x0
-       str r1, [r0]
-       ldr r0, REG_TC_EMIFS_PRIO
-       str r1, [r0]
-       ldr r0, REG_TC_EMIFF_PRIO
-       str r1, [r0]
-
-       ldr r0, REG_TC_EMIFS_CONFIG
-       ldr r1, [r0]
-       bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
-       bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
-       str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
-
-       /* Setup some clock domains */
-       ldr r1, =OMAP1510_CLKS
-       ldr r0, REG_ARM_IDLECT2
-       strh r1, [r0]  /* CLKM, Clock domain control. */
-
-       mov r1, #0x01  /* PER_EN bit */
-       ldr r0, REG_ARM_RSTCT2
-       strh r1, [r0]  /* CLKM; Peripheral reset. */
-
-       /* Set CLKM to Sync-Scalable  */
-       /* I supposidly need to enable the dsp clock before switching */
-       mov r1, #0x1000
-       ldr r0, REG_ARM_SYSST
-       strh r1, [r0]
-       mov r0, #0x400
-1:
-       subs r0, r0, #0x1   /* wait for any bubbles to finish */
-       bne 1b
-
-       ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
-       ldr r0, REG_ARM_CKCTL
-       strh r1, [r0]
-
-       /* setup DPLL 1 */
-       ldr r1, VAL_DPLL1_CTL
-       ldr r0, REG_DPLL1_CTL
-       strh r1, [r0]
-       ands r1, r1, #0x10  /* Check if PLL is enabled. */
-       beq lock_end        /* Do not look for lock if BYPASS selected */
-2:
-       ldrh r1, [r0]
-       ands r1, r1, #0x01  /* Check the LOCK bit. */
-       beq 2b              /* ...loop until bit goes hi. */
-lock_end:
-
-       /* Set memory timings corresponding to the new clock speed */
-
-       /* Check execution location to determine current execution location
-        * and branch to appropriate initialization code.
-        */
-       mov r0, #0x10000000                 /* Load physical SDRAM base. */
-       mov r1, pc                          /* Get current execution location. */
-       /* Zero all but top 6 bits of PC, as they alone detect whether an
-        * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
-        * valid range for SDRAM on the OMAP 1510/5910.
-        */
-       and r1, r1, #0xfc000000
-       cmp r1, r0                      /* Compare. */
-       beq skip_sdram                  /* Skip over EMIF-fast initialization
-                                        * if running from SDRAM.
-                                        */
-
-       /*
-        * Delay for SDRAM initialization.
-        */
-       mov r3, #0x1800                        /* value should be checked */
-3:
-       subs r3, r3, #0x1                     /* Decrement count */
-       bne 3b
-
-       /*
-        * Set SDRAM control values. Disable refresh before MRS command.
-        */
-       ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
-       bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
-       orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
-       orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
-       ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
-       str r3, [r2]                        /* Store the passed value with AR disabled. */
-
-       ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
-       ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
-       str r1, [r2]                        /* Store the passed value.*/
-
-       ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
-       str r0, [r2]                        /* Store the passed value. */
-
-       /*
-        * Delay for SDRAM initialization.
-        */
-       mov r3, #0x1800
-4:
-       subs r3, r3, #1                     /* Decrement count. */
-       bne 4b
-
-skip_sdram:
-
-       /* slow interface */
-       ldr r1, VAL_TC_EMIFS_CS0_CONFIG
-       ldr r0, REG_TC_EMIFS_CS0_CONFIG
-       str r1, [r0] /* Chip Select 0 */
-       ldr r1, VAL_TC_EMIFS_CS1_CONFIG
-       ldr r0, REG_TC_EMIFS_CS1_CONFIG
-       str r1, [r0] /* Chip Select 1 */
-       ldr r1, VAL_TC_EMIFS_CS2_CONFIG
-       ldr r0, REG_TC_EMIFS_CS2_CONFIG
-       str r1, [r0] /* Chip Select 2 */
-       ldr r1, VAL_TC_EMIFS_CS3_CONFIG
-       ldr r0, REG_TC_EMIFS_CS3_CONFIG
-       str r1, [r0] /* Chip Select 3 */
-
- /* Next, Enable the RS232 Line Drivers in the FPGA. */
- /* Also, power on the audio CODEC's amplifier here, */
- /* which will make a noise on the audio output. */
- /* This is done here instead of in the kernel so there */
- /* isn't a loud popping noise at the start of each */
- /* song. */
- /* Also, disable the CODEC's clocks. */
- /* omap1510-HelenP1 [specific] */
-
-       ldr r0, REG_FPGA_POWER
-       mov r1, #0
-       ldr r2, REG_FPGA_DIP_SWITCH
-       ldrb r3, [r2]
-       cmp r3, #0x8
-       movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
-       strb r1, [r0]
-       ldr r0, REG_FPGA_AUDIO
-       mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
-       strb r1, [r0]
-
-       /* back to arch calling code */
-       mov     pc, lr
-
-/* the literal pools origin */
-       .ltorg
-
-/* OMAP configuration registers */
-REG_FUNC_MUX_CTRL_0:           /* 32 bits */
-       .word 0xfffe1000
-REG_FUNC_MUX_CTRL_1:           /* 32 bits */
-       .word 0xfffe1004
-REG_FUNC_MUX_CTRL_2:           /* 32 bits */
-       .word 0xfffe1008
-REG_COMP_MODE_CTRL_0:          /* 32 bits */
-       .word 0xfffe100c
-REG_FUNC_MUX_CTRL_3:           /* 32 bits */
-       .word 0xfffe1010
-REG_FUNC_MUX_CTRL_4:           /* 32 bits */
-       .word 0xfffe1014
-REG_FUNC_MUX_CTRL_5:           /* 32 bits */
-       .word 0xfffe1018
-REG_FUNC_MUX_CTRL_6:           /* 32 bits */
-       .word 0xfffe101c
-REG_FUNC_MUX_CTRL_7:           /* 32 bits */
-       .word 0xfffe1020
-REG_FUNC_MUX_CTRL_8:           /* 32 bits */
-       .word 0xfffe1024
-REG_FUNC_MUX_CTRL_9:           /* 32 bits */
-       .word 0xfffe1028
-REG_FUNC_MUX_CTRL_A:           /* 32 bits */
-       .word 0xfffe102C
-REG_FUNC_MUX_CTRL_B:           /* 32 bits */
-       .word 0xfffe1030
-REG_FUNC_MUX_CTRL_C:           /* 32 bits */
-       .word 0xfffe1034
-REG_FUNC_MUX_CTRL_D:           /* 32 bits */
-       .word 0xfffe1038
-REG_PULL_DWN_CTRL_0:           /* 32 bits */
-       .word 0xfffe1040
-REG_PULL_DWN_CTRL_1:           /* 32 bits */
-       .word 0xfffe1044
-REG_PULL_DWN_CTRL_2:           /* 32 bits */
-       .word 0xfffe1048
-REG_PULL_DWN_CTRL_3:           /* 32 bits */
-       .word 0xfffe104c
-REG_VOLTAGE_CTRL_0:            /* 32 bits */
-       .word 0xfffe1060
-REG_TEST_DBG_CTRL_0:           /* 32 bits */
-       .word 0xfffe1070
-REG_MOD_CONF_CTRL_0:           /* 32 bits */
-       .word 0xfffe1080
-REG_TC_IMIF_PRIO:              /* 32 bits */
-       .word 0xfffecc00
-REG_TC_EMIFS_PRIO:             /* 32 bits */
-       .word 0xfffecc04
-REG_TC_EMIFF_PRIO:             /* 32 bits */
-       .word 0xfffecc08
-REG_TC_EMIFS_CONFIG:           /* 32 bits */
-       .word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
-       .word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
-       .word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
-       .word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
-       .word 0xfffecc1c
-REG_TC_EMIFF_SDRAM_CONFIG:     /* 32 bits */
-       .word 0xfffecc20
-REG_TC_EMIFF_MRS:              /* 32 bits */
-       .word 0xfffecc24
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL:                 /* 16 bits */
-       .word 0xfffece00
-REG_ARM_IDLECT2:               /* 16 bits */
-       .word 0xfffece08
-REG_ARM_RSTCT2:                        /* 16 bits */
-       .word 0xfffece14
-REG_ARM_SYSST:                 /* 16 bits */
-       .word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL:                 /* 16 bits */
-       .word 0xfffecf00
-/* identification code register */
-REG_IDCODE:                    /* 32 bits */
-       .word 0xfffed404
-
-/* Innovator specific */
-REG_FPGA_LED_DIGIT:            /* 8 bits (not used on Innovator) */
-       .word 0x08000003
-REG_FPGA_POWER:                        /* 8 bits */
-       .word 0x08000005
-REG_FPGA_AUDIO:                        /* 8 bits (not used on Innovator) */
-       .word 0x0800000c
-REG_FPGA_DIP_SWITCH:           /* 8 bits (not used on Innovator) */
-       .word 0x0800000e
-
-VAL_COMP_MODE_CTRL_0:
-       .word 0x0000eaef
-VAL_FUNC_MUX_CTRL_4:
-       .word 0x00000000
-VAL_FUNC_MUX_CTRL_5:
-       .word 0x00000000
-VAL_FUNC_MUX_CTRL_6:
-       .word 0x00000001
-VAL_FUNC_MUX_CTRL_7:
-       .word 0x00000000
-VAL_FUNC_MUX_CTRL_8:
-       .word 0x10001200
-VAL_FUNC_MUX_CTRL_9:
-       .word 0x01201012
-VAL_FUNC_MUX_CTRL_A:
-       .word 0x00000248
-VAL_FUNC_MUX_CTRL_B:
-       .word 0x00000248
-VAL_FUNC_MUX_CTRL_C:
-       .word 0x09000000
-VAL_FUNC_MUX_CTRL_D:
-       .word 0x00000000
-VAL_PULL_DWN_CTRL_0:
-       .word 0x11a10000
-VAL_PULL_DWN_CTRL_1:
-       .word 0x2e047fff
-VAL_PULL_DWN_CTRL_2:
-       .word 0xffd603a6
-VAL_PULL_DWN_CTRL_3:
-       .word 0x00003e03
-VAL_VOLTAGE_CTRL_0:
-       .word 0x00000007
-VAL_TEST_DBG_CTRL_0:
-       /*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
-        *   This slows down internal SRAM accesses.
-        */
-       .word 0x00000007
-VAL_MOD_CONF_CTRL_0:
-       .word 0x0b000008
-VAL_ARM_CKCTL:
-       .word 0x010f
-VAL_DPLL1_CTL:
-       .word 0x2710
-VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
-       .word 0x00001149
-VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
-       .word 0x00004158
-VAL_TC_EMIFS_CS0_CONFIG:
-       .word 0x002130b0
-VAL_TC_EMIFS_CS1_CONFIG:
-       .word 0x0000f559
-VAL_TC_EMIFS_CS2_CONFIG:
-       .word 0x000055f0
-VAL_TC_EMIFS_CS3_CONFIG:
-       .word 0x00003331
-VAL_TC_EMIFF_SDRAM_CONFIG:
-       .word 0x010290fc
-VAL_TC_EMIFF_MRS:
-       .word 0x00000027
index 4a96b8334be2fd0b57ceedae6d3d7356c9fbadda..4560102327e9d786d965bb0e8c2b4035c97c0aad 100644 (file)
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    = lib$(BOARD).a
 
 OBJS   := omap1610innovator.o flash.o
-SOBJS  := platform.o
+SOBJS  := lowlevel_init.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $^
diff --git a/board/omap1610inn/lowlevel_init.S b/board/omap1610inn/lowlevel_init.S
new file mode 100644 (file)
index 0000000..eaf1742
--- /dev/null
@@ -0,0 +1,452 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+       .word   TEXT_BASE       /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+
+       /*------------------------------------------------------*
+        *mask all IRQs by setting all bits in the INTMR default*
+        *------------------------------------------------------*/
+       mov     r1, #0xffffffff
+       ldr     r0, =REG_IHL1_MIR
+       str     r1, [r0]
+       ldr     r0, =REG_IHL2_MIR
+       str     r1, [r0]
+
+       /*------------------------------------------------------*
+        * Set up ARM CLM registers (IDLECT1)                   *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_ARM_IDLECT1
+       ldr     r1,     VAL_ARM_IDLECT1
+       str     r1,     [r0]
+
+       /*------------------------------------------------------*
+        * Set up ARM CLM registers (IDLECT2)                   *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_ARM_IDLECT2
+       ldr     r1,     VAL_ARM_IDLECT2
+       str     r1,     [r0]
+
+       /*------------------------------------------------------*
+        * Set up ARM CLM registers (IDLECT3)                   *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_ARM_IDLECT3
+       ldr     r1,     VAL_ARM_IDLECT3
+       str     r1,     [r0]
+
+#ifdef CONFIG_CS_AUTOBOOT              /* do the setup depending on boot mode */
+       ldr     r0, CONF_STATUS
+       ldr     r1, [r0]
+       tst     r1, #0x02
+       beq     disable_wd              /* booting from RAM, skip setup */
+#endif
+
+       mov     r1,     #0x01           /* PER_EN bit */
+       ldr     r0,     REG_ARM_RSTCT2
+       strh    r1,     [r0]            /* CLKM; Peripheral reset. */
+
+       /* Set CLKM to Sync-Scalable    */
+       /* I supposedly need to enable the dsp clock before switching */
+       mov     r1,     #0x0000
+       ldr     r0,     REG_ARM_SYSST
+       strh    r1,     [r0]
+       mov     r0,     #0x400
+1:
+       subs    r0,     r0,     #0x1    /* wait for any bubbles to finish */
+       bne     1b
+       ldr     r1,     VAL_ARM_CKCTL
+       ldr     r0,     REG_ARM_CKCTL
+       strh    r1,     [r0]
+
+       /* a few nops to let settle */
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+
+       /* setup DPLL 1 */
+       /* Ramp up the clock to 96Mhz */
+       ldr     r1,     VAL_DPLL1_CTL
+       ldr     r0,     REG_DPLL1_CTL
+       strh    r1,     [r0]
+       ands    r1,     r1,     #0x10   /* Check if PLL is enabled. */
+       beq     lock_end        /* Do not look for lock if BYPASS selected */
+2:
+       ldrh    r1,     [r0]
+       ands    r1,     r1,     #0x01   /*      Check the LOCK bit.*/
+       beq 2b                  /*      loop until bit goes hi. */
+lock_end:
+
+
+       /*------------------------------------------------------*
+        * Turn off the watchdog during init...                 *
+        *------------------------------------------------------*/
+disable_wd:
+       ldr     r0,     REG_WATCHDOG
+       ldr     r1,     WATCHDOG_VAL1
+       str     r1,     [r0]
+       ldr     r1,     WATCHDOG_VAL2
+       str     r1,     [r0]
+       ldr     r0,     REG_WSPRDOG
+       ldr     r1,     WSPRDOG_VAL1
+       str     r1,     [r0]
+       ldr     r0,     REG_WWPSDOG
+
+watch1Wait:
+       ldr     r1,     [r0]
+       tst     r1,     #0x10
+       bne     watch1Wait
+
+       ldr     r0,     REG_WSPRDOG
+       ldr     r1,     WSPRDOG_VAL2
+       str     r1,     [r0]
+       ldr     r0,     REG_WWPSDOG
+watch2Wait:
+       ldr     r1,     [r0]
+       tst     r1,     #0x10
+       bne     watch2Wait
+
+
+       /* Set memory timings corresponding to the new clock speed */
+
+       /* Check execution location to determine current execution location
+        * and branch to appropriate initialization code.
+        */
+       /* Load physical SDRAM base. */
+       mov     r0,     #0x10000000
+       /* Get current execution location. */
+       mov     r1,     pc
+       /* Compare. */
+       cmp     r1,     r0
+       /* Skip over EMIF-fast initialization if running from SDRAM. */
+       bge     skip_sdram
+
+       /*
+       * Delay for SDRAM initialization.
+       */
+       mov     r3,     #0x1800         /* value should be checked */
+3:
+       subs    r3,     r3,     #0x1    /* Decrement count */
+       bne     3b
+
+
+       /*
+        * Set SDRAM control values. Disable refresh before MRS command.
+        */
+
+       /* mobile ddr operation */
+       ldr     r0,     REG_SDRAM_OPERATION
+       mov     r2,     #07
+       str     r2,     [r0]
+
+       /* config register */
+       ldr     r0,     REG_SDRAM_CONFIG
+       ldr     r1,     SDRAM_CONFIG_VAL
+       str     r1,     [r0]
+
+       /* manual command register */
+       ldr     r0,     REG_SDRAM_MANUAL_CMD
+       /* issue set cke high */
+       mov     r1,     #CMD_SDRAM_CKE_SET_HIGH
+       str     r1,     [r0]
+       /* issue nop */
+       mov     r1,     #CMD_SDRAM_NOP
+       str     r1,     [r0]
+
+       mov     r2,     #0x0100
+waitMDDR1:
+       subs    r2,     r2,      #1
+       bne     waitMDDR1       /* delay loop */
+
+       /* issue precharge */
+       mov     r1,     #CMD_SDRAM_PRECHARGE
+       str     r1,     [r0]
+
+       /* issue autorefresh x 2 */
+       mov     r1,     #CMD_SDRAM_AUTOREFRESH
+       str     r1,     [r0]
+       str     r1,     [r0]
+
+       /* mrs register ddr mobile */
+       ldr     r0,     REG_SDRAM_MRS
+       mov     r1,     #0x33
+       str     r1,     [r0]
+
+       /* emrs1 low-power register */
+       ldr     r0,     REG_SDRAM_EMRS1
+       /* self refresh on all banks */
+       mov     r1,     #0
+       str     r1,     [r0]
+
+       ldr     r0,     REG_DLL_URD_CONTROL
+       ldr     r1,     DLL_URD_CONTROL_VAL
+       str     r1,     [r0]
+
+       ldr     r0,     REG_DLL_LRD_CONTROL
+       ldr     r1,     DLL_LRD_CONTROL_VAL
+       str     r1,     [r0]
+
+       ldr     r0,     REG_DLL_WRT_CONTROL
+       ldr     r1,     DLL_WRT_CONTROL_VAL
+       str     r1,     [r0]
+
+       /* delay loop */
+       mov     r2,     #0x0100
+waitMDDR2:
+       subs    r2,     r2,     #1
+       bne     waitMDDR2
+
+       /*
+        * Delay for SDRAM initialization.
+        */
+       mov     r3,     #0x1800
+4:
+       subs    r3,     r3,     #1      /* Decrement count. */
+       bne     4b
+       b       common_tc
+
+skip_sdram:
+
+       ldr     r0,     REG_SDRAM_CONFIG
+       ldr     r1,     SDRAM_CONFIG_VAL
+       str     r1,     [r0]
+
+common_tc:
+       /* slow interface */
+       ldr     r1,     VAL_TC_EMIFS_CS0_CONFIG
+       ldr     r0,     REG_TC_EMIFS_CS0_CONFIG
+       str     r1,     [r0] /* Chip Select 0 */
+
+       ldr     r1,     VAL_TC_EMIFS_CS1_CONFIG
+       ldr     r0,     REG_TC_EMIFS_CS1_CONFIG
+       str     r1,     [r0] /* Chip Select 1 */
+       ldr     r1,     VAL_TC_EMIFS_CS3_CONFIG
+       ldr     r0,     REG_TC_EMIFS_CS3_CONFIG
+       str     r1,     [r0] /* Chip Select 3 */
+
+#ifdef CONFIG_H2_OMAP1610
+       /* inserting additional 2 clock cycle hold time for LAN */
+       ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+       ldr     r1,     VAL_TC_EMIFS_CS1_ADVANCED
+       str     r1,     [r0]
+#endif
+       /* Start MPU Timer 1 */
+       ldr     r0,     REG_MPU_LOAD_TIMER
+       ldr     r1,     VAL_MPU_LOAD_TIMER
+       str     r1,     [r0]
+
+       ldr     r0,     REG_MPU_CNTL_TIMER
+       ldr     r1,     VAL_MPU_CNTL_TIMER
+       str     r1,     [r0]
+
+       /* back to arch calling code */
+       mov     pc,     lr
+
+       /* the literal pools origin */
+       .ltorg
+
+#ifdef CONFIG_CS_AUTOBOOT
+CONF_STATUS:
+       .word 0xfffe1130        /* 32 bits */
+#endif
+
+REG_TC_EMIFS_CONFIG:           /* 32 bits */
+       .word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
+       .word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
+       .word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
+       .word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
+       .word 0xfffecc1c
+
+#ifdef CONFIG_H2_OMAP1610
+REG_TC_EMIFS_CS1_ADVANCED:     /* 32 bits */
+       .word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:                 /* 16 bits */
+       .word 0xfffece00
+
+REG_ARM_IDLECT3:               /* 16 bits */
+       .word 0xfffece24
+REG_ARM_IDLECT2:               /* 16 bits */
+       .word 0xfffece08
+REG_ARM_IDLECT1:               /* 16 bits */
+       .word 0xfffece04
+
+REG_ARM_RSTCT2:                        /* 16 bits */
+       .word 0xfffece14
+REG_ARM_SYSST:                 /* 16 bits */
+       .word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:                 /* 16 bits */
+       .word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+       .word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+       .word 0xfffeb034
+
+WSPRDOG_VAL1:
+       .word 0x0000aaaa
+WSPRDOG_VAL2:
+       .word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+       .word 0xfffecc20
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+       .word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+       .word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+       .word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+       .word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+       .word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+       .word 0x03f00002
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+       .word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+       .word 0x00800002
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+       .word 0xfffecccc
+
+REG_WATCHDOG:
+       .word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+       .word 0xfffec600
+REG_MPU_CNTL_TIMER:
+       .word 0xfffec500
+
+/* 96 MHz Samsung Mobile DDR */
+SDRAM_CONFIG_VAL:
+       .word 0x001200f4
+
+DLL_LRD_CONTROL_VAL:
+       .word 0x00800002
+
+VAL_ARM_CKCTL:
+       .word 0x3000
+VAL_DPLL1_CTL:
+       .word 0x2830
+
+#ifdef CONFIG_INNOVATOROMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+       .word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+       .word 0x00001131
+VAL_TC_EMIFS_CS2_CONFIG:
+       .word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+       .word 0x88011131
+#endif
+
+#ifdef CONFIG_H2_OMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+       .word 0x00203331
+VAL_TC_EMIFS_CS1_CONFIG:
+       .word 0x8180fff3
+VAL_TC_EMIFS_CS2_CONFIG:
+       .word 0xf800f22a
+VAL_TC_EMIFS_CS3_CONFIG:
+       .word 0x88011131
+VAL_TC_EMIFS_CS1_ADVANCED:
+       .word 0x00000022
+#endif
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+       .word 0x010290fc
+VAL_TC_EMIFF_MRS:
+       .word 0x00000027
+
+VAL_ARM_IDLECT1:
+       .word 0x00000400
+
+VAL_ARM_IDLECT2:
+       .word 0x00000886
+VAL_ARM_IDLECT3:
+       .word 0x00000015
+
+WATCHDOG_VAL1:
+       .word 0x000000f5
+WATCHDOG_VAL2:
+       .word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+       .word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+       .word 0xffffffa1
+
+/* command values */
+.equ CMD_SDRAM_NOP,            0x00000000
+.equ CMD_SDRAM_PRECHARGE,      0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,    0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,   0x00000007
diff --git a/board/omap1610inn/platform.S b/board/omap1610inn/platform.S
deleted file mode 100644 (file)
index d694f94..0000000
+++ /dev/null
@@ -1,452 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#endif
-
-
-_TEXT_BASE:
-       .word   TEXT_BASE       /* sdram load addr from config.mk */
-
-.globl platformsetup
-platformsetup:
-
-
-       /*------------------------------------------------------*
-        *mask all IRQs by setting all bits in the INTMR default*
-        *------------------------------------------------------*/
-       mov     r1, #0xffffffff
-       ldr     r0, =REG_IHL1_MIR
-       str     r1, [r0]
-       ldr     r0, =REG_IHL2_MIR
-       str     r1, [r0]
-
-       /*------------------------------------------------------*
-        * Set up ARM CLM registers (IDLECT1)                   *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_ARM_IDLECT1
-       ldr     r1,     VAL_ARM_IDLECT1
-       str     r1,     [r0]
-
-       /*------------------------------------------------------*
-        * Set up ARM CLM registers (IDLECT2)                   *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_ARM_IDLECT2
-       ldr     r1,     VAL_ARM_IDLECT2
-       str     r1,     [r0]
-
-       /*------------------------------------------------------*
-        * Set up ARM CLM registers (IDLECT3)                   *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_ARM_IDLECT3
-       ldr     r1,     VAL_ARM_IDLECT3
-       str     r1,     [r0]
-
-#ifdef CONFIG_CS_AUTOBOOT              /* do the setup depending on boot mode */
-       ldr     r0, CONF_STATUS
-       ldr     r1, [r0]
-       tst     r1, #0x02
-       beq     disable_wd              /* booting from RAM, skip setup */
-#endif
-
-       mov     r1,     #0x01           /* PER_EN bit */
-       ldr     r0,     REG_ARM_RSTCT2
-       strh    r1,     [r0]            /* CLKM; Peripheral reset. */
-
-       /* Set CLKM to Sync-Scalable    */
-       /* I supposedly need to enable the dsp clock before switching */
-       mov     r1,     #0x0000
-       ldr     r0,     REG_ARM_SYSST
-       strh    r1,     [r0]
-       mov     r0,     #0x400
-1:
-       subs    r0,     r0,     #0x1    /* wait for any bubbles to finish */
-       bne     1b
-       ldr     r1,     VAL_ARM_CKCTL
-       ldr     r0,     REG_ARM_CKCTL
-       strh    r1,     [r0]
-
-       /* a few nops to let settle */
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-
-       /* setup DPLL 1 */
-       /* Ramp up the clock to 96Mhz */
-       ldr     r1,     VAL_DPLL1_CTL
-       ldr     r0,     REG_DPLL1_CTL
-       strh    r1,     [r0]
-       ands    r1,     r1,     #0x10   /* Check if PLL is enabled. */
-       beq     lock_end        /* Do not look for lock if BYPASS selected */
-2:
-       ldrh    r1,     [r0]
-       ands    r1,     r1,     #0x01   /*      Check the LOCK bit.*/
-       beq 2b                  /*      loop until bit goes hi. */
-lock_end:
-
-
-       /*------------------------------------------------------*
-        * Turn off the watchdog during init...                 *
-        *------------------------------------------------------*/
-disable_wd:
-       ldr     r0,     REG_WATCHDOG
-       ldr     r1,     WATCHDOG_VAL1
-       str     r1,     [r0]
-       ldr     r1,     WATCHDOG_VAL2
-       str     r1,     [r0]
-       ldr     r0,     REG_WSPRDOG
-       ldr     r1,     WSPRDOG_VAL1
-       str     r1,     [r0]
-       ldr     r0,     REG_WWPSDOG
-
-watch1Wait:
-       ldr     r1,     [r0]
-       tst     r1,     #0x10
-       bne     watch1Wait
-
-       ldr     r0,     REG_WSPRDOG
-       ldr     r1,     WSPRDOG_VAL2
-       str     r1,     [r0]
-       ldr     r0,     REG_WWPSDOG
-watch2Wait:
-       ldr     r1,     [r0]
-       tst     r1,     #0x10
-       bne     watch2Wait
-
-
-       /* Set memory timings corresponding to the new clock speed */
-
-       /* Check execution location to determine current execution location
-        * and branch to appropriate initialization code.
-        */
-       /* Load physical SDRAM base. */
-       mov     r0,     #0x10000000
-       /* Get current execution location. */
-       mov     r1,     pc
-       /* Compare. */
-       cmp     r1,     r0
-       /* Skip over EMIF-fast initialization if running from SDRAM. */
-       bge     skip_sdram
-
-       /*
-       * Delay for SDRAM initialization.
-       */
-       mov     r3,     #0x1800         /* value should be checked */
-3:
-       subs    r3,     r3,     #0x1    /* Decrement count */
-       bne     3b
-
-
-       /*
-        * Set SDRAM control values. Disable refresh before MRS command.
-        */
-
-       /* mobile ddr operation */
-       ldr     r0,     REG_SDRAM_OPERATION
-       mov     r2,     #07
-       str     r2,     [r0]
-
-       /* config register */
-       ldr     r0,     REG_SDRAM_CONFIG
-       ldr     r1,     SDRAM_CONFIG_VAL
-       str     r1,     [r0]
-
-       /* manual command register */
-       ldr     r0,     REG_SDRAM_MANUAL_CMD
-       /* issue set cke high */
-       mov     r1,     #CMD_SDRAM_CKE_SET_HIGH
-       str     r1,     [r0]
-       /* issue nop */
-       mov     r1,     #CMD_SDRAM_NOP
-       str     r1,     [r0]
-
-       mov     r2,     #0x0100
-waitMDDR1:
-       subs    r2,     r2,      #1
-       bne     waitMDDR1       /* delay loop */
-
-       /* issue precharge */
-       mov     r1,     #CMD_SDRAM_PRECHARGE
-       str     r1,     [r0]
-
-       /* issue autorefresh x 2 */
-       mov     r1,     #CMD_SDRAM_AUTOREFRESH
-       str     r1,     [r0]
-       str     r1,     [r0]
-
-       /* mrs register ddr mobile */
-       ldr     r0,     REG_SDRAM_MRS
-       mov     r1,     #0x33
-       str     r1,     [r0]
-
-       /* emrs1 low-power register */
-       ldr     r0,     REG_SDRAM_EMRS1
-       /* self refresh on all banks */
-       mov     r1,     #0
-       str     r1,     [r0]
-
-       ldr     r0,     REG_DLL_URD_CONTROL
-       ldr     r1,     DLL_URD_CONTROL_VAL
-       str     r1,     [r0]
-
-       ldr     r0,     REG_DLL_LRD_CONTROL
-       ldr     r1,     DLL_LRD_CONTROL_VAL
-       str     r1,     [r0]
-
-       ldr     r0,     REG_DLL_WRT_CONTROL
-       ldr     r1,     DLL_WRT_CONTROL_VAL
-       str     r1,     [r0]
-
-       /* delay loop */
-       mov     r2,     #0x0100
-waitMDDR2:
-       subs    r2,     r2,     #1
-       bne     waitMDDR2
-
-       /*
-        * Delay for SDRAM initialization.
-        */
-       mov     r3,     #0x1800
-4:
-       subs    r3,     r3,     #1      /* Decrement count. */
-       bne     4b
-       b       common_tc
-
-skip_sdram:
-
-       ldr     r0,     REG_SDRAM_CONFIG
-       ldr     r1,     SDRAM_CONFIG_VAL
-       str     r1,     [r0]
-
-common_tc:
-       /* slow interface */
-       ldr     r1,     VAL_TC_EMIFS_CS0_CONFIG
-       ldr     r0,     REG_TC_EMIFS_CS0_CONFIG
-       str     r1,     [r0] /* Chip Select 0 */
-
-       ldr     r1,     VAL_TC_EMIFS_CS1_CONFIG
-       ldr     r0,     REG_TC_EMIFS_CS1_CONFIG
-       str     r1,     [r0] /* Chip Select 1 */
-       ldr     r1,     VAL_TC_EMIFS_CS3_CONFIG
-       ldr     r0,     REG_TC_EMIFS_CS3_CONFIG
-       str     r1,     [r0] /* Chip Select 3 */
-
-#ifdef CONFIG_H2_OMAP1610
-       /* inserting additional 2 clock cycle hold time for LAN */
-       ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
-       ldr     r1,     VAL_TC_EMIFS_CS1_ADVANCED
-       str     r1,     [r0]
-#endif
-       /* Start MPU Timer 1 */
-       ldr     r0,     REG_MPU_LOAD_TIMER
-       ldr     r1,     VAL_MPU_LOAD_TIMER
-       str     r1,     [r0]
-
-       ldr     r0,     REG_MPU_CNTL_TIMER
-       ldr     r1,     VAL_MPU_CNTL_TIMER
-       str     r1,     [r0]
-
-       /* back to arch calling code */
-       mov     pc,     lr
-
-       /* the literal pools origin */
-       .ltorg
-
-#ifdef CONFIG_CS_AUTOBOOT
-CONF_STATUS:
-       .word 0xfffe1130        /* 32 bits */
-#endif
-
-REG_TC_EMIFS_CONFIG:           /* 32 bits */
-       .word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
-       .word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
-       .word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
-       .word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
-       .word 0xfffecc1c
-
-#ifdef CONFIG_H2_OMAP1610
-REG_TC_EMIFS_CS1_ADVANCED:     /* 32 bits */
-       .word 0xfffecc54
-#endif
-
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL:                 /* 16 bits */
-       .word 0xfffece00
-
-REG_ARM_IDLECT3:               /* 16 bits */
-       .word 0xfffece24
-REG_ARM_IDLECT2:               /* 16 bits */
-       .word 0xfffece08
-REG_ARM_IDLECT1:               /* 16 bits */
-       .word 0xfffece04
-
-REG_ARM_RSTCT2:                        /* 16 bits */
-       .word 0xfffece14
-REG_ARM_SYSST:                 /* 16 bits */
-       .word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL:                 /* 16 bits */
-       .word 0xfffecf00
-
-/* Watch Dog register */
-/* secure watchdog stop */
-REG_WSPRDOG:
-       .word 0xfffeb048
-/* watchdog write pending */
-REG_WWPSDOG:
-       .word 0xfffeb034
-
-WSPRDOG_VAL1:
-       .word 0x0000aaaa
-WSPRDOG_VAL2:
-       .word 0x00005555
-
-/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
- counter @8192 rows, 10 ns, 8 burst */
-REG_SDRAM_CONFIG:
-       .word 0xfffecc20
-
-/* Operation register */
-REG_SDRAM_OPERATION:
-       .word 0xfffecc80
-
-/* Manual command register */
-REG_SDRAM_MANUAL_CMD:
-       .word 0xfffecc84
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_MRS:
-       .word 0xfffecc70
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_EMRS1:
-       .word 0xfffecc78
-
-/* WRT DLL register */
-REG_DLL_WRT_CONTROL:
-       .word 0xfffecc68
-DLL_WRT_CONTROL_VAL:
-       .word 0x03f00002
-
-/* URD DLL register */
-REG_DLL_URD_CONTROL:
-       .word 0xfffeccc0
-DLL_URD_CONTROL_VAL:
-       .word 0x00800002
-
-/* LRD DLL register */
-REG_DLL_LRD_CONTROL:
-       .word 0xfffecccc
-
-REG_WATCHDOG:
-       .word 0xfffec808
-
-REG_MPU_LOAD_TIMER:
-       .word 0xfffec600
-REG_MPU_CNTL_TIMER:
-       .word 0xfffec500
-
-/* 96 MHz Samsung Mobile DDR */
-SDRAM_CONFIG_VAL:
-       .word 0x001200f4
-
-DLL_LRD_CONTROL_VAL:
-       .word 0x00800002
-
-VAL_ARM_CKCTL:
-       .word 0x3000
-VAL_DPLL1_CTL:
-       .word 0x2830
-
-#ifdef CONFIG_INNOVATOROMAP1610
-VAL_TC_EMIFS_CS0_CONFIG:
-       .word 0x002130b0
-VAL_TC_EMIFS_CS1_CONFIG:
-       .word 0x00001131
-VAL_TC_EMIFS_CS2_CONFIG:
-       .word 0x000055f0
-VAL_TC_EMIFS_CS3_CONFIG:
-       .word 0x88011131
-#endif
-
-#ifdef CONFIG_H2_OMAP1610
-VAL_TC_EMIFS_CS0_CONFIG:
-       .word 0x00203331
-VAL_TC_EMIFS_CS1_CONFIG:
-       .word 0x8180fff3
-VAL_TC_EMIFS_CS2_CONFIG:
-       .word 0xf800f22a
-VAL_TC_EMIFS_CS3_CONFIG:
-       .word 0x88011131
-VAL_TC_EMIFS_CS1_ADVANCED:
-       .word 0x00000022
-#endif
-
-VAL_TC_EMIFF_SDRAM_CONFIG:
-       .word 0x010290fc
-VAL_TC_EMIFF_MRS:
-       .word 0x00000027
-
-VAL_ARM_IDLECT1:
-       .word 0x00000400
-
-VAL_ARM_IDLECT2:
-       .word 0x00000886
-VAL_ARM_IDLECT3:
-       .word 0x00000015
-
-WATCHDOG_VAL1:
-       .word 0x000000f5
-WATCHDOG_VAL2:
-       .word 0x000000a0
-
-VAL_MPU_LOAD_TIMER:
-       .word 0xffffffff
-VAL_MPU_CNTL_TIMER:
-       .word 0xffffffa1
-
-/* command values */
-.equ CMD_SDRAM_NOP,            0x00000000
-.equ CMD_SDRAM_PRECHARGE,      0x00000001
-.equ CMD_SDRAM_AUTOREFRESH,    0x00000002
-.equ CMD_SDRAM_CKE_SET_HIGH,   0x00000007
index 38dec00d367673e6be4decde7423f450a0e69270..ed4786879a1cc96f6c271512654c3fdba3a466f8 100644 (file)
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    = lib$(BOARD).a
 
 OBJS   := omap2420h4.o mem.o sys_info.o
-SOBJS  := platform.o
+SOBJS  := lowlevel_init.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $^
diff --git a/board/omap2420h4/lowlevel_init.S b/board/omap2420h4/lowlevel_init.S
new file mode 100644 (file)
index 0000000..9752fc4
--- /dev/null
@@ -0,0 +1,185 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+       .word   TEXT_BASE       /* sdram load addr from config.mk */
+
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+       /* Copy DPLL code into SRAM */
+       adr     r0, go_to_speed         /* get addr of clock setting code */
+       mov     r2, #384                /* r2 size to copy (div by 32 bytes) */
+       mov     r1, r1                  /* r1 <- dest address (passed in) */
+       add     r2, r2, r0              /* r2 <- source end address */
+next2:
+       ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
+       stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
+       cmp     r0, r2                  /* until source end address [r2]    */
+       bne     next2
+       mov     pc, lr                  /* back to caller */
+
+/* ****************************************************************************
+ *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ *              -executed from SRAM.
+ *  R0 = PRCM_CLKCFG_CTRL - addr of valid reg
+ *  R1 = CM_CLKEN_PLL - addr dpll ctlr reg
+ *  R2 = dpll value
+ *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+       sub     sp, sp, #0x4 /* get some stack space */
+       str     r4, [sp]     /* save r4's value */
+
+       /* move into fast relock bypass */
+       ldr     r8, pll_ctl_add
+       mov     r4, #0x2
+       str     r4, [r8]
+       ldr     r4, pll_stat
+block:
+       ldr     r8, [r4]        /* wait for bypass to take effect */
+       and     r8, r8, #0x3
+       cmp     r8, #0x1
+       bne     block
+
+       /* set new dpll dividers _after_ in bypass */
+       ldr     r4, pll_div_add
+       ldr     r8, pll_div_val
+       str     r8, [r4]
+
+       /* now prepare GPMC (flash) for new dpll speed */
+       /* flash needs to be stable when we jump back to it */
+       ldr     r4, cfg3_0_addr
+       ldr     r8, cfg3_0_val
+       str     r8, [r4]
+       ldr     r4, cfg4_0_addr
+       ldr     r8, cfg4_0_val
+       str     r8, [r4]
+       ldr     r4, cfg1_0_addr
+       ldr     r8, [r4]
+       orr     r8, r8, #0x3     /* up gpmc divider */
+       str     r8, [r4]
+
+       /* setup to 2x loop though code.  The first loop pre-loads the
+        * icache, the 2nd commits the prcm config, and locks the dpll
+        */
+       mov     r4, #0x1000      /* spin spin spin */
+       mov     r8, #0x4         /* first pass condition & set registers */
+       cmp     r8, #0x4
+2:
+       ldrne   r8, [r3]         /* DPLL lock check */
+       and     r8, r8, #0x7
+       cmp     r8, #0x2
+       beq     4f
+3:
+       subeq   r8, r8, #0x1
+       streq   r8, [r0]         /* commit dividers (2nd time) */
+       nop
+lloop1:
+       sub     r4, r4, #0x1    /* Loop currently necessary else bad jumps */
+       nop
+       cmp     r4, #0x0
+       bne     lloop1
+       mov     r4, #0x40000
+       cmp     r8, #0x1
+       nop
+       streq   r2, [r1]        /* lock dpll (2nd time) */
+       nop
+lloop2:
+       sub     r4, r4, #0x1    /* loop currently necessary else bad jumps */
+       nop
+       cmp     r4, #0x0
+       bne     lloop2
+       mov     r4, #0x40000
+       cmp     r8, #0x1
+       nop
+       ldreq   r8, [r3]         /* get lock condition for dpll */
+       cmp     r8, #0x4         /* first time though? */
+       bne     2b
+       moveq   r8, #0x2         /* set to dpll check condition. */
+       beq     3b               /* if condition not true branch */
+4:
+       ldr     r4, [sp]
+       add     sp, sp, #0x4     /* return stack space */
+       mov     pc, lr           /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+cfg3_0_addr:
+    .word  GPMC_CONFIG3_0
+cfg3_0_val:
+    .word  H4_24XX_GPMC_CONFIG3_0
+cfg4_0_addr:
+    .word  GPMC_CONFIG4_0
+cfg4_0_val:
+    .word  H4_24XX_GPMC_CONFIG4_0
+cfg1_0_addr:
+    .word  GPMC_CONFIG1_0
+pll_ctl_add:
+    .word CM_CLKEN_PLL
+pll_stat:
+    .word CM_IDLEST_CKGEN
+pll_div_add:
+    .word CM_CLKSEL1_PLL
+pll_div_val:
+    .word DPLL_VAL     /* DPLL setting (300MHz default) */
+
+.globl lowlevel_init
+lowlevel_init:
+       ldr     sp,     SRAM_STACK
+       str     ip,     [sp]    /* stash old link register */
+       mov     ip,     lr      /* save link reg across call */
+       bl      s_init          /* go setup pll,mux,memory */
+       ldr     ip,     [sp]    /* restore save ip */
+       mov     lr,     ip      /* restore link reg */
+
+       /* map interrupt controller */
+       ldr     r0,     VAL_INTH_SETUP
+       mcr     p15, 0, r0, c15, c2, 4
+
+       /* back to arch calling code */
+       mov     pc,     lr
+
+       /* the literal pools origin */
+       .ltorg
+
+REG_CONTROL_STATUS:
+       .word CONTROL_STATUS
+VAL_INTH_SETUP:
+       .word PERIFERAL_PORT_BASE
+SRAM_STACK:
+       .word LOW_LEVEL_SRAM_STACK
diff --git a/board/omap2420h4/platform.S b/board/omap2420h4/platform.S
deleted file mode 100644 (file)
index 73ba462..0000000
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
-       .word   TEXT_BASE       /* sdram load addr from config.mk */
-
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
-       /* Copy DPLL code into SRAM */
-       adr     r0, go_to_speed         /* get addr of clock setting code */
-       mov     r2, #384                /* r2 size to copy (div by 32 bytes) */
-       mov     r1, r1                  /* r1 <- dest address (passed in) */
-       add     r2, r2, r0              /* r2 <- source end address */
-next2:
-       ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
-       stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       bne     next2
-       mov     pc, lr                  /* back to caller */
-
-/* ****************************************************************************
- *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- *              -executed from SRAM.
- *  R0 = PRCM_CLKCFG_CTRL - addr of valid reg
- *  R1 = CM_CLKEN_PLL - addr dpll ctlr reg
- *  R2 = dpll value
- *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
-       sub     sp, sp, #0x4 /* get some stack space */
-       str     r4, [sp]     /* save r4's value */
-
-       /* move into fast relock bypass */
-       ldr     r8, pll_ctl_add
-       mov     r4, #0x2
-       str     r4, [r8]
-       ldr     r4, pll_stat
-block:
-       ldr     r8, [r4]        /* wait for bypass to take effect */
-       and     r8, r8, #0x3
-       cmp     r8, #0x1
-       bne     block
-
-       /* set new dpll dividers _after_ in bypass */
-       ldr     r4, pll_div_add
-       ldr     r8, pll_div_val
-       str     r8, [r4]
-
-       /* now prepare GPMC (flash) for new dpll speed */
-       /* flash needs to be stable when we jump back to it */
-       ldr     r4, cfg3_0_addr
-       ldr     r8, cfg3_0_val
-       str     r8, [r4]
-       ldr     r4, cfg4_0_addr
-       ldr     r8, cfg4_0_val
-       str     r8, [r4]
-       ldr     r4, cfg1_0_addr
-       ldr     r8, [r4]
-       orr     r8, r8, #0x3     /* up gpmc divider */
-       str     r8, [r4]
-
-       /* setup to 2x loop though code.  The first loop pre-loads the
-        * icache, the 2nd commits the prcm config, and locks the dpll
-        */
-       mov     r4, #0x1000      /* spin spin spin */
-       mov     r8, #0x4         /* first pass condition & set registers */
-       cmp     r8, #0x4
-2:
-       ldrne   r8, [r3]         /* DPLL lock check */
-       and     r8, r8, #0x7
-       cmp     r8, #0x2
-       beq     4f
-3:
-       subeq   r8, r8, #0x1
-       streq   r8, [r0]         /* commit dividers (2nd time) */
-       nop
-lloop1:
-       sub     r4, r4, #0x1    /* Loop currently necessary else bad jumps */
-       nop
-       cmp     r4, #0x0
-       bne     lloop1
-       mov     r4, #0x40000
-       cmp     r8, #0x1
-       nop
-       streq   r2, [r1]        /* lock dpll (2nd time) */
-       nop
-lloop2:
-       sub     r4, r4, #0x1    /* loop currently necessary else bad jumps */
-       nop
-       cmp     r4, #0x0
-       bne     lloop2
-       mov     r4, #0x40000
-       cmp     r8, #0x1
-       nop
-       ldreq   r8, [r3]         /* get lock condition for dpll */
-       cmp     r8, #0x4         /* first time though? */
-       bne     2b
-       moveq   r8, #0x2         /* set to dpll check condition. */
-       beq     3b               /* if condition not true branch */
-4:
-       ldr     r4, [sp]
-       add     sp, sp, #0x4     /* return stack space */
-       mov     pc, lr           /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-cfg3_0_addr:
-    .word  GPMC_CONFIG3_0
-cfg3_0_val:
-    .word  H4_24XX_GPMC_CONFIG3_0
-cfg4_0_addr:
-    .word  GPMC_CONFIG4_0
-cfg4_0_val:
-    .word  H4_24XX_GPMC_CONFIG4_0
-cfg1_0_addr:
-    .word  GPMC_CONFIG1_0
-pll_ctl_add:
-    .word CM_CLKEN_PLL
-pll_stat:
-    .word CM_IDLEST_CKGEN
-pll_div_add:
-    .word CM_CLKSEL1_PLL
-pll_div_val:
-    .word DPLL_VAL     /* DPLL setting (300MHz default) */
-
-.globl platformsetup
-platformsetup:
-       ldr     sp,     SRAM_STACK
-       str     ip,     [sp]    /* stash old link register */
-       mov     ip,     lr      /* save link reg across call */
-       bl      s_init          /* go setup pll,mux,memory */
-       ldr     ip,     [sp]    /* restore save ip */
-       mov     lr,     ip      /* restore link reg */
-
-       /* map interrupt controller */
-       ldr     r0,     VAL_INTH_SETUP
-       mcr     p15, 0, r0, c15, c2, 4
-
-       /* back to arch calling code */
-       mov     pc,     lr
-
-       /* the literal pools origin */
-       .ltorg
-
-REG_CONTROL_STATUS:
-       .word CONTROL_STATUS
-VAL_INTH_SETUP:
-       .word PERIFERAL_PORT_BASE
-SRAM_STACK:
-       .word LOW_LEVEL_SRAM_STACK
index 64804663a96ba9e8f661116ad69cb73d8aefc1b5..4b564217b74799bc8c332a30122e08189c02ecee 100644 (file)
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    = lib$(BOARD).a
 
 OBJS   := omap5912osk.o
-SOBJS  := platform.o
+SOBJS  := lowlevel_init.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $^
diff --git a/board/omap5912osk/lowlevel_init.S b/board/omap5912osk/lowlevel_init.S
new file mode 100644 (file)
index 0000000..3b9633a
--- /dev/null
@@ -0,0 +1,442 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+       .word   TEXT_BASE       /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+
+       /*------------------------------------------------------*
+        *mask all IRQs by setting all bits in the INTMR default*
+        *------------------------------------------------------*/
+       mov     r1, #0xffffffff
+       ldr     r0, =REG_IHL1_MIR
+       str     r1, [r0]
+       ldr     r0, =REG_IHL2_MIR
+       str     r1, [r0]
+
+       /*------------------------------------------------------*
+        * Set up ARM CLM registers (IDLECT1)                   *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_ARM_IDLECT1
+       ldr     r1,     VAL_ARM_IDLECT1
+       str     r1,     [r0]
+
+       /*------------------------------------------------------*
+        * Set up ARM CLM registers (IDLECT2)                   *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_ARM_IDLECT2
+       ldr     r1,     VAL_ARM_IDLECT2
+       str     r1,     [r0]
+
+       /*------------------------------------------------------*
+        * Set up ARM CLM registers (IDLECT3)                   *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_ARM_IDLECT3
+       ldr     r1,     VAL_ARM_IDLECT3
+       str     r1,     [r0]
+
+
+       mov     r1,     #0x01           /* PER_EN bit */
+       ldr     r0,     REG_ARM_RSTCT2
+       strh    r1,     [r0]            /* CLKM; Peripheral reset. */
+
+       /* Set CLKM to Sync-Scalable    */
+       /* I supposedly need to enable the dsp clock before switching */
+       mov     r1,     #0x0000
+       ldr     r0,     REG_ARM_SYSST
+       strh    r1,     [r0]
+       mov     r0,     #0x400
+1:
+       subs    r0,     r0,     #0x1    /* wait for any bubbles to finish */
+       bne     1b
+       ldr     r1,     VAL_ARM_CKCTL
+       ldr     r0,     REG_ARM_CKCTL
+       strh    r1,     [r0]
+
+       /* a few nops to let settle */
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+
+       /* setup DPLL 1 */
+       /* Ramp up the clock to 96Mhz */
+       ldr     r1,     VAL_DPLL1_CTL
+       ldr     r0,     REG_DPLL1_CTL
+       strh    r1,     [r0]
+       ands    r1,     r1,     #0x10   /* Check if PLL is enabled. */
+       beq     lock_end        /* Do not look for lock if BYPASS selected */
+2:
+       ldrh    r1,     [r0]
+       ands    r1,     r1,     #0x01   /*      Check the LOCK bit.*/
+       beq 2b                  /*      loop until bit goes hi. */
+lock_end:
+
+
+       /*------------------------------------------------------*
+        * Turn off the watchdog during init...                 *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_WATCHDOG
+       ldr     r1,     WATCHDOG_VAL1
+       str     r1,     [r0]
+       ldr     r1,     WATCHDOG_VAL2
+       str     r1,     [r0]
+       ldr     r0,     REG_WSPRDOG
+       ldr     r1,     WSPRDOG_VAL1
+       str     r1,     [r0]
+       ldr     r0,     REG_WWPSDOG
+
+watch1Wait:
+       ldr     r1,     [r0]
+       tst     r1,     #0x10
+       bne     watch1Wait
+
+       ldr     r0,     REG_WSPRDOG
+       ldr     r1,     WSPRDOG_VAL2
+       str     r1,     [r0]
+       ldr     r0,     REG_WWPSDOG
+watch2Wait:
+       ldr     r1,     [r0]
+       tst     r1,     #0x10
+       bne     watch2Wait
+
+
+       /* Set memory timings corresponding to the new clock speed */
+
+       /* Check execution location to determine current execution location
+        * and branch to appropriate initialization code.
+        */
+       /* Load physical SDRAM base. */
+       mov     r0,     #0x10000000
+       /* Get current execution location. */
+       mov     r1,     pc
+       /* Compare. */
+       cmp     r1,     r0
+       /* Skip over EMIF-fast initialization if running from SDRAM. */
+       bge     skip_sdram
+
+       /*
+       * Delay for SDRAM initialization.
+       */
+       mov     r3,     #0x1800         /* value should be checked */
+3:
+       subs    r3,     r3,     #0x1    /* Decrement count */
+       bne     3b
+
+
+       /*
+        * Set SDRAM control values. Disable refresh before MRS command.
+        */
+
+       /* mobile ddr operation */
+       ldr     r0,     REG_SDRAM_OPERATION
+       mov     r2,     #07
+       str     r2,     [r0]
+
+       /* config register */
+       ldr     r0,     REG_SDRAM_CONFIG
+       ldr     r1,     SDRAM_CONFIG_VAL
+       str     r1,     [r0]
+
+       /* manual command register */
+       ldr     r0,     REG_SDRAM_MANUAL_CMD
+       /* issue set cke high */
+       mov     r1,     #CMD_SDRAM_CKE_SET_HIGH
+       str     r1,     [r0]
+       /* issue nop */
+       mov     r1,     #CMD_SDRAM_NOP
+       str     r1,     [r0]
+
+       mov     r2,     #0x0100
+waitMDDR1:
+       subs    r2,     r2,      #1
+       bne     waitMDDR1       /* delay loop */
+
+       /* issue precharge */
+       mov     r1,     #CMD_SDRAM_PRECHARGE
+       str     r1,     [r0]
+
+       /* issue autorefresh x 2 */
+       mov     r1,     #CMD_SDRAM_AUTOREFRESH
+       str     r1,     [r0]
+       str     r1,     [r0]
+
+       /* mrs register ddr mobile */
+       ldr     r0,     REG_SDRAM_MRS
+       mov     r1,     #0x33
+       str     r1,     [r0]
+
+       /* emrs1 low-power register */
+       ldr     r0,     REG_SDRAM_EMRS1
+       /* self refresh on all banks */
+       mov     r1,     #0
+       str     r1,     [r0]
+
+       ldr     r0,     REG_DLL_URD_CONTROL
+       ldr     r1,     DLL_URD_CONTROL_VAL
+       str     r1,     [r0]
+
+       ldr     r0,     REG_DLL_LRD_CONTROL
+       ldr     r1,     DLL_LRD_CONTROL_VAL
+       str     r1,     [r0]
+
+       ldr     r0,     REG_DLL_WRT_CONTROL
+       ldr     r1,     DLL_WRT_CONTROL_VAL
+       str     r1,     [r0]
+
+       /* delay loop */
+       mov     r2,     #0x0100
+waitMDDR2:
+       subs    r2,     r2,     #1
+       bne     waitMDDR2
+
+       /*
+        * Delay for SDRAM initialization.
+        */
+       mov     r3,     #0x1800
+4:
+       subs    r3,     r3,     #1      /* Decrement count. */
+       bne     4b
+       b       common_tc
+
+skip_sdram:
+
+       ldr     r0,     REG_SDRAM_CONFIG
+       ldr     r1,     SDRAM_CONFIG_VAL
+       str     r1,     [r0]
+
+common_tc:
+       /* slow interface */
+       ldr     r1,     VAL_TC_EMIFS_CS0_CONFIG
+       ldr     r0,     REG_TC_EMIFS_CS0_CONFIG
+       str     r1,     [r0] /* Chip Select 0 */
+
+       ldr     r1,     VAL_TC_EMIFS_CS1_CONFIG
+       ldr     r0,     REG_TC_EMIFS_CS1_CONFIG
+       str     r1,     [r0] /* Chip Select 1 */
+       ldr     r1,     VAL_TC_EMIFS_CS3_CONFIG
+       ldr     r0,     REG_TC_EMIFS_CS3_CONFIG
+       str     r1,     [r0] /* Chip Select 3 */
+
+#ifdef CONFIG_H2_OMAP1610
+       /* inserting additional 2 clock cycle hold time for LAN */
+       ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+       ldr     r1,     VAL_TC_EMIFS_CS1_ADVANCED
+       str     r1,     [r0]
+#endif
+       /* Start MPU Timer 1 */
+       ldr     r0,     REG_MPU_LOAD_TIMER
+       ldr     r1,     VAL_MPU_LOAD_TIMER
+       str     r1,     [r0]
+
+       ldr     r0,     REG_MPU_CNTL_TIMER
+       ldr     r1,     VAL_MPU_CNTL_TIMER
+       str     r1,     [r0]
+
+       /* back to arch calling code */
+       mov     pc,     lr
+
+       /* the literal pools origin */
+       .ltorg
+
+
+REG_TC_EMIFS_CONFIG:           /* 32 bits */
+       .word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
+       .word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
+       .word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
+       .word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
+       .word 0xfffecc1c
+
+#ifdef CONFIG_H2_OMAP1610
+REG_TC_EMIFS_CS1_ADVANCED:     /* 32 bits */
+       .word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:                 /* 16 bits */
+       .word 0xfffece00
+
+REG_ARM_IDLECT3:               /* 16 bits */
+       .word 0xfffece24
+REG_ARM_IDLECT2:               /* 16 bits */
+       .word 0xfffece08
+REG_ARM_IDLECT1:               /* 16 bits */
+       .word 0xfffece04
+
+REG_ARM_RSTCT2:                        /* 16 bits */
+       .word 0xfffece14
+REG_ARM_SYSST:                 /* 16 bits */
+       .word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:                 /* 16 bits */
+       .word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+       .word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+       .word 0xfffeb034
+
+WSPRDOG_VAL1:
+       .word 0x0000aaaa
+WSPRDOG_VAL2:
+       .word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+       .word 0xfffecc20
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+       .word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+       .word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+       .word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+       .word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+       .word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+       .word 0x03f00002
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+       .word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+       .word 0x00800002
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+       .word 0xfffecccc
+
+REG_WATCHDOG:
+       .word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+       .word 0xfffec600
+REG_MPU_CNTL_TIMER:
+       .word 0xfffec500
+
+/* 96 MHz Samsung Mobile DDR */
+SDRAM_CONFIG_VAL:
+       .word 0x001200f4
+
+DLL_LRD_CONTROL_VAL:
+       .word 0x00800002
+
+VAL_ARM_CKCTL:
+       .word 0x3000
+VAL_DPLL1_CTL:
+       .word 0x2830
+
+#ifdef CONFIG_OSK_OMAP5912
+VAL_TC_EMIFS_CS0_CONFIG:
+       .word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+       .word 0x00001131
+VAL_TC_EMIFS_CS2_CONFIG:
+       .word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+       .word 0x88011131
+#endif
+
+#ifdef CONFIG_H2_OMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+       .word 0x00203331
+VAL_TC_EMIFS_CS1_CONFIG:
+       .word 0x8180fff3
+VAL_TC_EMIFS_CS2_CONFIG:
+       .word 0xf800f22a
+VAL_TC_EMIFS_CS3_CONFIG:
+       .word 0x88011131
+VAL_TC_EMIFS_CS1_ADVANCED:
+       .word 0x00000022
+#endif
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+       .word 0x010290fc
+VAL_TC_EMIFF_MRS:
+       .word 0x00000027
+
+VAL_ARM_IDLECT1:
+       .word 0x00000400
+
+VAL_ARM_IDLECT2:
+       .word 0x00000886
+VAL_ARM_IDLECT3:
+       .word 0x00000015
+
+WATCHDOG_VAL1:
+       .word 0x000000f5
+WATCHDOG_VAL2:
+       .word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+       .word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+       .word 0xffffffa1
+
+/* command values */
+.equ CMD_SDRAM_NOP,            0x00000000
+.equ CMD_SDRAM_PRECHARGE,      0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,    0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,   0x00000007
diff --git a/board/omap5912osk/platform.S b/board/omap5912osk/platform.S
deleted file mode 100644 (file)
index 33c7242..0000000
+++ /dev/null
@@ -1,442 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#endif
-
-
-_TEXT_BASE:
-       .word   TEXT_BASE       /* sdram load addr from config.mk */
-
-.globl platformsetup
-platformsetup:
-
-
-       /*------------------------------------------------------*
-        *mask all IRQs by setting all bits in the INTMR default*
-        *------------------------------------------------------*/
-       mov     r1, #0xffffffff
-       ldr     r0, =REG_IHL1_MIR
-       str     r1, [r0]
-       ldr     r0, =REG_IHL2_MIR
-       str     r1, [r0]
-
-       /*------------------------------------------------------*
-        * Set up ARM CLM registers (IDLECT1)                   *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_ARM_IDLECT1
-       ldr     r1,     VAL_ARM_IDLECT1
-       str     r1,     [r0]
-
-       /*------------------------------------------------------*
-        * Set up ARM CLM registers (IDLECT2)                   *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_ARM_IDLECT2
-       ldr     r1,     VAL_ARM_IDLECT2
-       str     r1,     [r0]
-
-       /*------------------------------------------------------*
-        * Set up ARM CLM registers (IDLECT3)                   *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_ARM_IDLECT3
-       ldr     r1,     VAL_ARM_IDLECT3
-       str     r1,     [r0]
-
-
-       mov     r1,     #0x01           /* PER_EN bit */
-       ldr     r0,     REG_ARM_RSTCT2
-       strh    r1,     [r0]            /* CLKM; Peripheral reset. */
-
-       /* Set CLKM to Sync-Scalable    */
-       /* I supposedly need to enable the dsp clock before switching */
-       mov     r1,     #0x0000
-       ldr     r0,     REG_ARM_SYSST
-       strh    r1,     [r0]
-       mov     r0,     #0x400
-1:
-       subs    r0,     r0,     #0x1    /* wait for any bubbles to finish */
-       bne     1b
-       ldr     r1,     VAL_ARM_CKCTL
-       ldr     r0,     REG_ARM_CKCTL
-       strh    r1,     [r0]
-
-       /* a few nops to let settle */
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-
-       /* setup DPLL 1 */
-       /* Ramp up the clock to 96Mhz */
-       ldr     r1,     VAL_DPLL1_CTL
-       ldr     r0,     REG_DPLL1_CTL
-       strh    r1,     [r0]
-       ands    r1,     r1,     #0x10   /* Check if PLL is enabled. */
-       beq     lock_end        /* Do not look for lock if BYPASS selected */
-2:
-       ldrh    r1,     [r0]
-       ands    r1,     r1,     #0x01   /*      Check the LOCK bit.*/
-       beq 2b                  /*      loop until bit goes hi. */
-lock_end:
-
-
-       /*------------------------------------------------------*
-        * Turn off the watchdog during init...                 *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_WATCHDOG
-       ldr     r1,     WATCHDOG_VAL1
-       str     r1,     [r0]
-       ldr     r1,     WATCHDOG_VAL2
-       str     r1,     [r0]
-       ldr     r0,     REG_WSPRDOG
-       ldr     r1,     WSPRDOG_VAL1
-       str     r1,     [r0]
-       ldr     r0,     REG_WWPSDOG
-
-watch1Wait:
-       ldr     r1,     [r0]
-       tst     r1,     #0x10
-       bne     watch1Wait
-
-       ldr     r0,     REG_WSPRDOG
-       ldr     r1,     WSPRDOG_VAL2
-       str     r1,     [r0]
-       ldr     r0,     REG_WWPSDOG
-watch2Wait:
-       ldr     r1,     [r0]
-       tst     r1,     #0x10
-       bne     watch2Wait
-
-
-       /* Set memory timings corresponding to the new clock speed */
-
-       /* Check execution location to determine current execution location
-        * and branch to appropriate initialization code.
-        */
-       /* Load physical SDRAM base. */
-       mov     r0,     #0x10000000
-       /* Get current execution location. */
-       mov     r1,     pc
-       /* Compare. */
-       cmp     r1,     r0
-       /* Skip over EMIF-fast initialization if running from SDRAM. */
-       bge     skip_sdram
-
-       /*
-       * Delay for SDRAM initialization.
-       */
-       mov     r3,     #0x1800         /* value should be checked */
-3:
-       subs    r3,     r3,     #0x1    /* Decrement count */
-       bne     3b
-
-
-       /*
-        * Set SDRAM control values. Disable refresh before MRS command.
-        */
-
-       /* mobile ddr operation */
-       ldr     r0,     REG_SDRAM_OPERATION
-       mov     r2,     #07
-       str     r2,     [r0]
-
-       /* config register */
-       ldr     r0,     REG_SDRAM_CONFIG
-       ldr     r1,     SDRAM_CONFIG_VAL
-       str     r1,     [r0]
-
-       /* manual command register */
-       ldr     r0,     REG_SDRAM_MANUAL_CMD
-       /* issue set cke high */
-       mov     r1,     #CMD_SDRAM_CKE_SET_HIGH
-       str     r1,     [r0]
-       /* issue nop */
-       mov     r1,     #CMD_SDRAM_NOP
-       str     r1,     [r0]
-
-       mov     r2,     #0x0100
-waitMDDR1:
-       subs    r2,     r2,      #1
-       bne     waitMDDR1       /* delay loop */
-
-       /* issue precharge */
-       mov     r1,     #CMD_SDRAM_PRECHARGE
-       str     r1,     [r0]
-
-       /* issue autorefresh x 2 */
-       mov     r1,     #CMD_SDRAM_AUTOREFRESH
-       str     r1,     [r0]
-       str     r1,     [r0]
-
-       /* mrs register ddr mobile */
-       ldr     r0,     REG_SDRAM_MRS
-       mov     r1,     #0x33
-       str     r1,     [r0]
-
-       /* emrs1 low-power register */
-       ldr     r0,     REG_SDRAM_EMRS1
-       /* self refresh on all banks */
-       mov     r1,     #0
-       str     r1,     [r0]
-
-       ldr     r0,     REG_DLL_URD_CONTROL
-       ldr     r1,     DLL_URD_CONTROL_VAL
-       str     r1,     [r0]
-
-       ldr     r0,     REG_DLL_LRD_CONTROL
-       ldr     r1,     DLL_LRD_CONTROL_VAL
-       str     r1,     [r0]
-
-       ldr     r0,     REG_DLL_WRT_CONTROL
-       ldr     r1,     DLL_WRT_CONTROL_VAL
-       str     r1,     [r0]
-
-       /* delay loop */
-       mov     r2,     #0x0100
-waitMDDR2:
-       subs    r2,     r2,     #1
-       bne     waitMDDR2
-
-       /*
-        * Delay for SDRAM initialization.
-        */
-       mov     r3,     #0x1800
-4:
-       subs    r3,     r3,     #1      /* Decrement count. */
-       bne     4b
-       b       common_tc
-
-skip_sdram:
-
-       ldr     r0,     REG_SDRAM_CONFIG
-       ldr     r1,     SDRAM_CONFIG_VAL
-       str     r1,     [r0]
-
-common_tc:
-       /* slow interface */
-       ldr     r1,     VAL_TC_EMIFS_CS0_CONFIG
-       ldr     r0,     REG_TC_EMIFS_CS0_CONFIG
-       str     r1,     [r0] /* Chip Select 0 */
-
-       ldr     r1,     VAL_TC_EMIFS_CS1_CONFIG
-       ldr     r0,     REG_TC_EMIFS_CS1_CONFIG
-       str     r1,     [r0] /* Chip Select 1 */
-       ldr     r1,     VAL_TC_EMIFS_CS3_CONFIG
-       ldr     r0,     REG_TC_EMIFS_CS3_CONFIG
-       str     r1,     [r0] /* Chip Select 3 */
-
-#ifdef CONFIG_H2_OMAP1610
-       /* inserting additional 2 clock cycle hold time for LAN */
-       ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
-       ldr     r1,     VAL_TC_EMIFS_CS1_ADVANCED
-       str     r1,     [r0]
-#endif
-       /* Start MPU Timer 1 */
-       ldr     r0,     REG_MPU_LOAD_TIMER
-       ldr     r1,     VAL_MPU_LOAD_TIMER
-       str     r1,     [r0]
-
-       ldr     r0,     REG_MPU_CNTL_TIMER
-       ldr     r1,     VAL_MPU_CNTL_TIMER
-       str     r1,     [r0]
-
-       /* back to arch calling code */
-       mov     pc,     lr
-
-       /* the literal pools origin */
-       .ltorg
-
-
-REG_TC_EMIFS_CONFIG:           /* 32 bits */
-       .word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
-       .word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
-       .word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
-       .word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
-       .word 0xfffecc1c
-
-#ifdef CONFIG_H2_OMAP1610
-REG_TC_EMIFS_CS1_ADVANCED:     /* 32 bits */
-       .word 0xfffecc54
-#endif
-
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL:                 /* 16 bits */
-       .word 0xfffece00
-
-REG_ARM_IDLECT3:               /* 16 bits */
-       .word 0xfffece24
-REG_ARM_IDLECT2:               /* 16 bits */
-       .word 0xfffece08
-REG_ARM_IDLECT1:               /* 16 bits */
-       .word 0xfffece04
-
-REG_ARM_RSTCT2:                        /* 16 bits */
-       .word 0xfffece14
-REG_ARM_SYSST:                 /* 16 bits */
-       .word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL:                 /* 16 bits */
-       .word 0xfffecf00
-
-/* Watch Dog register */
-/* secure watchdog stop */
-REG_WSPRDOG:
-       .word 0xfffeb048
-/* watchdog write pending */
-REG_WWPSDOG:
-       .word 0xfffeb034
-
-WSPRDOG_VAL1:
-       .word 0x0000aaaa
-WSPRDOG_VAL2:
-       .word 0x00005555
-
-/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
- counter @8192 rows, 10 ns, 8 burst */
-REG_SDRAM_CONFIG:
-       .word 0xfffecc20
-
-/* Operation register */
-REG_SDRAM_OPERATION:
-       .word 0xfffecc80
-
-/* Manual command register */
-REG_SDRAM_MANUAL_CMD:
-       .word 0xfffecc84
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_MRS:
-       .word 0xfffecc70
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_EMRS1:
-       .word 0xfffecc78
-
-/* WRT DLL register */
-REG_DLL_WRT_CONTROL:
-       .word 0xfffecc68
-DLL_WRT_CONTROL_VAL:
-       .word 0x03f00002
-
-/* URD DLL register */
-REG_DLL_URD_CONTROL:
-       .word 0xfffeccc0
-DLL_URD_CONTROL_VAL:
-       .word 0x00800002
-
-/* LRD DLL register */
-REG_DLL_LRD_CONTROL:
-       .word 0xfffecccc
-
-REG_WATCHDOG:
-       .word 0xfffec808
-
-REG_MPU_LOAD_TIMER:
-       .word 0xfffec600
-REG_MPU_CNTL_TIMER:
-       .word 0xfffec500
-
-/* 96 MHz Samsung Mobile DDR */
-SDRAM_CONFIG_VAL:
-       .word 0x001200f4
-
-DLL_LRD_CONTROL_VAL:
-       .word 0x00800002
-
-VAL_ARM_CKCTL:
-       .word 0x3000
-VAL_DPLL1_CTL:
-       .word 0x2830
-
-#ifdef CONFIG_OSK_OMAP5912
-VAL_TC_EMIFS_CS0_CONFIG:
-       .word 0x002130b0
-VAL_TC_EMIFS_CS1_CONFIG:
-       .word 0x00001131
-VAL_TC_EMIFS_CS2_CONFIG:
-       .word 0x000055f0
-VAL_TC_EMIFS_CS3_CONFIG:
-       .word 0x88011131
-#endif
-
-#ifdef CONFIG_H2_OMAP1610
-VAL_TC_EMIFS_CS0_CONFIG:
-       .word 0x00203331
-VAL_TC_EMIFS_CS1_CONFIG:
-       .word 0x8180fff3
-VAL_TC_EMIFS_CS2_CONFIG:
-       .word 0xf800f22a
-VAL_TC_EMIFS_CS3_CONFIG:
-       .word 0x88011131
-VAL_TC_EMIFS_CS1_ADVANCED:
-       .word 0x00000022
-#endif
-
-VAL_TC_EMIFF_SDRAM_CONFIG:
-       .word 0x010290fc
-VAL_TC_EMIFF_MRS:
-       .word 0x00000027
-
-VAL_ARM_IDLECT1:
-       .word 0x00000400
-
-VAL_ARM_IDLECT2:
-       .word 0x00000886
-VAL_ARM_IDLECT3:
-       .word 0x00000015
-
-WATCHDOG_VAL1:
-       .word 0x000000f5
-WATCHDOG_VAL2:
-       .word 0x000000a0
-
-VAL_MPU_LOAD_TIMER:
-       .word 0xffffffff
-VAL_MPU_CNTL_TIMER:
-       .word 0xffffffa1
-
-/* command values */
-.equ CMD_SDRAM_NOP,            0x00000000
-.equ CMD_SDRAM_PRECHARGE,      0x00000001
-.equ CMD_SDRAM_AUTOREFRESH,    0x00000002
-.equ CMD_SDRAM_CKE_SET_HIGH,   0x00000007
index 10585080739caeaf1a625a04bd725fc3e068caff..29467ac39e6426de19a855f14118f869141f591d 100644 (file)
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    = lib$(BOARD).a
 
 OBJS   := omap730p2.o flash.o
-SOBJS  := platform.o
+SOBJS  := lowlevel_init.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $^
diff --git a/board/omap730p2/lowlevel_init.S b/board/omap730p2/lowlevel_init.S
new file mode 100644 (file)
index 0000000..6c6f482
--- /dev/null
@@ -0,0 +1,395 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003-2004
+ *
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
+ * (http://www.mpc-data.co.uk)
+ *
+ * TODO : Tidy up and change to use system register defines
+ *        from omap730.h where possible.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+_TEXT_BASE:
+       .word   TEXT_BASE       /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+       /* Save callers address in r11 - r11 must never be modified */
+       mov r11, lr
+
+       /*------------------------------------------------------*
+        *mask all IRQs by setting all bits in the INTMR default*
+        *------------------------------------------------------*/
+       mov     r1,     #0xffffffff
+       ldr     r0,     =REG_IHL1_MIR
+       str     r1,     [r0]
+       ldr     r0,     =REG_IHL2_MIR
+       str     r1,     [r0]
+
+       /*------------------------------------------------------*
+        * Set up ARM CLM registers (IDLECT1)                   *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_ARM_IDLECT1
+       ldr     r1,     VAL_ARM_IDLECT1
+       str     r1,     [r0]
+
+       /*------------------------------------------------------*
+        * Set up ARM CLM registers (IDLECT2)                   *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_ARM_IDLECT2
+       ldr     r1,     VAL_ARM_IDLECT2
+       str     r1,     [r0]
+
+       /*------------------------------------------------------*
+        * Set up ARM CLM registers (IDLECT3)                   *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_ARM_IDLECT3
+       ldr     r1,     VAL_ARM_IDLECT3
+       str     r1,     [r0]
+
+
+       mov     r1,     #0x01           /* PER_EN bit */
+       ldr     r0,     REG_ARM_RSTCT2
+       strh    r1,     [r0]            /* CLKM; Peripheral reset. */
+
+       /* Set CLKM to Sync-Scalable    */
+       /* I supposedly need to enable the dsp clock before switching */
+       mov     r1,     #0x1000
+       ldr     r0,     REG_ARM_SYSST
+       strh    r1,     [r0]
+       mov     r0,     #0x400
+1:
+       subs    r0,     r0,     #0x1    /* wait for any bubbles to finish */
+       bne     1b
+       ldr     r1,     VAL_ARM_CKCTL
+       ldr     r0,     REG_ARM_CKCTL
+       strh    r1,     [r0]
+
+       /* a few nops to let settle */
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+
+       /* setup DPLL 1 */
+       /* Ramp up the clock to 96Mhz */
+       ldr     r1,     VAL_DPLL1_CTL
+       ldr     r0,     REG_DPLL1_CTL
+       strh    r1,     [r0]
+       ands    r1,     r1,     #0x10   /* Check if PLL is enabled. */
+       beq     lock_end        /* Do not look for lock if BYPASS selected */
+2:
+       ldrh    r1,     [r0]
+       ands    r1,     r1,     #0x01   /*      Check the LOCK bit.*/
+       beq 2b                  /*      loop until bit goes hi. */
+lock_end:
+
+       /*------------------------------------------------------*
+        * Turn off the watchdog during init...                 *
+        *------------------------------------------------------*/
+       ldr     r0,     REG_WATCHDOG
+       ldr     r1,     WATCHDOG_VAL1
+       str     r1,     [r0]
+       ldr     r1,     WATCHDOG_VAL2
+       str     r1,     [r0]
+       ldr     r0,     REG_WSPRDOG
+       ldr     r1,     WSPRDOG_VAL1
+       str     r1,     [r0]
+       ldr     r0,     REG_WWPSDOG
+
+watch1Wait:
+       ldr     r1,     [r0]
+       tst     r1,     #0x10
+       bne     watch1Wait
+
+       ldr     r0,     REG_WSPRDOG
+       ldr     r1,     WSPRDOG_VAL2
+       str     r1,     [r0]
+       ldr     r0,     REG_WWPSDOG
+watch2Wait:
+       ldr     r1,     [r0]
+       tst     r1,     #0x10
+       bne     watch2Wait
+
+       /* Set memory timings corresponding to the new clock speed */
+
+       /* Check execution location to determine current execution location
+        * and branch to appropriate initialization code.
+        */
+       /* Compare physical SDRAM base & current execution location. */
+       and     r0, pc, #0xF0000000
+       /* Compare. */
+       cmp     r0, #0
+       /* Skip over EMIF-fast initialization if running from SDRAM. */
+       bne     skip_sdram
+
+       /*
+       * Delay for SDRAM initialization.
+       */
+       mov     r3,     #0x1800         /* value should be checked */
+3:
+       subs    r3,     r3,     #0x1    /* Decrement count */
+       bne     3b
+
+       ldr     r0,     REG_SDRAM_CONFIG
+       ldr     r1,     SDRAM_CONFIG_VAL
+       str     r1,     [r0]
+
+       ldr     r0,     REG_SDRAM_MRS_LEGACY
+       ldr     r1,     SDRAM_MRS_VAL
+       str     r1,     [r0]
+
+skip_sdram:
+
+common_tc:
+       /* slow interface */
+       ldr     r1,     VAL_TC_EMIFS_CS0_CONFIG
+       ldr     r0,     REG_TC_EMIFS_CS0_CONFIG
+       str     r1,     [r0] /* Chip Select 0 */
+
+       ldr     r1,     VAL_TC_EMIFS_CS1_CONFIG
+       ldr     r0,     REG_TC_EMIFS_CS1_CONFIG
+       str     r1,     [r0] /* Chip Select 1 */
+       ldr     r1,     VAL_TC_EMIFS_CS2_CONFIG
+       ldr     r0,     REG_TC_EMIFS_CS2_CONFIG
+       str     r1,     [r0] /* Chip Select 2 */
+       ldr     r1,     VAL_TC_EMIFS_CS3_CONFIG
+       ldr     r0,     REG_TC_EMIFS_CS3_CONFIG
+       str     r1,     [r0] /* Chip Select 3 */
+
+       /* 48MHz clock request for UART1 */
+       ldr     r1,     PERSEUS2_CONFIG_BASE
+       ldrh    r0,     [r1, #CONFIG_PCC_CONF]
+       orr     r0,     r0, #CONF_MOD_UART1_CLK_MODE_R
+       strh    r0,     [r1, #CONFIG_PCC_CONF]
+
+       /* Initialize public and private rheas
+        *  - set access factor 2 on both rhea / strobe
+        *  - disable write buffer on strb0, enable write buffer on strb1
+        */
+
+       ldr     R0,     REG_RHEA_PUB_CTL
+       ldr     R1,     REG_RHEA_PRIV_CTL
+       ldr     R2,     VAL_RHEA_CTL
+       strh    R2,     [R0]
+       strh    R2,     [R1]
+       mov     R3,     #2          /* disable write buffer on strb0, enable write buffer on strb1 */
+       strh    R3,     [R0, #0x08]     /* arm rhea control reg */
+       strh    R3,     [R1, #0x08]
+
+       /* enable IRQ and FIQ */
+
+       mrs     r4,     CPSR
+       bic     r4,     r4, #IRQ_MASK
+       bic     r4,     r4, #FIQ_MASK
+       msr     CPSR,   r4
+
+       /* set TAP CONF to TRI EMULATION */
+
+       ldr     r1,     [r0, #CONFIG_MODE2]
+       bic     r1,     r1, #0x18
+       orr     r1,     r1, #0x10
+       str     r1,     [r0, #CONFIG_MODE2]
+
+       /* set tdbgen to 1 */
+
+       ldr     r0,     PERSEUS2_CONFIG_BASE
+       ldr     r1,     [r0, #CONFIG_MODE1]
+       mov     r2,     #0x10000
+       orr     r1,     r1, r2
+       str     r1,     [r0, #CONFIG_MODE1]
+
+#ifdef CONFIG_P2_OMAP1610
+       /* inserting additional 2 clock cycle hold time for LAN */
+       ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+       ldr     r1,     VAL_TC_EMIFS_CS1_ADVANCED
+       str     r1,     [r0]
+#endif
+       /* Start MPU Timer 1 */
+       ldr     r0,     REG_MPU_LOAD_TIMER
+       ldr     r1,     VAL_MPU_LOAD_TIMER
+       str     r1,     [r0]
+
+       ldr     r0,     REG_MPU_CNTL_TIMER
+       ldr     r1,     VAL_MPU_CNTL_TIMER
+       str     r1,     [r0]
+
+       /* back to arch calling code */
+       mov     pc,     r11
+
+       /* the literal pools origin */
+       .ltorg
+
+REG_TC_EMIFS_CONFIG:           /* 32 bits */
+       .word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
+       .word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
+       .word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
+       .word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
+       .word 0xfffecc1c
+
+#ifdef CONFIG_P2_OMAP730
+REG_TC_EMIFS_CS1_ADVANCED:     /* 32 bits */
+       .word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:                 /* 16 bits */
+       .word 0xfffece00
+
+REG_ARM_IDLECT3:               /* 16 bits */
+       .word 0xfffece24
+REG_ARM_IDLECT2:               /* 16 bits */
+       .word 0xfffece08
+REG_ARM_IDLECT1:               /* 16 bits */
+       .word 0xfffece04
+
+REG_ARM_RSTCT2:                        /* 16 bits */
+       .word 0xfffece14
+REG_ARM_SYSST:                 /* 16 bits */
+       .word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:                 /* 16 bits */
+       .word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+       .word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+       .word 0xfffeb034
+
+WSPRDOG_VAL1:
+       .word 0x0000aaaa
+WSPRDOG_VAL2:
+       .word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+       .word 0xfffecc20
+
+REG_SDRAM_MRS_LEGACY:
+       .word 0xfffecc24
+
+REG_WATCHDOG:
+       .word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+       .word 0xfffec600
+REG_MPU_CNTL_TIMER:
+       .word 0xfffec500
+
+/* Public and private rhea bridge registers definition */
+
+REG_RHEA_PUB_CTL:
+       .word 0xFFFECA00
+
+REG_RHEA_PRIV_CTL:
+       .word 0xFFFED300
+
+/* EMIFF SDRAM Configuration register
+   - self refresh disable
+   - auto refresh enabled
+   - SDRAM type 64 Mb, 16 bits bus 4 banks
+   - power down enabled
+   - SDRAM clock disabled
+ */
+SDRAM_CONFIG_VAL:
+       .word 0x0C017DF4
+
+/* Burst full page length ; cas latency = 3 */
+SDRAM_MRS_VAL:
+       .word 0x00000037
+
+VAL_ARM_CKCTL:
+       .word 0x6505
+VAL_DPLL1_CTL:
+       .word 0x3412
+
+#ifdef CONFIG_P2_OMAP730
+VAL_TC_EMIFS_CS0_CONFIG:
+       .word 0x0000FFF3
+VAL_TC_EMIFS_CS1_CONFIG:
+       .word 0x00004278
+VAL_TC_EMIFS_CS2_CONFIG:
+       .word 0x00004278
+VAL_TC_EMIFS_CS3_CONFIG:
+       .word 0x00004278
+VAL_TC_EMIFS_CS1_ADVANCED:
+       .word 0x00000022
+#endif
+
+VAL_ARM_IDLECT1:
+       .word 0x00000400
+VAL_ARM_IDLECT2:
+       .word 0x00000886
+VAL_ARM_IDLECT3:
+       .word 0x00000015
+
+WATCHDOG_VAL1:
+       .word 0x000000f5
+WATCHDOG_VAL2:
+       .word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+       .word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+       .word 0xffffffa1
+
+VAL_RHEA_CTL:
+       .word                   0xFF22
+
+/* Config Register vals */
+PERSEUS2_CONFIG_BASE:
+       .word                   0xFFFE1000
+
+.equ   CONFIG_PCC_CONF,        0xB4
+.equ   CONFIG_MODE1,           0x10
+.equ   CONFIG_MODE2,           0x14
+.equ   CONF_MOD_UART1_CLK_MODE_R,      0x0A
+
+/* misc values */
+.equ   IRQ_MASK,               0x80           /* IRQ mask value */
+.equ   FIQ_MASK,               0x40           /* FIQ mask value */
diff --git a/board/omap730p2/platform.S b/board/omap730p2/platform.S
deleted file mode 100644 (file)
index f30c242..0000000
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003-2004
- *
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
- * (http://www.mpc-data.co.uk)
- *
- * TODO : Tidy up and change to use system register defines
- *        from omap730.h where possible.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP730)
-#include <./configs/omap730.h>
-#endif
-
-_TEXT_BASE:
-       .word   TEXT_BASE       /* sdram load addr from config.mk */
-
-.globl platformsetup
-platformsetup:
-       /* Save callers address in r11 - r11 must never be modified */
-       mov r11, lr
-
-       /*------------------------------------------------------*
-        *mask all IRQs by setting all bits in the INTMR default*
-        *------------------------------------------------------*/
-       mov     r1,     #0xffffffff
-       ldr     r0,     =REG_IHL1_MIR
-       str     r1,     [r0]
-       ldr     r0,     =REG_IHL2_MIR
-       str     r1,     [r0]
-
-       /*------------------------------------------------------*
-        * Set up ARM CLM registers (IDLECT1)                   *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_ARM_IDLECT1
-       ldr     r1,     VAL_ARM_IDLECT1
-       str     r1,     [r0]
-
-       /*------------------------------------------------------*
-        * Set up ARM CLM registers (IDLECT2)                   *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_ARM_IDLECT2
-       ldr     r1,     VAL_ARM_IDLECT2
-       str     r1,     [r0]
-
-       /*------------------------------------------------------*
-        * Set up ARM CLM registers (IDLECT3)                   *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_ARM_IDLECT3
-       ldr     r1,     VAL_ARM_IDLECT3
-       str     r1,     [r0]
-
-
-       mov     r1,     #0x01           /* PER_EN bit */
-       ldr     r0,     REG_ARM_RSTCT2
-       strh    r1,     [r0]            /* CLKM; Peripheral reset. */
-
-       /* Set CLKM to Sync-Scalable    */
-       /* I supposedly need to enable the dsp clock before switching */
-       mov     r1,     #0x1000
-       ldr     r0,     REG_ARM_SYSST
-       strh    r1,     [r0]
-       mov     r0,     #0x400
-1:
-       subs    r0,     r0,     #0x1    /* wait for any bubbles to finish */
-       bne     1b
-       ldr     r1,     VAL_ARM_CKCTL
-       ldr     r0,     REG_ARM_CKCTL
-       strh    r1,     [r0]
-
-       /* a few nops to let settle */
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-
-       /* setup DPLL 1 */
-       /* Ramp up the clock to 96Mhz */
-       ldr     r1,     VAL_DPLL1_CTL
-       ldr     r0,     REG_DPLL1_CTL
-       strh    r1,     [r0]
-       ands    r1,     r1,     #0x10   /* Check if PLL is enabled. */
-       beq     lock_end        /* Do not look for lock if BYPASS selected */
-2:
-       ldrh    r1,     [r0]
-       ands    r1,     r1,     #0x01   /*      Check the LOCK bit.*/
-       beq 2b                  /*      loop until bit goes hi. */
-lock_end:
-
-       /*------------------------------------------------------*
-        * Turn off the watchdog during init...                 *
-        *------------------------------------------------------*/
-       ldr     r0,     REG_WATCHDOG
-       ldr     r1,     WATCHDOG_VAL1
-       str     r1,     [r0]
-       ldr     r1,     WATCHDOG_VAL2
-       str     r1,     [r0]
-       ldr     r0,     REG_WSPRDOG
-       ldr     r1,     WSPRDOG_VAL1
-       str     r1,     [r0]
-       ldr     r0,     REG_WWPSDOG
-
-watch1Wait:
-       ldr     r1,     [r0]
-       tst     r1,     #0x10
-       bne     watch1Wait
-
-       ldr     r0,     REG_WSPRDOG
-       ldr     r1,     WSPRDOG_VAL2
-       str     r1,     [r0]
-       ldr     r0,     REG_WWPSDOG
-watch2Wait:
-       ldr     r1,     [r0]
-       tst     r1,     #0x10
-       bne     watch2Wait
-
-       /* Set memory timings corresponding to the new clock speed */
-
-       /* Check execution location to determine current execution location
-        * and branch to appropriate initialization code.
-        */
-       /* Compare physical SDRAM base & current execution location. */
-       and     r0, pc, #0xF0000000
-       /* Compare. */
-       cmp     r0, #0
-       /* Skip over EMIF-fast initialization if running from SDRAM. */
-       bne     skip_sdram
-
-       /*
-       * Delay for SDRAM initialization.
-       */
-       mov     r3,     #0x1800         /* value should be checked */
-3:
-       subs    r3,     r3,     #0x1    /* Decrement count */
-       bne     3b
-
-       ldr     r0,     REG_SDRAM_CONFIG
-       ldr     r1,     SDRAM_CONFIG_VAL
-       str     r1,     [r0]
-
-       ldr     r0,     REG_SDRAM_MRS_LEGACY
-       ldr     r1,     SDRAM_MRS_VAL
-       str     r1,     [r0]
-
-skip_sdram:
-
-common_tc:
-       /* slow interface */
-       ldr     r1,     VAL_TC_EMIFS_CS0_CONFIG
-       ldr     r0,     REG_TC_EMIFS_CS0_CONFIG
-       str     r1,     [r0] /* Chip Select 0 */
-
-       ldr     r1,     VAL_TC_EMIFS_CS1_CONFIG
-       ldr     r0,     REG_TC_EMIFS_CS1_CONFIG
-       str     r1,     [r0] /* Chip Select 1 */
-       ldr     r1,     VAL_TC_EMIFS_CS2_CONFIG
-       ldr     r0,     REG_TC_EMIFS_CS2_CONFIG
-       str     r1,     [r0] /* Chip Select 2 */
-       ldr     r1,     VAL_TC_EMIFS_CS3_CONFIG
-       ldr     r0,     REG_TC_EMIFS_CS3_CONFIG
-       str     r1,     [r0] /* Chip Select 3 */
-
-       /* 48MHz clock request for UART1 */
-       ldr     r1,     PERSEUS2_CONFIG_BASE
-       ldrh    r0,     [r1, #CONFIG_PCC_CONF]
-       orr     r0,     r0, #CONF_MOD_UART1_CLK_MODE_R
-       strh    r0,     [r1, #CONFIG_PCC_CONF]
-
-       /* Initialize public and private rheas
-        *  - set access factor 2 on both rhea / strobe
-        *  - disable write buffer on strb0, enable write buffer on strb1
-        */
-
-       ldr     R0,     REG_RHEA_PUB_CTL
-       ldr     R1,     REG_RHEA_PRIV_CTL
-       ldr     R2,     VAL_RHEA_CTL
-       strh    R2,     [R0]
-       strh    R2,     [R1]
-       mov     R3,     #2          /* disable write buffer on strb0, enable write buffer on strb1 */
-       strh    R3,     [R0, #0x08]     /* arm rhea control reg */
-       strh    R3,     [R1, #0x08]
-
-       /* enable IRQ and FIQ */
-
-       mrs     r4,     CPSR
-       bic     r4,     r4, #IRQ_MASK
-       bic     r4,     r4, #FIQ_MASK
-       msr     CPSR,   r4
-
-       /* set TAP CONF to TRI EMULATION */
-
-       ldr     r1,     [r0, #CONFIG_MODE2]
-       bic     r1,     r1, #0x18
-       orr     r1,     r1, #0x10
-       str     r1,     [r0, #CONFIG_MODE2]
-
-       /* set tdbgen to 1 */
-
-       ldr     r0,     PERSEUS2_CONFIG_BASE
-       ldr     r1,     [r0, #CONFIG_MODE1]
-       mov     r2,     #0x10000
-       orr     r1,     r1, r2
-       str     r1,     [r0, #CONFIG_MODE1]
-
-#ifdef CONFIG_P2_OMAP1610
-       /* inserting additional 2 clock cycle hold time for LAN */
-       ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
-       ldr     r1,     VAL_TC_EMIFS_CS1_ADVANCED
-       str     r1,     [r0]
-#endif
-       /* Start MPU Timer 1 */
-       ldr     r0,     REG_MPU_LOAD_TIMER
-       ldr     r1,     VAL_MPU_LOAD_TIMER
-       str     r1,     [r0]
-
-       ldr     r0,     REG_MPU_CNTL_TIMER
-       ldr     r1,     VAL_MPU_CNTL_TIMER
-       str     r1,     [r0]
-
-       /* back to arch calling code */
-       mov     pc,     r11
-
-       /* the literal pools origin */
-       .ltorg
-
-REG_TC_EMIFS_CONFIG:           /* 32 bits */
-       .word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
-       .word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
-       .word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
-       .word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
-       .word 0xfffecc1c
-
-#ifdef CONFIG_P2_OMAP730
-REG_TC_EMIFS_CS1_ADVANCED:     /* 32 bits */
-       .word 0xfffecc54
-#endif
-
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL:                 /* 16 bits */
-       .word 0xfffece00
-
-REG_ARM_IDLECT3:               /* 16 bits */
-       .word 0xfffece24
-REG_ARM_IDLECT2:               /* 16 bits */
-       .word 0xfffece08
-REG_ARM_IDLECT1:               /* 16 bits */
-       .word 0xfffece04
-
-REG_ARM_RSTCT2:                        /* 16 bits */
-       .word 0xfffece14
-REG_ARM_SYSST:                 /* 16 bits */
-       .word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL:                 /* 16 bits */
-       .word 0xfffecf00
-
-/* Watch Dog register */
-/* secure watchdog stop */
-REG_WSPRDOG:
-       .word 0xfffeb048
-/* watchdog write pending */
-REG_WWPSDOG:
-       .word 0xfffeb034
-
-WSPRDOG_VAL1:
-       .word 0x0000aaaa
-WSPRDOG_VAL2:
-       .word 0x00005555
-
-/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
- counter @8192 rows, 10 ns, 8 burst */
-REG_SDRAM_CONFIG:
-       .word 0xfffecc20
-
-REG_SDRAM_MRS_LEGACY:
-       .word 0xfffecc24
-
-REG_WATCHDOG:
-       .word 0xfffec808
-
-REG_MPU_LOAD_TIMER:
-       .word 0xfffec600
-REG_MPU_CNTL_TIMER:
-       .word 0xfffec500
-
-/* Public and private rhea bridge registers definition */
-
-REG_RHEA_PUB_CTL:
-       .word 0xFFFECA00
-
-REG_RHEA_PRIV_CTL:
-       .word 0xFFFED300
-
-/* EMIFF SDRAM Configuration register
-   - self refresh disable
-   - auto refresh enabled
-   - SDRAM type 64 Mb, 16 bits bus 4 banks
-   - power down enabled
-   - SDRAM clock disabled
- */
-SDRAM_CONFIG_VAL:
-       .word 0x0C017DF4
-
-/* Burst full page length ; cas latency = 3 */
-SDRAM_MRS_VAL:
-       .word 0x00000037
-
-VAL_ARM_CKCTL:
-       .word 0x6505
-VAL_DPLL1_CTL:
-       .word 0x3412
-
-#ifdef CONFIG_P2_OMAP730
-VAL_TC_EMIFS_CS0_CONFIG:
-       .word 0x0000FFF3
-VAL_TC_EMIFS_CS1_CONFIG:
-       .word 0x00004278
-VAL_TC_EMIFS_CS2_CONFIG:
-       .word 0x00004278
-VAL_TC_EMIFS_CS3_CONFIG:
-       .word 0x00004278
-VAL_TC_EMIFS_CS1_ADVANCED:
-       .word 0x00000022
-#endif
-
-VAL_ARM_IDLECT1:
-       .word 0x00000400
-VAL_ARM_IDLECT2:
-       .word 0x00000886
-VAL_ARM_IDLECT3:
-       .word 0x00000015
-
-WATCHDOG_VAL1:
-       .word 0x000000f5
-WATCHDOG_VAL2:
-       .word 0x000000a0
-
-VAL_MPU_LOAD_TIMER:
-       .word 0xffffffff
-VAL_MPU_CNTL_TIMER:
-       .word 0xffffffa1
-
-VAL_RHEA_CTL:
-       .word                   0xFF22
-
-/* Config Register vals */
-PERSEUS2_CONFIG_BASE:
-       .word                   0xFFFE1000
-
-.equ   CONFIG_PCC_CONF,        0xB4
-.equ   CONFIG_MODE1,           0x10
-.equ   CONFIG_MODE2,           0x14
-.equ   CONF_MOD_UART1_CLK_MODE_R,      0x0A
-
-/* misc values */
-.equ   IRQ_MASK,               0x80           /* IRQ mask value */
-.equ   FIQ_MASK,               0x40           /* FIQ mask value */
index 8cd02d1411bac55833118e2715dc1fbc3561a571..8fbdf2a5e337c860e3079a7fe77c3554a4ace27a 100644 (file)
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    = lib$(BOARD).a
 
 OBJS   := sx1.o
-SOBJS  := platform.o
+SOBJS  := lowlevel_init.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $^
diff --git a/board/sx1/lowlevel_init.S b/board/sx1/lowlevel_init.S
new file mode 100644 (file)
index 0000000..bdf812e
--- /dev/null
@@ -0,0 +1,397 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * -- Some bits of code used from rrload's head_OMAP1510.s --
+ * Copyright (C) 2002 RidgeRun, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
+
+
+_TEXT_BASE:
+       .word   TEXT_BASE        /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+       /*
+        * Configure 1510 pins functions to match our board.
+        */
+       ldr     r0, REG_PULL_DWN_CTRL_0
+       ldr     r1, VAL_PULL_DWN_CTRL_0
+       str     r1, [r0]
+       ldr     r0, REG_PULL_DWN_CTRL_1
+       ldr     r1, VAL_PULL_DWN_CTRL_1
+       str     r1, [r0]
+       ldr     r0, REG_PULL_DWN_CTRL_2
+       ldr     r1, VAL_PULL_DWN_CTRL_2
+       str     r1, [r0]
+       ldr     r0, REG_PULL_DWN_CTRL_3
+       ldr     r1, VAL_PULL_DWN_CTRL_3
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_4
+       ldr     r1, VAL_FUNC_MUX_CTRL_4
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_5
+       ldr     r1, VAL_FUNC_MUX_CTRL_5
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_6
+       ldr     r1, VAL_FUNC_MUX_CTRL_6
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_7
+       ldr     r1, VAL_FUNC_MUX_CTRL_7
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_8
+       ldr     r1, VAL_FUNC_MUX_CTRL_8
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_9
+       ldr     r1, VAL_FUNC_MUX_CTRL_9
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_A
+       ldr     r1, VAL_FUNC_MUX_CTRL_A
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_B
+       ldr     r1, VAL_FUNC_MUX_CTRL_B
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_C
+       ldr     r1, VAL_FUNC_MUX_CTRL_C
+       str     r1, [r0]
+       ldr     r0, REG_FUNC_MUX_CTRL_D
+       ldr     r1, VAL_FUNC_MUX_CTRL_D
+       str     r1, [r0]
+       ldr     r0, REG_VOLTAGE_CTRL_0
+       ldr     r1, VAL_VOLTAGE_CTRL_0
+       str     r1, [r0]
+       ldr     r0, REG_TEST_DBG_CTRL_0
+       ldr     r1, VAL_TEST_DBG_CTRL_0
+       str     r1, [r0]
+       ldr     r0, REG_MOD_CONF_CTRL_0
+       ldr     r1, VAL_MOD_CONF_CTRL_0
+       str     r1, [r0]
+
+       /* Move to 1510 mode */
+       ldr     r0, REG_COMP_MODE_CTRL_0
+       ldr     r1, VAL_COMP_MODE_CTRL_0
+       str     r1, [r0]
+
+       /* Set up Traffic Ctlr*/
+       ldr r0, REG_TC_IMIF_PRIO
+       mov r1, #0x0
+       str r1, [r0]
+       ldr r0, REG_TC_EMIFS_PRIO
+       str r1, [r0]
+       ldr r0, REG_TC_EMIFF_PRIO
+       str r1, [r0]
+
+       ldr r0, REG_TC_EMIFS_CONFIG
+       ldr r1, [r0]
+       bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
+       bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
+       str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
+
+       ldr r0, _GPIO_PIN_CONTROL_REG
+       mov r1,#0
+       orr r1, r1, #0x0001 /* M_PCM_SYNC */
+       orr r1, r1, #0x4000 /* IPC_ACTIVE */
+       strh r1,[r0]
+
+       ldr r0, _GPIO_DIR_CONTROL_REG
+       mov r1,#0
+       bic r1, r1, #0x0001 /* M_PCM_SYNC */
+       bic r1, r1, #0x4000 /* IPC_ACTIVE */
+       strh r1,[r0]
+
+       ldr r0, _GPIO_DATA_OUTPUT_REG
+       mov r1,#0
+       bic r1, r1, #0x0001 /* M_PCM_SYNC */
+       orr r1, r1, #0x4000 /* IPC_ACTIVE */
+       strh r1,[r0]
+
+       /* Setup some clock domains */
+       ldr r1, =OMAP1510_CLKS
+       ldr r0, REG_ARM_IDLECT2
+       strh r1, [r0]  /* CLKM, Clock domain control. */
+
+       mov r1, #0x01  /* PER_EN bit */
+       ldr r0, REG_ARM_RSTCT2
+       strh r1, [r0]  /* CLKM; Peripheral reset. */
+
+       /* Set CLKM to Sync-Scalable  */
+       /* I supposidly need to enable the dsp clock before switching */
+       mov r1, #0x1000
+       ldr r0, REG_ARM_SYSST
+       strh r1, [r0]
+       mov r0, #0x400
+1:
+       subs r0, r0, #0x1   /* wait for any bubbles to finish */
+       bne 1b
+
+       ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
+       ldr r0, REG_ARM_CKCTL
+       strh r1, [r0]
+
+       /* setup DPLL 1 */
+       ldr r1, VAL_DPLL1_CTL
+       ldr r0, REG_DPLL1_CTL
+       strh r1, [r0]
+       ands r1, r1, #0x10  /* Check if PLL is enabled. */
+       beq lock_end        /* Do not look for lock if BYPASS selected */
+2:
+       ldrh r1, [r0]
+       ands r1, r1, #0x01  /* Check the LOCK bit. */
+       beq 2b              /* ...loop until bit goes hi. */
+lock_end:
+
+       /* Set memory timings corresponding to the new clock speed */
+
+       /* Check execution location to determine current execution location
+        * and branch to appropriate initialization code.
+        */
+       mov r0, #0x10000000                 /* Load physical SDRAM base. */
+       mov r1, pc                          /* Get current execution location. */
+       cmp r1, r0                          /* Compare. */
+       bge skip_sdram                      /* Skip over EMIF-fast initialization if running from SDRAM. */
+
+       /*
+        * Delay for SDRAM initialization.
+        */
+       mov r3, #0x1800                        /* value should be checked */
+3:
+       subs r3, r3, #0x1                     /* Decrement count */
+       bne 3b
+
+       /*
+        * Set SDRAM control values. Disable refresh before MRS command.
+        */
+       ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
+       bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
+       orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
+       orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
+       ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+       str r3, [r2]                        /* Store the passed value with AR disabled. */
+
+       ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
+       ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
+       str r1, [r2]                        /* Store the passed value.*/
+
+       ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+       str r0, [r2]                        /* Store the passed value. */
+
+       /*
+        * Delay for SDRAM initialization.
+        */
+       mov r3, #0x1800
+4:
+       subs r3, r3, #1                     /* Decrement count. */
+       bne 4b
+
+skip_sdram:
+
+       /* slow interface */
+       ldr r1, VAL_TC_EMIFS_CS0_CONFIG
+       ldr r0, REG_TC_EMIFS_CS0_CONFIG
+       str r1, [r0] /* Chip Select 0 */
+       ldr r1, VAL_TC_EMIFS_CS1_CONFIG
+       ldr r0, REG_TC_EMIFS_CS1_CONFIG
+       str r1, [r0] /* Chip Select 1 */
+       ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+       ldr r0, REG_TC_EMIFS_CS2_CONFIG
+       str r1, [r0] /* Chip Select 2 */
+       ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+       ldr r0, REG_TC_EMIFS_CS3_CONFIG
+       str r1, [r0] /* Chip Select 3 */
+
+       /* back to arch calling code */
+       mov     pc, lr
+
+/* the literal pools origin */
+       .ltorg
+
+/* OMAP configuration registers */
+REG_FUNC_MUX_CTRL_0:           /* 32 bits */
+       .word 0xfffe1000
+REG_FUNC_MUX_CTRL_1:           /* 32 bits */
+       .word 0xfffe1004
+REG_FUNC_MUX_CTRL_2:           /* 32 bits */
+       .word 0xfffe1008
+REG_COMP_MODE_CTRL_0:          /* 32 bits */
+       .word 0xfffe100c
+REG_FUNC_MUX_CTRL_3:           /* 32 bits */
+       .word 0xfffe1010
+REG_FUNC_MUX_CTRL_4:           /* 32 bits */
+       .word 0xfffe1014
+REG_FUNC_MUX_CTRL_5:           /* 32 bits */
+       .word 0xfffe1018
+REG_FUNC_MUX_CTRL_6:           /* 32 bits */
+       .word 0xfffe101c
+REG_FUNC_MUX_CTRL_7:           /* 32 bits */
+       .word 0xfffe1020
+REG_FUNC_MUX_CTRL_8:           /* 32 bits */
+       .word 0xfffe1024
+REG_FUNC_MUX_CTRL_9:           /* 32 bits */
+       .word 0xfffe1028
+REG_FUNC_MUX_CTRL_A:           /* 32 bits */
+       .word 0xfffe102C
+REG_FUNC_MUX_CTRL_B:           /* 32 bits */
+       .word 0xfffe1030
+REG_FUNC_MUX_CTRL_C:           /* 32 bits */
+       .word 0xfffe1034
+REG_FUNC_MUX_CTRL_D:           /* 32 bits */
+       .word 0xfffe1038
+REG_PULL_DWN_CTRL_0:           /* 32 bits */
+       .word 0xfffe1040
+REG_PULL_DWN_CTRL_1:           /* 32 bits */
+       .word 0xfffe1044
+REG_PULL_DWN_CTRL_2:           /* 32 bits */
+       .word 0xfffe1048
+REG_PULL_DWN_CTRL_3:           /* 32 bits */
+       .word 0xfffe104c
+REG_VOLTAGE_CTRL_0:            /* 32 bits */
+       .word 0xfffe1060
+REG_TEST_DBG_CTRL_0:           /* 32 bits */
+       .word 0xfffe1070
+REG_MOD_CONF_CTRL_0:           /* 32 bits */
+       .word 0xfffe1080
+REG_TC_IMIF_PRIO:              /* 32 bits */
+       .word 0xfffecc00
+REG_TC_EMIFS_PRIO:             /* 32 bits */
+       .word 0xfffecc04
+REG_TC_EMIFF_PRIO:             /* 32 bits */
+       .word 0xfffecc08
+REG_TC_EMIFS_CONFIG:           /* 32 bits */
+       .word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
+       .word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
+       .word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
+       .word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
+       .word 0xfffecc1c
+REG_TC_EMIFF_SDRAM_CONFIG:     /* 32 bits */
+       .word 0xfffecc20
+REG_TC_EMIFF_MRS:              /* 32 bits */
+       .word 0xfffecc24
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:                 /* 16 bits */
+       .word 0xfffece00
+REG_ARM_IDLECT2:               /* 16 bits */
+       .word 0xfffece08
+REG_ARM_RSTCT2:                        /* 16 bits */
+       .word 0xfffece14
+REG_ARM_SYSST:                 /* 16 bits */
+       .word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:                 /* 16 bits */
+       .word 0xfffecf00
+/* identification code register */
+REG_IDCODE:                    /* 32 bits */
+       .word 0xfffed404
+
+/* SX1 specific */
+_GPIO_PIN_CONTROL_REG:
+       .word GPIO_PIN_CONTROL_REG
+_GPIO_DIR_CONTROL_REG:
+       .word GPIO_DIR_CONTROL_REG
+_GPIO_DATA_OUTPUT_REG:
+       .word GPIO_DATA_OUTPUT_REG
+
+VAL_COMP_MODE_CTRL_0:
+       .word 0x0000eaef
+VAL_FUNC_MUX_CTRL_4:
+       .word 0x00000000
+VAL_FUNC_MUX_CTRL_5:
+       .word 0x00000000
+VAL_FUNC_MUX_CTRL_6:
+       .word 0x00000001
+VAL_FUNC_MUX_CTRL_7:
+       .word 0x00001000
+VAL_FUNC_MUX_CTRL_8:
+       .word 0x00001240       /*[Knoller]  Value of Symbian Image Wing B2*/
+VAL_FUNC_MUX_CTRL_9:
+       .word 0x00201008
+VAL_FUNC_MUX_CTRL_A:
+       .word 0x00001000
+VAL_FUNC_MUX_CTRL_B:
+       .word 0x00000000
+VAL_FUNC_MUX_CTRL_C:
+       .word 0x09008001       /*[Knoller]  Value of Symbian Image Wing B2*/
+VAL_FUNC_MUX_CTRL_D:
+       .word 0x00000000
+VAL_PULL_DWN_CTRL_0:
+       .word 0xfffeffff
+VAL_PULL_DWN_CTRL_1:
+       .word 0xd1ffffec
+VAL_PULL_DWN_CTRL_2:
+       .word 0xffa80c5b
+VAL_PULL_DWN_CTRL_3:
+       .word 0xffffc0fe
+VAL_VOLTAGE_CTRL_0:
+       .word 0x00000007
+VAL_TEST_DBG_CTRL_0:
+       /* The OMAP5910 TRM says this register must be 0, but HelenConfRegs
+        * says to write a 7.  Don't know what the right thing is to do, so
+        * I'm leaving it at 7 since that's what was already here.
+        */
+       .word 0x00000007
+VAL_MOD_CONF_CTRL_0:
+       .word 0x0da20000       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_ARM_CKCTL:
+       .word 0x010D
+
+VAL_DPLL1_CTL:
+       .word 0x3A33   /*[Hertle] Value of Symbian Image*/
+
+VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
+       .word 0x00001149
+
+VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
+       .word 0x00004158
+
+VAL_TC_EMIFS_CS0_CONFIG:
+       .word 0x00213090       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFS_CS1_CONFIG:
+       .word 0x00215070       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFS_CS2_CONFIG:
+       .word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFS_CS3_CONFIG:
+       .word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+       .word 0x0105f0b4       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+
+VAL_TC_EMIFF_MRS:
+       .word 0x00000027       /*[Knoller]  Value of Symbian Image Wing B2*/
diff --git a/board/sx1/platform.S b/board/sx1/platform.S
deleted file mode 100644 (file)
index bd54df1..0000000
+++ /dev/null
@@ -1,397 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- *
- * -- Some bits of code used from rrload's head_OMAP1510.s --
- * Copyright (C) 2002 RidgeRun, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1510)
-#include <./configs/omap1510.h>
-#endif
-
-#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
-
-
-_TEXT_BASE:
-       .word   TEXT_BASE        /* sdram load addr from config.mk */
-
-.globl platformsetup
-platformsetup:
-
-       /*
-        * Configure 1510 pins functions to match our board.
-        */
-       ldr     r0, REG_PULL_DWN_CTRL_0
-       ldr     r1, VAL_PULL_DWN_CTRL_0
-       str     r1, [r0]
-       ldr     r0, REG_PULL_DWN_CTRL_1
-       ldr     r1, VAL_PULL_DWN_CTRL_1
-       str     r1, [r0]
-       ldr     r0, REG_PULL_DWN_CTRL_2
-       ldr     r1, VAL_PULL_DWN_CTRL_2
-       str     r1, [r0]
-       ldr     r0, REG_PULL_DWN_CTRL_3
-       ldr     r1, VAL_PULL_DWN_CTRL_3
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_4
-       ldr     r1, VAL_FUNC_MUX_CTRL_4
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_5
-       ldr     r1, VAL_FUNC_MUX_CTRL_5
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_6
-       ldr     r1, VAL_FUNC_MUX_CTRL_6
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_7
-       ldr     r1, VAL_FUNC_MUX_CTRL_7
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_8
-       ldr     r1, VAL_FUNC_MUX_CTRL_8
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_9
-       ldr     r1, VAL_FUNC_MUX_CTRL_9
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_A
-       ldr     r1, VAL_FUNC_MUX_CTRL_A
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_B
-       ldr     r1, VAL_FUNC_MUX_CTRL_B
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_C
-       ldr     r1, VAL_FUNC_MUX_CTRL_C
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_D
-       ldr     r1, VAL_FUNC_MUX_CTRL_D
-       str     r1, [r0]
-       ldr     r0, REG_VOLTAGE_CTRL_0
-       ldr     r1, VAL_VOLTAGE_CTRL_0
-       str     r1, [r0]
-       ldr     r0, REG_TEST_DBG_CTRL_0
-       ldr     r1, VAL_TEST_DBG_CTRL_0
-       str     r1, [r0]
-       ldr     r0, REG_MOD_CONF_CTRL_0
-       ldr     r1, VAL_MOD_CONF_CTRL_0
-       str     r1, [r0]
-
-       /* Move to 1510 mode */
-       ldr     r0, REG_COMP_MODE_CTRL_0
-       ldr     r1, VAL_COMP_MODE_CTRL_0
-       str     r1, [r0]
-
-       /* Set up Traffic Ctlr*/
-       ldr r0, REG_TC_IMIF_PRIO
-       mov r1, #0x0
-       str r1, [r0]
-       ldr r0, REG_TC_EMIFS_PRIO
-       str r1, [r0]
-       ldr r0, REG_TC_EMIFF_PRIO
-       str r1, [r0]
-
-       ldr r0, REG_TC_EMIFS_CONFIG
-       ldr r1, [r0]
-       bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
-       bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
-       str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
-
-       ldr r0, _GPIO_PIN_CONTROL_REG
-       mov r1,#0
-       orr r1, r1, #0x0001 /* M_PCM_SYNC */
-       orr r1, r1, #0x4000 /* IPC_ACTIVE */
-       strh r1,[r0]
-
-       ldr r0, _GPIO_DIR_CONTROL_REG
-       mov r1,#0
-       bic r1, r1, #0x0001 /* M_PCM_SYNC */
-       bic r1, r1, #0x4000 /* IPC_ACTIVE */
-       strh r1,[r0]
-
-       ldr r0, _GPIO_DATA_OUTPUT_REG
-       mov r1,#0
-       bic r1, r1, #0x0001 /* M_PCM_SYNC */
-       orr r1, r1, #0x4000 /* IPC_ACTIVE */
-       strh r1,[r0]
-
-       /* Setup some clock domains */
-       ldr r1, =OMAP1510_CLKS
-       ldr r0, REG_ARM_IDLECT2
-       strh r1, [r0]  /* CLKM, Clock domain control. */
-
-       mov r1, #0x01  /* PER_EN bit */
-       ldr r0, REG_ARM_RSTCT2
-       strh r1, [r0]  /* CLKM; Peripheral reset. */
-
-       /* Set CLKM to Sync-Scalable  */
-       /* I supposidly need to enable the dsp clock before switching */
-       mov r1, #0x1000
-       ldr r0, REG_ARM_SYSST
-       strh r1, [r0]
-       mov r0, #0x400
-1:
-       subs r0, r0, #0x1   /* wait for any bubbles to finish */
-       bne 1b
-
-       ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
-       ldr r0, REG_ARM_CKCTL
-       strh r1, [r0]
-
-       /* setup DPLL 1 */
-       ldr r1, VAL_DPLL1_CTL
-       ldr r0, REG_DPLL1_CTL
-       strh r1, [r0]
-       ands r1, r1, #0x10  /* Check if PLL is enabled. */
-       beq lock_end        /* Do not look for lock if BYPASS selected */
-2:
-       ldrh r1, [r0]
-       ands r1, r1, #0x01  /* Check the LOCK bit. */
-       beq 2b              /* ...loop until bit goes hi. */
-lock_end:
-
-       /* Set memory timings corresponding to the new clock speed */
-
-       /* Check execution location to determine current execution location
-        * and branch to appropriate initialization code.
-        */
-       mov r0, #0x10000000                 /* Load physical SDRAM base. */
-       mov r1, pc                          /* Get current execution location. */
-       cmp r1, r0                          /* Compare. */
-       bge skip_sdram                      /* Skip over EMIF-fast initialization if running from SDRAM. */
-
-       /*
-        * Delay for SDRAM initialization.
-        */
-       mov r3, #0x1800                        /* value should be checked */
-3:
-       subs r3, r3, #0x1                     /* Decrement count */
-       bne 3b
-
-       /*
-        * Set SDRAM control values. Disable refresh before MRS command.
-        */
-       ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
-       bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
-       orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
-       orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
-       ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
-       str r3, [r2]                        /* Store the passed value with AR disabled. */
-
-       ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
-       ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
-       str r1, [r2]                        /* Store the passed value.*/
-
-       ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
-       str r0, [r2]                        /* Store the passed value. */
-
-       /*
-        * Delay for SDRAM initialization.
-        */
-       mov r3, #0x1800
-4:
-       subs r3, r3, #1                     /* Decrement count. */
-       bne 4b
-
-skip_sdram:
-
-       /* slow interface */
-       ldr r1, VAL_TC_EMIFS_CS0_CONFIG
-       ldr r0, REG_TC_EMIFS_CS0_CONFIG
-       str r1, [r0] /* Chip Select 0 */
-       ldr r1, VAL_TC_EMIFS_CS1_CONFIG
-       ldr r0, REG_TC_EMIFS_CS1_CONFIG
-       str r1, [r0] /* Chip Select 1 */
-       ldr r1, VAL_TC_EMIFS_CS2_CONFIG
-       ldr r0, REG_TC_EMIFS_CS2_CONFIG
-       str r1, [r0] /* Chip Select 2 */
-       ldr r1, VAL_TC_EMIFS_CS3_CONFIG
-       ldr r0, REG_TC_EMIFS_CS3_CONFIG
-       str r1, [r0] /* Chip Select 3 */
-
-       /* back to arch calling code */
-       mov     pc, lr
-
-/* the literal pools origin */
-       .ltorg
-
-/* OMAP configuration registers */
-REG_FUNC_MUX_CTRL_0:           /* 32 bits */
-       .word 0xfffe1000
-REG_FUNC_MUX_CTRL_1:           /* 32 bits */
-       .word 0xfffe1004
-REG_FUNC_MUX_CTRL_2:           /* 32 bits */
-       .word 0xfffe1008
-REG_COMP_MODE_CTRL_0:          /* 32 bits */
-       .word 0xfffe100c
-REG_FUNC_MUX_CTRL_3:           /* 32 bits */
-       .word 0xfffe1010
-REG_FUNC_MUX_CTRL_4:           /* 32 bits */
-       .word 0xfffe1014
-REG_FUNC_MUX_CTRL_5:           /* 32 bits */
-       .word 0xfffe1018
-REG_FUNC_MUX_CTRL_6:           /* 32 bits */
-       .word 0xfffe101c
-REG_FUNC_MUX_CTRL_7:           /* 32 bits */
-       .word 0xfffe1020
-REG_FUNC_MUX_CTRL_8:           /* 32 bits */
-       .word 0xfffe1024
-REG_FUNC_MUX_CTRL_9:           /* 32 bits */
-       .word 0xfffe1028
-REG_FUNC_MUX_CTRL_A:           /* 32 bits */
-       .word 0xfffe102C
-REG_FUNC_MUX_CTRL_B:           /* 32 bits */
-       .word 0xfffe1030
-REG_FUNC_MUX_CTRL_C:           /* 32 bits */
-       .word 0xfffe1034
-REG_FUNC_MUX_CTRL_D:           /* 32 bits */
-       .word 0xfffe1038
-REG_PULL_DWN_CTRL_0:           /* 32 bits */
-       .word 0xfffe1040
-REG_PULL_DWN_CTRL_1:           /* 32 bits */
-       .word 0xfffe1044
-REG_PULL_DWN_CTRL_2:           /* 32 bits */
-       .word 0xfffe1048
-REG_PULL_DWN_CTRL_3:           /* 32 bits */
-       .word 0xfffe104c
-REG_VOLTAGE_CTRL_0:            /* 32 bits */
-       .word 0xfffe1060
-REG_TEST_DBG_CTRL_0:           /* 32 bits */
-       .word 0xfffe1070
-REG_MOD_CONF_CTRL_0:           /* 32 bits */
-       .word 0xfffe1080
-REG_TC_IMIF_PRIO:              /* 32 bits */
-       .word 0xfffecc00
-REG_TC_EMIFS_PRIO:             /* 32 bits */
-       .word 0xfffecc04
-REG_TC_EMIFF_PRIO:             /* 32 bits */
-       .word 0xfffecc08
-REG_TC_EMIFS_CONFIG:           /* 32 bits */
-       .word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
-       .word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
-       .word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
-       .word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
-       .word 0xfffecc1c
-REG_TC_EMIFF_SDRAM_CONFIG:     /* 32 bits */
-       .word 0xfffecc20
-REG_TC_EMIFF_MRS:              /* 32 bits */
-       .word 0xfffecc24
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL:                 /* 16 bits */
-       .word 0xfffece00
-REG_ARM_IDLECT2:               /* 16 bits */
-       .word 0xfffece08
-REG_ARM_RSTCT2:                        /* 16 bits */
-       .word 0xfffece14
-REG_ARM_SYSST:                 /* 16 bits */
-       .word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL:                 /* 16 bits */
-       .word 0xfffecf00
-/* identification code register */
-REG_IDCODE:                    /* 32 bits */
-       .word 0xfffed404
-
-/* SX1 specific */
-_GPIO_PIN_CONTROL_REG:
-       .word GPIO_PIN_CONTROL_REG
-_GPIO_DIR_CONTROL_REG:
-       .word GPIO_DIR_CONTROL_REG
-_GPIO_DATA_OUTPUT_REG:
-       .word GPIO_DATA_OUTPUT_REG
-
-VAL_COMP_MODE_CTRL_0:
-       .word 0x0000eaef
-VAL_FUNC_MUX_CTRL_4:
-       .word 0x00000000
-VAL_FUNC_MUX_CTRL_5:
-       .word 0x00000000
-VAL_FUNC_MUX_CTRL_6:
-       .word 0x00000001
-VAL_FUNC_MUX_CTRL_7:
-       .word 0x00001000
-VAL_FUNC_MUX_CTRL_8:
-       .word 0x00001240       /*[Knoller]  Value of Symbian Image Wing B2*/
-VAL_FUNC_MUX_CTRL_9:
-       .word 0x00201008
-VAL_FUNC_MUX_CTRL_A:
-       .word 0x00001000
-VAL_FUNC_MUX_CTRL_B:
-       .word 0x00000000
-VAL_FUNC_MUX_CTRL_C:
-       .word 0x09008001       /*[Knoller]  Value of Symbian Image Wing B2*/
-VAL_FUNC_MUX_CTRL_D:
-       .word 0x00000000
-VAL_PULL_DWN_CTRL_0:
-       .word 0xfffeffff
-VAL_PULL_DWN_CTRL_1:
-       .word 0xd1ffffec
-VAL_PULL_DWN_CTRL_2:
-       .word 0xffa80c5b
-VAL_PULL_DWN_CTRL_3:
-       .word 0xffffc0fe
-VAL_VOLTAGE_CTRL_0:
-       .word 0x00000007
-VAL_TEST_DBG_CTRL_0:
-       /* The OMAP5910 TRM says this register must be 0, but HelenConfRegs
-        * says to write a 7.  Don't know what the right thing is to do, so
-        * I'm leaving it at 7 since that's what was already here.
-        */
-       .word 0x00000007
-VAL_MOD_CONF_CTRL_0:
-       .word 0x0da20000       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-VAL_ARM_CKCTL:
-       .word 0x010D
-
-VAL_DPLL1_CTL:
-       .word 0x3A33   /*[Hertle] Value of Symbian Image*/
-
-VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
-       .word 0x00001149
-
-VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
-       .word 0x00004158
-
-VAL_TC_EMIFS_CS0_CONFIG:
-       .word 0x00213090       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-VAL_TC_EMIFS_CS1_CONFIG:
-       .word 0x00215070       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-VAL_TC_EMIFS_CS2_CONFIG:
-       .word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-VAL_TC_EMIFS_CS3_CONFIG:
-       .word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-VAL_TC_EMIFF_SDRAM_CONFIG:
-       .word 0x0105f0b4       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-
-VAL_TC_EMIFF_MRS:
-       .word 0x00000027       /*[Knoller]  Value of Symbian Image Wing B2*/
index 42b6ed5b5c9ffd2de396f154d1f2c85b0d1ef796..fbdc627e386869ce57971fe4518afb25adb1afad 100644 (file)
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    = lib$(BOARD).a
 
 OBJS   := versatile.o flash.o
-SOBJS  := platform.o
+SOBJS  := lowlevel_init.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $^
diff --git a/board/versatile/lowlevel_init.S b/board/versatile/lowlevel_init.S
new file mode 100644 (file)
index 0000000..bdfce2d
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+       /* All done by Versatile's boot monitor! */
+       mov pc, lr
diff --git a/board/versatile/platform.S b/board/versatile/platform.S
deleted file mode 100644 (file)
index 68c3e8b..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-.globl platformsetup
-platformsetup:
-
-       /* All done by Versatile's boot monitor! */
-       mov pc, lr
diff --git a/board/versatile/split_by_variant.sh b/board/versatile/split_by_variant.sh
new file mode 100644 (file)
index 0000000..b462b7e
--- /dev/null
@@ -0,0 +1,45 @@
+#!/bin/sh
+# ---------------------------------------------------------
+#  Set the core module defines according to Core Module
+# ---------------------------------------------------------
+CC=$(CROSS_COMPILE)gcc
+config="versatilepb_config"
+
+if [ "$2" == "" ]
+then
+       echo "$0:: No preprocessor parameter - using $(CROSS_COMPILE)gcc"
+else
+       CC=$2
+fi
+
+
+# ---------------------------------------------------------
+# Set up the Versatile type define
+# ---------------------------------------------------------
+if [ "$1" == "" ]
+then
+       echo "$0:: No parameters - using $(CROSS_COMPILE)gcc versatilepb_config"
+
+else
+       case "$config" in
+       versatilepb_config      |       \
+       versatile_config)
+       echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h
+       ;;
+
+       versatileab_config)
+       echo "#define CONFIG_ARCH_VERSATILE_AB" > ./include/config.h
+       ;;
+
+
+       *)
+       echo "$0:: Unrecognised config - using versatilepb_config"
+       ;;
+
+       esac
+
+fi
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+./mkconfig -a versatile arm arm926ejs versatile
index 4a110e846dc084491f6786f80ee8a55ab14d161e..dcf37b5dce5bc9390f60e823162b691dfa93dcd9 100644 (file)
@@ -122,8 +122,8 @@ MUX_CONFIG_OFFSETS:
        .byte 0x0c              @ COMP_MODE_CTRL_0
        .byte 0xff
 
-.globl platformsetup
-platformsetup:
+.globl lowlevel_init
+lowlevel_init:
        /* Improve performance a bit... */
        mrc     p15, 0, r1, c0, c0, 0           @ read C15 ID register
        mrc     p15, 0, r1, c0, c0, 1           @ read C15 Cache information register
index 23236dcb0ff770ad1ad6f1b66485ad98adaa4940..6b1449e97a78620aa6c5f9e0dfa36adff2aa52c1 100644 (file)
 
 #include <common.h>
 #include <asm/arch/bits.h>
-#include <asm/arch/omap2420.h>
+
+#if !defined(CONFIG_INTEGRATOR) || ! defined(CONFIG_ARCH_CINTEGRATOR)
+# include <asm/arch/omap2420.h>
+#endif
+
 #include <asm/proc-armv/ptrace.h>
 
 #define TIMER_LOAD_VAL 0
@@ -175,6 +179,9 @@ void do_irq (struct pt_regs *pt_regs)
 static ulong timestamp;
 static ulong lastinc;
 
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
+/* Use the IntegratorCP function from board/integratorcp.c */
+#else
 /* nothing really to do with interrupts, just starts up a counter. */
 int interrupt_init (void)
 {
@@ -189,7 +196,6 @@ int interrupt_init (void)
 
        return(0);
 }
-
 /*
  * timer without interrupts
  */
@@ -281,7 +287,6 @@ unsigned long long get_ticks(void)
 {
        return get_timer(0);
 }
-
 /*
  * This function is derived from PowerPC code (timebase clock frequency).
  * On ARM it returns the number of timer ticks per second.
@@ -292,3 +297,4 @@ ulong get_tbclk (void)
        tbclk = CFG_HZ;
        return tbclk;
 }
+#endif /* !Integrator/CP */
index c3bf6e37e1cfda9820866dd1b0fc157d7a2f61fb..05c9128d84858619efeb6e2e47a01cc1207c1e68 100644 (file)
@@ -210,7 +210,7 @@ cpu_init_crit:
         * basic memory.  Go here to bump up clock rate and handle wake up conditions.
         */
        mov     ip, lr          /* persevere link reg across call */
-       bl      platformsetup   /* go setup pll,mux,memory */
+       bl      lowlevel_init   /* go setup pll,mux,memory */
        mov     lr, ip          /* restore link */
        mov     pc, lr          /* back to my caller */
 /*
@@ -397,6 +397,10 @@ arm1136_cache_flush:
                mcr     p15, 0, r1, c7, c5, 0   @ invalidate I cache
                mov     pc, lr                  @ back to caller
 
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
+/* Use the IntegratorCP function from board/integratorcp/platform.S */
+#else
+
        .align  5
 .globl reset_cpu
 reset_cpu:
@@ -408,3 +412,5 @@ _loop_forever:
        b       _loop_forever
 rstctl:
        .word   PM_RSTCTRL_WKUP
+
+#endif
index fcca360732beb122c4fd6e9347d97fb867e7ccb6..a5b6de7605525783eebe3608170f8cfa255cc2f8 100644 (file)
@@ -76,6 +76,8 @@ int cleanup_before_linux (void)
 #elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B)
        disable_interrupts ();
        /* Nothing more needed */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+       /* No cleanup before linux for IntegratorAP/CM720T as yet */
 #else
 #error No cleanup_before_linux() defined for this CPU type
 #endif
@@ -245,6 +247,11 @@ int dcache_status (void)
        return icache_status();
 }
 
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+       /* No specific cache setup for IntegratorAP/CM720T as yet */
+       void icache_enable (void)
+       {
+       }
 #else
 #error No icache/dcache enable/disable functions defined for this CPU type
 #endif
index d0eaca5e0276b12a4d436a5f65be020a44417331..575d923a373c57113770907fe16585dc2f075c80 100644 (file)
@@ -193,6 +193,8 @@ void do_irq (struct pt_regs *pt_regs)
                /* clear pending interrupt */
                PUT_REG( REG_INTPEND, (1<<(pending>>2)));
        }
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+       /* No do_irq() for IntegratorAP/CM720T as yet */
 #else
 #error do_irq() not defined for this CPU type
 #endif
@@ -219,6 +221,10 @@ static void timer_isr( void *data) {
 static ulong timestamp;
 static ulong lastdec;
 
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+       /* Use IntegratorAP routines in board/integratorap.c */
+#else
+
 int interrupt_init (void)
 {
 
@@ -296,6 +302,8 @@ int interrupt_init (void)
        return (0);
 }
 
+#endif /* ! IntegratorAP */
+
 /*
  * timer without interrupts
  */
@@ -398,6 +406,8 @@ void udelay (unsigned long usec)
 
 }
 
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+       /* No timer routines for IntegratorAP/CM720T as yet */
 #else
 #error Timer routines not defined for this CPU type
 #endif
index eb26476a666b8f70bcf07df64b9820566716d098..43582b3284d69e2d3333ca8bf3f4f9dfa1b38e0b 100644 (file)
@@ -301,6 +301,8 @@ cpu_init_crit:
        ldr r1, =0x83ffffa0     /* cache-disabled  */
        str r1, [r0]
 
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+       /* No specific initialisation for IntegratorAP/CM720T as yet */
 #else
 #error No cpu_init_crit() defined for current CPU type
 #endif
@@ -316,12 +318,12 @@ cpu_init_crit:
        str     r1, [r0]
 #endif
 
+       mov     ip, lr
        /*
         * before relocating, we have to setup RAM timing
         * because memory timing is board-dependent, you will
         * find a lowlevel_init.S in your board directory.
         */
-       mov     ip, lr
        bl      lowlevel_init
        mov     lr, ip
 
@@ -530,6 +532,8 @@ reset_cpu:
 #elif defined(CONFIG_S3C4510B)
 /* Nothing done here as reseting the CPU is board specific, depending
  * on external peripherals such as watchdog timers, etc. */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+       /* No specific reset actions for IntegratorAP/CM720T as yet */
 #else
 #error No reset_cpu() defined for current CPU type
 #endif
index 74a97d52903db7396f1172f0808a0776968326ea..4603cf573376fdfaa5b7b88933c6b1190591976a 100644 (file)
@@ -255,7 +255,6 @@ cpu_init_crit:
        orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
        mcr     p15, 0, r0, c1, c0, 0
 
-
        /*
         * before relocating, we have to setup RAM timing
         * because memory timing is board-dependend, you will
@@ -264,7 +263,6 @@ cpu_init_crit:
        mov     ip, lr
        bl      lowlevel_init
        mov     lr, ip
-
        mov     pc, lr
 
 
index 238925936eaf60b2a07895748aae7f61b33b806d..acd77426d301fff7e95dac350e5ed0595c78d968 100644 (file)
@@ -246,7 +246,7 @@ cpu_init_crit:
         * Go setup Memory and board specific bits prior to relocation.
         */
        mov     ip, lr          /* perserve link reg across call */
-       bl      platformsetup   /* go setup pll,mux,memory */
+       bl      lowlevel_init   /* go setup pll,mux,memory */
        mov     lr, ip          /* restore link */
        mov     pc, lr          /* back to my caller */
 /*
index 5f5a1c59690798dfe2a7a35f9e0ad7864015dd2b..fc6b20b21e3f1c4d8a631238ea6883e3c8578438 100644 (file)
@@ -222,7 +222,7 @@ cpu_init_crit:
         * Go setup Memory and board specific bits prior to relocation.
         */
        mov     ip, lr          /* perserve link reg across call */
-       bl      platformsetup   /* go setup pll,mux,memory */
+       bl      lowlevel_init   /* go setup pll,mux,memory */
        mov     lr, ip          /* restore link */
        mov     pc, lr          /* back to my caller */
 /*
index ef3be8ec9350692f0565b2eadb9a4c32201e089b..e8c908bf28111d0784d5b6e66e2b231de3397f1c 100644 (file)
@@ -214,7 +214,7 @@ cpu_init_crit:
         * Go setup Memory and board specific bits prior to relocation.
         */
        mov     ip, lr          /* perserve link reg across call */
-       bl      platformsetup   /* go setup memory */
+       bl      lowlevel_init   /* go setup memory */
        mov     lr, ip          /* restore link */
        mov     pc, lr          /* back to my caller */
 /*
index 827221f1ea0baa75f1cf1385f5b060a3e2ab7ea4..ce8a9d26ad4fc4e1dd3d7d856aa4bc0f0faf5271 100644 (file)
@@ -62,3 +62,49 @@ of the Integrator board itself, has been placed in
 
        board/integrator<>/platform.S
        board/integrator<>/integrator<>.c
+
+Targets
+=======
+The U-Boot make targets map to the available core modules as below.
+
+Integrator/AP is no longer available from ARM.
+Core modules marked ** are also no longer available.
+
+ap720t_config          ** CM720T
+ap920t_config          ** CM920T
+ap926ejs_config        Integrator Core Module for ARM926EJ-STM
+ap946es_config         Integrator Core Module for ARM946E-STM
+cp920t_config          ** CM920T
+cp926ejs_config        Integrator Core Module for ARM926EJ-STM
+cp946es_config         Integrator Core Module for ARM946E-STM
+cp1136_config          Integrator Core Module ARM1136JF-S  TM
+
+The final groups of targets are for core modules where no explicit cpu
+code has yet been added to U-Boot i.e. they all use the same U-Boot binary
+using the generic "arm_intcm" core:
+
+ap966_config                   Integrator Core Module for ARM966E-S TM
+ap922_config                   Integrator Core Module for ARM922T TM with ETM
+ap922_XA10_config              Integrator Core Module for ARM922T using Altera Excalibur
+ap7_config                     ** CM7TDMI
+integratorap_config
+ap_config
+
+
+cp966_config                   Integrator Core Module for ARM966E-S TM
+cp922_config                   Integrator Core Module for ARM922T TM with ETM
+cp922_XA10_config              Integrator Core Module for ARM922T using Altera Excalibur
+cp1026_config                  Integrator Core Module ARM1026EJ-S TM
+integratorcp_config
+cp_config
+
+The Makefile targets call board/integrator<>/split_by_variant.sh
+to configure various defines in include/configs/integrator<>.h
+to indicate the core module & core configuration and ensure that
+board/integrator<>/u-boot.lds loads the cpu object first in the U-Boot image.
+
+*********************************
+Because of this mechanism
+> make clean
+must be run before each change in configuration
+*********************************
index 9404acd4553e156ec736e10fe495c7a22a23bba9..3056ca7f673ad919f170e6083eb5026122853e25 100644 (file)
@@ -34,6 +34,8 @@
 /* include EP7312 specific hardware file if there was one */
 #elif defined(CONFIG_ARMADILLO)
 /* include armadillo specific hardware file if there was one */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+/* include IntegratorCP/CM720T specific hardware file if there was one */
 #else
 #error No hardware file defined for this configuration
 #endif