/*******************************************************************************
* Simple function to initialise all BL31 helper libraries.
******************************************************************************/
-void bl31_lib_init(void)
+void __init bl31_lib_init(void)
{
cm_init();
}
* This function programs EL3 registers and performs other setup to enable entry
* into the next image after BL31 at the next ERET.
******************************************************************************/
-void bl31_prepare_next_image_entry(void)
+void __init bl31_prepare_next_image_entry(void)
{
entry_point_info_t *next_image_info;
uint32_t image_type;
/*
* Initialize the EL3 exception handling.
*/
-void ehf_init(void)
+void __init ehf_init(void)
{
unsigned int flags = 0;
int ret __unused;
* The unique oen is used as an index into the 'rt_svc_descs_indices' array.
* The index of the runtime service descriptor is stored at this index.
******************************************************************************/
-void runtime_svc_init(void)
+void __init runtime_svc_init(void)
{
int rc = 0;
unsigned int index, start_idx, end_idx;
* which will used for programming an entry into a lower EL. The same context
* will used to save state upon exception entry from that EL.
******************************************************************************/
-void cm_init(void)
+void __init cm_init(void)
{
/*
* The context management library has only global data to intialize, but
return 0;
}
-void ras_init(void)
+void __init ras_init(void)
{
#if ENABLE_ASSERTIONS
/* Check RAS interrupts are sorted */
/******************************************************************************
* This function initializes the psci_req_local_pwr_states.
*****************************************************************************/
-void psci_init_req_local_pwr_states(void)
+void __init psci_init_req_local_pwr_states(void)
{
/* Initialize the requested state of all non CPU power domains as OFF */
unsigned int pwrlvl;
* Function which initializes the 'psci_non_cpu_pd_nodes' or the
* 'psci_cpu_pd_nodes' corresponding to the power level.
******************************************************************************/
-static void psci_init_pwr_domain_node(unsigned char node_idx,
+static void __init psci_init_pwr_domain_node(unsigned char node_idx,
unsigned int parent_idx,
unsigned char level)
{
* mapping of the CPUs to indices via plat_core_pos_by_mpidr() and
* plat_my_core_pos() APIs.
*******************************************************************************/
-static void psci_update_pwrlvl_limits(void)
+static void __init psci_update_pwrlvl_limits(void)
{
int j, cpu_idx;
unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0};
* informs the number of root power domains. The parent nodes of the root nodes
* will point to an invalid entry(-1).
******************************************************************************/
-static void populate_power_domain_tree(const unsigned char *topology)
+static void __init populate_power_domain_tree(const unsigned char *topology)
{
unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl;
unsigned int node_index = 0U, num_children;
* | CPU 0 | CPU 1 | CPU 2 | CPU 3 |
* ------------------------------------------------
******************************************************************************/
-int psci_setup(const psci_lib_args_t *lib_args)
+int __init psci_setup(const psci_lib_args_t *lib_args)
{
const unsigned char *topology_tree;