gic_write(reg, regval);
}
-static inline void gic_reset_mask(unsigned int intr)
-{
- gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
- 1ul << GIC_INTR_BIT(intr));
-}
-
-static inline void gic_set_mask(unsigned int intr)
-{
- gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
- 1ul << GIC_INTR_BIT(intr));
-}
-
static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
{
gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
static void gic_mask_irq(struct irq_data *d)
{
- gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
+ write_gic_rmask(BIT(GIC_HWIRQ_TO_SHARED(d->hwirq)));
}
static void gic_unmask_irq(struct irq_data *d)
{
- gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
+ write_gic_smask(BIT(GIC_HWIRQ_TO_SHARED(d->hwirq)));
}
static void gic_ack_irq(struct irq_data *d)
for (i = 0; i < gic_shared_intrs; i++) {
gic_set_polarity(i, GIC_POL_POS);
gic_set_trigger(i, GIC_TRIG_LEVEL);
- gic_reset_mask(i);
+ write_gic_rmask(BIT(i));
}
for (i = 0; i < gic_vpes; i++) {
/* Set/Clear corresponding bit in Edge Detect Register */
#define GIC_SH_WEDGE_OFS 0x0280
-/* Mask manipulation */
-#define GIC_SH_RMASK_OFS 0x0300
-#define GIC_SH_SMASK_OFS 0x0380
-
/* Maps Interrupt X to a Pin */
#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
#define GIC_SH_MAP_TO_PIN(intr) (4 * (intr))