T210: Add support for 64-bit T210-based P2571 board

Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.

With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).

Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
index f2a005967c9f88782c6e95f8ba70c653e02d7d29..147e6a83d722bacfe5635a306600f882b2658071 100644 (file)
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,9 +3,16 @@ if TEGRA210
 choice
        prompt "Tegra210 board select"
 
+config TARGET_P2571
+       bool "NVIDIA Tegra210 P2571 base board"
+       help
+         P2571 is a P2530 married to a P1963 I/O board
+
 endchoice
 
 config SYS_SOC
        default "tegra210"
 
+source "board/nvidia/p2571/Kconfig"
+
 endif

diff --git a/board/nvidia/p2571/Kconfig b/board/nvidia/p2571/Kconfig
new file mode 100644 (file)
index 0000000..7bc4874
--- /dev/null
+++ b/board/nvidia/p2571/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2571
+
+config SYS_BOARD
+       default "p2571"
+
+config SYS_VENDOR
+       default "nvidia"
+
+config SYS_CONFIG_NAME
+       default "p2571"
+
+endif

diff --git a/board/nvidia/p2571/MAINTAINERS b/board/nvidia/p2571/MAINTAINERS
new file mode 100644 (file)
index 0000000..c165135
--- /dev/null
+++ b/board/nvidia/p2571/MAINTAINERS
@@ -0,0 +1,6 @@
+P2571 BOARD
+M:     Tom Warren <twarren@nvidia.com>
+S:     Maintained
+F:     board/nvidia/p2571/
+F:     include/configs/p2571.h
+F:     configs/p2571_defconfig

diff --git a/board/nvidia/p2571/Makefile b/board/nvidia/p2571/Makefile
new file mode 100644 (file)
index 0000000..223062e
--- /dev/null
+++ b/board/nvidia/p2571/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2013-2015
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += max77620_init.o
+obj-y  += p2571.o

diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c
new file mode 100644 (file)
index 0000000..ed8d4dc
--- /dev/null
+++ b/board/nvidia/p2571/max77620_init.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "max77620_init.h"
+
+/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+       struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+       writel(addr, &reg->cmd_addr0);
+       writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+       struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+       writel(data, &reg->cmd_data1);
+       writel(config, &reg->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+       uint reg;
+       debug("%s entry\n", __func__);
+
+       /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
+       debug("%s: Setting GPIO5 to enable CPU regulator\n", __func__);
+       /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */
+       reg = 0x0900 | MAX77620_GPIO5_REG;
+       tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
+       udelay(10 * 1000);
+
+       /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */
+       debug("%s: Setting GPIO1 to enable HDMI\n", __func__);
+       reg = 0x0900 | MAX77620_GPIO1_REG;
+       tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
+       udelay(10 * 1000);
+
+       /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
+       reg = 0x1C00 | MAX77620_AME_GPIO;
+       tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
+       udelay(10 * 1000);
+
+       /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v */
+       debug("%s: Set SD1 for LPDDR4, disable SD1RS, voltage to 1.125v\n",
+             __func__);
+       /* bit1=0, SD1 remote sense disabled */
+       reg = 0x0400 | MAX77620_CNFG2SD_REG;
+       tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
+       udelay(10 * 1000);
+
+       /* SD1 output = 1.125V */
+       reg = 0x2A00 | MAX77620_SD1_REG;
+       tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
+       udelay(10 * 1000);
+
+       debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+       /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+       reg = 0xF200 | MAX77620_CNFG1_L2_REG;
+       tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
+       udelay(10 * 1000);
+
+       debug("%s: Set LDO1 for USB3 phy power to 1.05V??\n", __func__);
+       /* 0xCA for 105v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+       reg = 0xCA00 | MAX77620_CNFG1_L1_REG;
+       tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
+       udelay(10 * 1000);
+}

diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h
new file mode 100644 (file)
index 0000000..9d5cce7
--- /dev/null
+++ b/board/nvidia/p2571/max77620_init.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MAX77620_INIT_H_
+#define _MAX77620_INIT_H_
+
+/* MAX77620-PMIC-specific early init regs */
+
+#define MAX77620_I2C_ADDR              0x78            /* or 0x3C 7-bit */
+
+#define MAX77620_SD0_REG               0x16
+#define MAX77620_SD1_REG               0x17
+#define MAX77620_SD2_REG               0x18
+#define MAX77620_SD3_REG               0x19
+#define MAX77620_CNFG2SD_REG           0x22
+
+#define MAX77620_CNFG1_L0_REG          0x23
+#define MAX77620_CNFG2_L0_REG          0x24
+#define MAX77620_CNFG1_L1_REG          0x25
+#define MAX77620_CNFG2_L1_REG          0x26
+#define MAX77620_CNFG1_L2_REG          0x27
+#define MAX77620_CNFG2_L2_REG          0x28
+#define MAX77620_CNFG1_L3_REG          0x29
+#define MAX77620_CNFG2_L3_REG          0x2A
+#define MAX77620_CNFG1_L4_REG          0x2B
+#define MAX77620_CNFG2_L4_REG          0x2C
+#define MAX77620_CNFG1_L5_REG          0x2D
+#define MAX77620_CNFG2_L5_REG          0x2E
+#define MAX77620_CNFG1_L6_REG          0x2F
+#define MAX77620_CNFG2_L6_REG          0x30
+#define MAX77620_CNFG1_L7_REG          0x31
+#define MAX77620_CNFG2_L7_REG          0x32
+#define MAX77620_CNFG1_L8_REG          0x33
+#define MAX77620_CNFG2_L8_REG          0x34
+#define MAX77620_CNFG3_LDO_REG         0x35
+
+#define MAX77620_GPIO0_REG             0x36
+#define MAX77620_GPIO1_REG             0x37
+#define MAX77620_GPIO2_REG             0x38
+#define MAX77620_GPIO3_REG             0x39
+#define MAX77620_GPIO4_REG             0x3A
+#define MAX77620_GPIO5_REG             0x3B
+#define MAX77620_GPIO6_REG             0x3C
+#define MAX77620_GPIO7_REG             0x3D
+#define MAX77620_GPIO_PUE_GPIO         0x3E
+#define MAX77620_GPIO_PDE_GPIO         0x3F
+
+#define MAX77620_AME_GPIO              0x40
+#define MAX77620_REG_ONOFF_CFG1                0x41
+#define MAX77620_REG_ONOFF_CFG2                0x42
+
+#define MAX77620_CID0_REG              0x58
+#define MAX77620_CID1_REG              0x59
+#define MAX77620_CID2_REG              0x5A
+#define MAX77620_CID3_REG              0x5B
+#define MAX77620_CID4_REG              0x5C
+#define MAX77620_CID5_REG              0x5D
+
+#define I2C_SEND_2_BYTES       0x0A02
+
+void pmic_enable_cpu_vdd(void);
+
+#endif /* _MAX77620_INIT_H_ */

diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
new file mode 100644 (file)
index 0000000..fc710c1
--- /dev/null
+++ b/board/nvidia/p2571/p2571.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-p2571.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+       pinmux_clear_tristate_input_clamping();
+
+       gpio_config_table(p2571_gpio_inits,
+                         ARRAY_SIZE(p2571_gpio_inits));
+
+       pinmux_config_pingrp_table(p2571_pingrps,
+                                  ARRAY_SIZE(p2571_pingrps));
+
+       pinmux_config_drvgrp_table(p2571_drvgrps,
+                                  ARRAY_SIZE(p2571_drvgrps));
+}

diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h
new file mode 100644 (file)
index 0000000..ac414f0
--- /dev/null
+++ b/board/nvidia/p2571/pinmux-config-p2571.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_P2571_H_
+#define _PINMUX_CONFIG_P2571_H_
+
+#define GPIO_INIT(_gpio, _init)                                \
+       {                                               \
+               .gpio   = GPIO_P##_gpio,                \
+               .init   = TEGRA_GPIO_INIT_##_init,      \
+       }
+
+static const struct tegra_gpio_config p2571_gpio_inits[] = {
+       /*        gpio, init_val */
+       GPIO_INIT(A0,   IN),
+       GPIO_INIT(A5,   IN),
+       GPIO_INIT(D4,   IN),
+       GPIO_INIT(E4,   OUT0),
+       GPIO_INIT(G0,   IN),
+       GPIO_INIT(H0,   OUT0),
+       GPIO_INIT(H2,   IN),
+       GPIO_INIT(H3,   OUT0),
+       GPIO_INIT(H4,   OUT0),
+       GPIO_INIT(H5,   IN),
+       GPIO_INIT(I0,   OUT0),
+       GPIO_INIT(I1,   IN),
+       GPIO_INIT(V1,   OUT0),
+       GPIO_INIT(V6,   OUT1),
+       GPIO_INIT(X4,   IN),
+       GPIO_INIT(X6,   IN),
+       GPIO_INIT(X7,   IN),
+       GPIO_INIT(Y1,   IN),
+       GPIO_INIT(Z0,   IN),
+       GPIO_INIT(Z4,   OUT0),
+       GPIO_INIT(BB2,  OUT0),
+       GPIO_INIT(CC1,  IN),
+       GPIO_INIT(CC3,  IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
+       {                                                       \
+               .pingrp         = PMUX_PINGRP_##_pingrp,        \
+               .func           = PMUX_FUNC_##_mux,             \
+               .pull           = PMUX_PULL_##_pull,            \
+               .tristate       = PMUX_TRI_##_tri,              \
+               .io             = PMUX_PIN_##_io,               \
+               .od             = PMUX_PIN_OD_##_od,            \
+               .e_io_hv        = PMUX_PIN_E_IO_HV_##_e_io_hv,  \
+               .lock           = PMUX_PIN_LOCK_DEFAULT,        \
+       }
+
+static const struct pmux_pingrp_config p2571_pingrps[] = {
+       /*     pingrp,               mux,      pull,   tri,      e_input, od,      e_io_hv */
+       PINCFG(PEX_L0_RST_N_PA0,     DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, NORMAL),
+       PINCFG(PEX_L0_CLKREQ_N_PA1,  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
+       PINCFG(PEX_WAKE_N_PA2,       RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
+       PINCFG(PEX_L1_RST_N_PA3,     RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
+       PINCFG(PEX_L1_CLKREQ_N_PA4,  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
+       PINCFG(SATA_LED_ACTIVE_PA5,  DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(PA6,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(DAP1_FS_PB0,          RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(DAP1_DIN_PB1,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(DAP1_DOUT_PB2,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(DAP1_SCLK_PB3,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI2_MOSI_PB4,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI2_MISO_PB5,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI2_SCK_PB6,         RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI2_CS0_PB7,         RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI1_MOSI_PC0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI1_MISO_PC1,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI1_SCK_PC2,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI1_CS0_PC3,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI1_CS1_PC4,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI4_SCK_PC5,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI4_CS0_PC6,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI4_MOSI_PC7,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPI4_MISO_PD0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART3_TX_PD1,         RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART3_RX_PD2,         RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART3_RTS_PD3,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART3_CTS_PD4,        DEFAULT,  NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DMIC1_CLK_PE0,        I2S3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DMIC1_DAT_PE1,        I2S3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DMIC2_CLK_PE2,        I2S3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DMIC2_DAT_PE3,        I2S3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DMIC3_CLK_PE4,        DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(DMIC3_DAT_PE5,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PE6,                  RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PE7,                  PWM3,     NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(GEN3_I2C_SCL_PF0,     I2C3,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
+       PINCFG(GEN3_I2C_SDA_PF1,     I2C3,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
+       PINCFG(UART2_TX_PG0,         DEFAULT,  NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(UART2_RX_PG1,         UARTB,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART2_RTS_PG2,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART2_CTS_PG3,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(WIFI_EN_PH0,          DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(WIFI_RST_PH1,         RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(WIFI_WAKE_AP_PH2,     DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(AP_WAKE_BT_PH3,       DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(BT_RST_PH4,           DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(BT_WAKE_AP_PH5,       DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(PH6,                  RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(AP_WAKE_NFC_PH7,      RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(NFC_EN_PI0,           DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(NFC_INT_PI1,          DEFAULT,  NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(GPS_EN_PI2,           RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(GPS_RST_PI3,          RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART4_TX_PI4,         UARTD,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART4_RX_PI5,         UARTD,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(UART4_RTS_PI6,        UARTD,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART4_CTS_PI7,        UARTD,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(GEN1_I2C_SDA_PJ0,     I2C1,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
+       PINCFG(GEN1_I2C_SCL_PJ1,     I2C1,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
+       PINCFG(GEN2_I2C_SCL_PJ2,     I2C2,     NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
+       PINCFG(GEN2_I2C_SDA_PJ3,     I2C2,     NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
+       PINCFG(DAP4_FS_PJ4,          RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(DAP4_DIN_PJ5,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(DAP4_DOUT_PJ6,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(DAP4_SCLK_PJ7,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PK0,                  RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PK1,                  RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PK2,                  RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PK3,                  RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PK4,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PK5,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PK6,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PK7,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PL0,                  RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PL1,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SDMMC1_CLK_PM0,       SDMMC1,   NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC1_CMD_PM1,       SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC1_DAT3_PM2,      SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC1_DAT2_PM3,      SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC1_DAT1_PM4,      SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC1_DAT0_PM5,      SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC3_CLK_PP0,       SDMMC3,   NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC3_CMD_PP1,       SDMMC3,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC3_DAT3_PP2,      SDMMC3,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC3_DAT2_PP3,      SDMMC3,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC3_DAT1_PP4,      SDMMC3,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC3_DAT0_PP5,      SDMMC3,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(CAM1_MCLK_PS0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CAM2_MCLK_PS1,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CAM_I2C_SCL_PS2,      I2CVI,    NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
+       PINCFG(CAM_I2C_SDA_PS3,      I2CVI,    NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
+       PINCFG(CAM_RST_PS4,          RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CAM_AF_EN_PS5,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CAM_FLASH_EN_PS6,     RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CAM1_PWDN_PS7,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CAM2_PWDN_PT0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CAM1_STROBE_PT1,      RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART1_TX_PU0,         UARTA,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART1_RX_PU1,         UARTA,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(UART1_RTS_PU2,        UARTA,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(UART1_CTS_PU3,        UARTA,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(LCD_BL_PWM_PV0,       PWM0,     NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(LCD_BL_EN_PV1,        DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(LCD_RST_PV2,          RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(LCD_GPIO1_PV3,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(LCD_GPIO2_PV4,        PWM1,     NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(AP_READY_PV5,         RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(TOUCH_RST_PV6,        DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(TOUCH_CLK_PV7,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(MODEM_WAKE_AP_PX0,    RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(TOUCH_INT_PX1,        RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(MOTION_INT_PX2,       RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(ALS_PROX_INT_PX3,     RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(TEMP_ALERT_PX4,       DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(BUTTON_POWER_ON_PX5,  RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(BUTTON_VOL_UP_PX6,    DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(BUTTON_VOL_DOWN_PX7,  DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(BUTTON_SLIDE_SW_PY0,  RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(BUTTON_HOME_PY1,      DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(LCD_TE_PY2,           RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PWR_I2C_SCL_PY3,      I2CPMU,   NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
+       PINCFG(PWR_I2C_SDA_PY4,      I2CPMU,   NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
+       PINCFG(CLK_32K_OUT_PY5,      SOC,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(PZ0,                  DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(PZ1,                  SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(PZ2,                  RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PZ3,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PZ4,                  DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PZ5,                  SOC,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DAP2_FS_PAA0,         I2S2,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DAP2_SCLK_PAA1,       I2S2,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DAP2_DIN_PAA2,        I2S2,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DAP2_DOUT_PAA3,       I2S2,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(AUD_MCLK_PBB0,        AUD,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(DVFS_PWM_PBB1,        CLDVFS,   NORMAL, TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(DVFS_CLK_PBB2,        DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(GPIO_X1_AUD_PBB3,     RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(GPIO_X3_AUD_PBB4,     RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(HDMI_CEC_PCC0,        CEC,      NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
+       PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT,  DOWN,   NORMAL,   INPUT,   DISABLE, NORMAL),
+       PINCFG(SPDIF_OUT_PCC2,       RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SPDIF_IN_PCC3,        DEFAULT,  NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(USB_VBUS_EN0_PCC4,    USB,      NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
+       PINCFG(USB_VBUS_EN1_PCC5,    USB,      NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
+       PINCFG(DP_HPD0_PCC6,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PCC7,                 RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
+       PINCFG(SPI2_CS1_PDD0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(QSPI_SCK_PEE0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(QSPI_CS_N_PEE1,       RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(QSPI_IO0_PEE2,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(QSPI_IO1_PEE3,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(QSPI_IO2_PEE4,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(QSPI_IO3_PEE5,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CORE_PWR_REQ,         CORE,     NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CPU_PWR_REQ,          CPU,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PWR_INT_N,            PMI,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(CLK_32K_IN,           CLK,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(JTAG_RTCK,            JTAG,     NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CLK_REQ,              SYS,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(SHUTDOWN,             SHUTDOWN, NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+       {                                               \
+               .drvgrp = PMUX_DRVGRP_##_drvgrp,        \
+               .slwf   = _slwf,                        \
+               .slwr   = _slwr,                        \
+               .drvup  = _drvup,                       \
+               .drvdn  = _drvdn,                       \
+               .lpmd   = PMUX_LPMD_##_lpmd,            \
+               .schmt  = PMUX_SCHMT_##_schmt,          \
+               .hsm    = PMUX_HSM_##_hsm,              \
+       }
+
+static const struct pmux_drvgrp_config p2571_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_P2571_H */

diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
new file mode 100644 (file)
index 0000000..8494bb5
--- /dev/null
+++ b/configs/p2571_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA210=y
+CONFIG_TARGET_P2571=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y

diff --git a/include/configs/p2571.h b/include/configs/p2571.h
new file mode 100644 (file)
index 0000000..77faf5f
--- /dev/null
+++ b/include/configs/p2571.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _P2571_H
+#define _P2571_H
+
+#include <linux/sizes.h>
+
+/* enable PMIC */
+#define CONFIG_MAX77620_POWER
+
+#include "tegra210-common.h"
+
+/* High-level configuration options */
+#define V_PROMPT                       "Tegra210 (P2571) # "
+#define CONFIG_TEGRA_BOARD_STRING      "NVIDIA P2571"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTA_BASE
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_CMD_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_SYS_MMC_ENV_PART                2
+#define CONFIG_ENV_OFFSET              (-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_TEGRA114_SPI            /* Compatible w/ Tegra114 SPI */
+#define CONFIG_TEGRA114_SPI_CTRLS      6
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED                24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB2.0 Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_DHCP
+
+/*
+ * TODO(twarren@nvidia.com) - add tegra-common-usb-gadget.h back
+ * breaks 64-bit build in ci_udc.c
+ */
+#include "tegra-common-post.h"
+
+#define COUNTER_FREQUENCY      38400000
+
+#endif /* _P2571_H */

diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
new file mode 100644 (file)
index 0000000..0348d47
--- /dev/null
+++ b/include/configs/tegra210-common.h
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA210_COMMON_H_
+#define _TEGRA210_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A57 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE      64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK          408000000       /* 408MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE       0x82800000      /* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE   0x8010E000
+
+/* Generic Interrupt Controller */
+#define CONFIG_GICV2
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x81000000
+#define MEM_LAYOUT_ENV_SETTINGS \
+       "scriptaddr=0x90000000\0" \
+       "pxefile_addr_r=0x90100000\0" \
+       "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+       "fdt_addr_r=0x82000000\0" \
+       "ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE           0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START    0x80090000
+#define CONFIG_SPL_STACK               0x800ffffc
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH  0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+
+#endif /* _TEGRA210_COMMON_H_ */