--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APQ_GCC_8084 is not set
+# CONFIG_APQ_MMCC_8084 is not set
+CONFIG_AR40XX_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_IPQ40XX=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+# CONFIG_ARCH_MDM9615 is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MSM8960 is not set
+# CONFIG_ARCH_MSM8974 is not set
+# CONFIG_ARCH_MSM8X60 is not set
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_CPUIDLE=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_CRYPTO=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
+# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
+# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AT803X_PHY=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BCH=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_CMDLINE_PARSER=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_QCOM=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRYPTO_AES_ARM=y
+CONFIG_CRYPTO_AES_ARM_BS=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_QCE=y
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
+CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
+CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
+CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
+CONFIG_CRYPTO_DEV_QCOM_RNG=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ESSEDMA=y
+CONFIG_EXTCON=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_74X164=y
+CONFIG_GPIO_WATCHDOG=y
+CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_OPTEE=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+# CONFIG_I2C_QCOM_CCI is not set
+CONFIG_I2C_QUP=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IO_URING=y
+# CONFIG_IPQ_APSS_PLL is not set
+CONFIG_IPQ_GCC_4019=y
+# CONFIG_IPQ_GCC_6018 is not set
+# CONFIG_IPQ_GCC_806X is not set
+# CONFIG_IPQ_GCC_8074 is not set
+# CONFIG_IPQ_LCC_806X is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_KPSS_XCC is not set
+# CONFIG_KRAITCC is not set
+CONFIG_LEDS_LP5523=y
+CONFIG_LEDS_LP5562=y
+CONFIG_LEDS_LP55XX_COMMON=y
+CONFIG_LEDS_TLC591XX=y
+CONFIG_LIBFDT=y
+CONFIG_LLD_VERSION=0
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_IPQ4019=y
+# CONFIG_MDM_GCC_9615 is not set
+# CONFIG_MDM_LCC_9615 is not set
+CONFIG_MEMFD_CREATE=y
+# CONFIG_MFD_HI6421_SPMI is not set
+# CONFIG_MFD_QCOM_RPM is not set
+# CONFIG_MFD_SPMI_PMIC is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_MSM=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MSM_GCC_8660 is not set
+# CONFIG_MSM_GCC_8916 is not set
+# CONFIG_MSM_GCC_8939 is not set
+# CONFIG_MSM_GCC_8960 is not set
+# CONFIG_MSM_GCC_8974 is not set
+# CONFIG_MSM_GCC_8994 is not set
+# CONFIG_MSM_GCC_8996 is not set
+# CONFIG_MSM_GCC_8998 is not set
+# CONFIG_MSM_GPUCC_8998 is not set
+# CONFIG_MSM_LCC_8960 is not set
+# CONFIG_MSM_MMCC_8960 is not set
+# CONFIG_MSM_MMCC_8974 is not set
+# CONFIG_MSM_MMCC_8996 is not set
+# CONFIG_MSM_MMCC_8998 is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_BCH=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_SPLIT_WRGG_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NLS=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OPTEE=y
+CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+# CONFIG_PHY_QCOM_APQ8064_SATA is not set
+CONFIG_PHY_QCOM_IPQ4019_USB=y
+# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
+# CONFIG_PHY_QCOM_IPQ806X_USB is not set
+# CONFIG_PHY_QCOM_PCIE2 is not set
+# CONFIG_PHY_QCOM_QMP is not set
+# CONFIG_PHY_QCOM_QUSB2 is not set
+# CONFIG_PHY_QCOM_USB_HS_28NM is not set
+# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
+# CONFIG_PHY_QCOM_USB_SS is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_APQ8064 is not set
+# CONFIG_PINCTRL_APQ8084 is not set
+CONFIG_PINCTRL_IPQ4019=y
+# CONFIG_PINCTRL_IPQ6018 is not set
+# CONFIG_PINCTRL_IPQ8064 is not set
+# CONFIG_PINCTRL_IPQ8074 is not set
+# CONFIG_PINCTRL_MDM9615 is not set
+CONFIG_PINCTRL_MSM=y
+# CONFIG_PINCTRL_MSM8226 is not set
+# CONFIG_PINCTRL_MSM8660 is not set
+# CONFIG_PINCTRL_MSM8916 is not set
+# CONFIG_PINCTRL_MSM8960 is not set
+# CONFIG_PINCTRL_MSM8976 is not set
+# CONFIG_PINCTRL_MSM8994 is not set
+# CONFIG_PINCTRL_MSM8996 is not set
+# CONFIG_PINCTRL_MSM8998 is not set
+# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
+# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
+# CONFIG_PINCTRL_QCS404 is not set
+# CONFIG_PINCTRL_SC7180 is not set
+# CONFIG_PINCTRL_SDM660 is not set
+# CONFIG_PINCTRL_SDM845 is not set
+# CONFIG_PINCTRL_SM8150 is not set
+# CONFIG_PINCTRL_SM8250 is not set
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_QCA807X_PHY=y
+CONFIG_QCOM_A53PLL=y
+CONFIG_QCOM_BAM_DMA=y
+# CONFIG_QCOM_COMMAND_DB is not set
+# CONFIG_QCOM_CPR is not set
+# CONFIG_QCOM_EBI2 is not set
+# CONFIG_QCOM_GENI_SE is not set
+# CONFIG_QCOM_GSBI is not set
+# CONFIG_QCOM_HFPLL is not set
+# CONFIG_QCOM_IOMMU is not set
+# CONFIG_QCOM_LLCC is not set
+# CONFIG_QCOM_OCMEM is not set
+# CONFIG_QCOM_PDC is not set
+CONFIG_QCOM_QFPROM=y
+# CONFIG_QCOM_RMTFS_MEM is not set
+# CONFIG_QCOM_RPMH is not set
+CONFIG_QCOM_SCM=y
+# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
+CONFIG_QCOM_SMEM=y
+# CONFIG_QCOM_SMSM is not set
+# CONFIG_QCOM_SOCINFO is not set
+CONFIG_QCOM_TCSR=y
+# CONFIG_QCOM_TSENS is not set
+CONFIG_QCOM_WDT=y
+# CONFIG_QCS_GCC_404 is not set
+# CONFIG_QCS_Q6SSTOP_404 is not set
+# CONFIG_QCS_TURING_404 is not set
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+CONFIG_REGULATOR_VCTRL=y
+CONFIG_REGULATOR_VQMMC_IPQ4019=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_QCOM_AOSS is not set
+# CONFIG_RESET_QCOM_PDC is not set
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SC_DISPCC_7180 is not set
+# CONFIG_SC_GCC_7180 is not set
+# CONFIG_SC_GPUCC_7180 is not set
+# CONFIG_SC_LPASS_CORECC_7180 is not set
+# CONFIG_SC_MSS_7180 is not set
+# CONFIG_SC_VIDEOCC_7180 is not set
+# CONFIG_SDM_CAMCC_845 is not set
+# CONFIG_SDM_DISPCC_845 is not set
+# CONFIG_SDM_GCC_660 is not set
+# CONFIG_SDM_GCC_845 is not set
+# CONFIG_SDM_GPUCC_845 is not set
+# CONFIG_SDM_LPASSCC_845 is not set
+# CONFIG_SDM_VIDEOCC_845 is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+# CONFIG_SM_GCC_8150 is not set
+# CONFIG_SM_GCC_8250 is not set
+# CONFIG_SM_GPUCC_8150 is not set
+# CONFIG_SM_GPUCC_8250 is not set
+# CONFIG_SM_VIDEOCC_8150 is not set
+# CONFIG_SM_VIDEOCC_8250 is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+CONFIG_SPMI_MSM_PMIC_ARB=y
+# CONFIG_SPMI_PMIC_CLKDIV is not set
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TEE=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/bitops.h>
+#include <linux/switch.h>
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/lockdep.h>
+#include <linux/workqueue.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/of_mdio.h>
+#include <linux/mdio.h>
+#include <linux/gpio.h>
+
+#include "ar40xx.h"
+
+static struct ar40xx_priv *ar40xx_priv;
+
+#define MIB_DESC(_s , _o, _n) \
+ { \
+ .size = (_s), \
+ .offset = (_o), \
+ .name = (_n), \
+ }
+
+static const struct ar40xx_mib_desc ar40xx_mibs[] = {
+ MIB_DESC(1, AR40XX_STATS_RXBROAD, "RxBroad"),
+ MIB_DESC(1, AR40XX_STATS_RXPAUSE, "RxPause"),
+ MIB_DESC(1, AR40XX_STATS_RXMULTI, "RxMulti"),
+ MIB_DESC(1, AR40XX_STATS_RXFCSERR, "RxFcsErr"),
+ MIB_DESC(1, AR40XX_STATS_RXALIGNERR, "RxAlignErr"),
+ MIB_DESC(1, AR40XX_STATS_RXRUNT, "RxRunt"),
+ MIB_DESC(1, AR40XX_STATS_RXFRAGMENT, "RxFragment"),
+ MIB_DESC(1, AR40XX_STATS_RX64BYTE, "Rx64Byte"),
+ MIB_DESC(1, AR40XX_STATS_RX128BYTE, "Rx128Byte"),
+ MIB_DESC(1, AR40XX_STATS_RX256BYTE, "Rx256Byte"),
+ MIB_DESC(1, AR40XX_STATS_RX512BYTE, "Rx512Byte"),
+ MIB_DESC(1, AR40XX_STATS_RX1024BYTE, "Rx1024Byte"),
+ MIB_DESC(1, AR40XX_STATS_RX1518BYTE, "Rx1518Byte"),
+ MIB_DESC(1, AR40XX_STATS_RXMAXBYTE, "RxMaxByte"),
+ MIB_DESC(1, AR40XX_STATS_RXTOOLONG, "RxTooLong"),
+ MIB_DESC(2, AR40XX_STATS_RXGOODBYTE, "RxGoodByte"),
+ MIB_DESC(2, AR40XX_STATS_RXBADBYTE, "RxBadByte"),
+ MIB_DESC(1, AR40XX_STATS_RXOVERFLOW, "RxOverFlow"),
+ MIB_DESC(1, AR40XX_STATS_FILTERED, "Filtered"),
+ MIB_DESC(1, AR40XX_STATS_TXBROAD, "TxBroad"),
+ MIB_DESC(1, AR40XX_STATS_TXPAUSE, "TxPause"),
+ MIB_DESC(1, AR40XX_STATS_TXMULTI, "TxMulti"),
+ MIB_DESC(1, AR40XX_STATS_TXUNDERRUN, "TxUnderRun"),
+ MIB_DESC(1, AR40XX_STATS_TX64BYTE, "Tx64Byte"),
+ MIB_DESC(1, AR40XX_STATS_TX128BYTE, "Tx128Byte"),
+ MIB_DESC(1, AR40XX_STATS_TX256BYTE, "Tx256Byte"),
+ MIB_DESC(1, AR40XX_STATS_TX512BYTE, "Tx512Byte"),
+ MIB_DESC(1, AR40XX_STATS_TX1024BYTE, "Tx1024Byte"),
+ MIB_DESC(1, AR40XX_STATS_TX1518BYTE, "Tx1518Byte"),
+ MIB_DESC(1, AR40XX_STATS_TXMAXBYTE, "TxMaxByte"),
+ MIB_DESC(1, AR40XX_STATS_TXOVERSIZE, "TxOverSize"),
+ MIB_DESC(2, AR40XX_STATS_TXBYTE, "TxByte"),
+ MIB_DESC(1, AR40XX_STATS_TXCOLLISION, "TxCollision"),
+ MIB_DESC(1, AR40XX_STATS_TXABORTCOL, "TxAbortCol"),
+ MIB_DESC(1, AR40XX_STATS_TXMULTICOL, "TxMultiCol"),
+ MIB_DESC(1, AR40XX_STATS_TXSINGLECOL, "TxSingleCol"),
+ MIB_DESC(1, AR40XX_STATS_TXEXCDEFER, "TxExcDefer"),
+ MIB_DESC(1, AR40XX_STATS_TXDEFER, "TxDefer"),
+ MIB_DESC(1, AR40XX_STATS_TXLATECOL, "TxLateCol"),
+};
+
+static u32
+ar40xx_read(struct ar40xx_priv *priv, int reg)
+{
+ return readl(priv->hw_addr + reg);
+}
+
+static u32
+ar40xx_psgmii_read(struct ar40xx_priv *priv, int reg)
+{
+ return readl(priv->psgmii_hw_addr + reg);
+}
+
+static void
+ar40xx_write(struct ar40xx_priv *priv, int reg, u32 val)
+{
+ writel(val, priv->hw_addr + reg);
+}
+
+static u32
+ar40xx_rmw(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)
+{
+ u32 ret;
+
+ ret = ar40xx_read(priv, reg);
+ ret &= ~mask;
+ ret |= val;
+ ar40xx_write(priv, reg, ret);
+ return ret;
+}
+
+static void
+ar40xx_psgmii_write(struct ar40xx_priv *priv, int reg, u32 val)
+{
+ writel(val, priv->psgmii_hw_addr + reg);
+}
+
+static void
+ar40xx_phy_dbg_write(struct ar40xx_priv *priv, int phy_addr,
+ u16 dbg_addr, u16 dbg_data)
+{
+ struct mii_bus *bus = priv->mii_bus;
+
+ mutex_lock(&bus->mdio_lock);
+ bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);
+ bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA, dbg_data);
+ mutex_unlock(&bus->mdio_lock);
+}
+
+static void
+ar40xx_phy_dbg_read(struct ar40xx_priv *priv, int phy_addr,
+ u16 dbg_addr, u16 *dbg_data)
+{
+ struct mii_bus *bus = priv->mii_bus;
+
+ mutex_lock(&bus->mdio_lock);
+ bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);
+ *dbg_data = bus->read(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA);
+ mutex_unlock(&bus->mdio_lock);
+}
+
+static void
+ar40xx_phy_mmd_write(struct ar40xx_priv *priv, u32 phy_id,
+ u16 mmd_num, u16 reg_id, u16 reg_val)
+{
+ struct mii_bus *bus = priv->mii_bus;
+
+ mutex_lock(&bus->mdio_lock);
+ bus->write(bus, phy_id,
+ AR40XX_MII_ATH_MMD_ADDR, mmd_num);
+ bus->write(bus, phy_id,
+ AR40XX_MII_ATH_MMD_DATA, reg_id);
+ bus->write(bus, phy_id,
+ AR40XX_MII_ATH_MMD_ADDR,
+ 0x4000 | mmd_num);
+ bus->write(bus, phy_id,
+ AR40XX_MII_ATH_MMD_DATA, reg_val);
+ mutex_unlock(&bus->mdio_lock);
+}
+
+static u16
+ar40xx_phy_mmd_read(struct ar40xx_priv *priv, u32 phy_id,
+ u16 mmd_num, u16 reg_id)
+{
+ u16 value;
+ struct mii_bus *bus = priv->mii_bus;
+
+ mutex_lock(&bus->mdio_lock);
+ bus->write(bus, phy_id,
+ AR40XX_MII_ATH_MMD_ADDR, mmd_num);
+ bus->write(bus, phy_id,
+ AR40XX_MII_ATH_MMD_DATA, reg_id);
+ bus->write(bus, phy_id,
+ AR40XX_MII_ATH_MMD_ADDR,
+ 0x4000 | mmd_num);
+ value = bus->read(bus, phy_id, AR40XX_MII_ATH_MMD_DATA);
+ mutex_unlock(&bus->mdio_lock);
+ return value;
+}
+
+/* Start of swconfig support */
+
+static void
+ar40xx_phy_poll_reset(struct ar40xx_priv *priv)
+{
+ u32 i, in_reset, retries = 500;
+ struct mii_bus *bus = priv->mii_bus;
+
+ /* Assume RESET was recently issued to some or all of the phys */
+ in_reset = GENMASK(AR40XX_NUM_PHYS - 1, 0);
+
+ while (retries--) {
+ /* 1ms should be plenty of time.
+ * 802.3 spec allows for a max wait time of 500ms
+ */
+ usleep_range(1000, 2000);
+
+ for (i = 0; i < AR40XX_NUM_PHYS; i++) {
+ int val;
+
+ /* skip devices which have completed reset */
+ if (!(in_reset & BIT(i)))
+ continue;
+
+ val = mdiobus_read(bus, i, MII_BMCR);
+ if (val < 0)
+ continue;
+
+ /* mark when phy is no longer in reset state */
+ if (!(val & BMCR_RESET))
+ in_reset &= ~BIT(i);
+ }
+
+ if (!in_reset)
+ return;
+ }
+
+ dev_warn(&bus->dev, "Failed to reset all phys! (in_reset: 0x%x)\n",
+ in_reset);
+}
+
+static void
+ar40xx_phy_init(struct ar40xx_priv *priv)
+{
+ int i;
+ struct mii_bus *bus;
+ u16 val;
+
+ bus = priv->mii_bus;
+ for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
+ ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);
+ val &= ~AR40XX_PHY_MANU_CTRL_EN;
+ ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);
+ mdiobus_write(bus, i,
+ MII_ADVERTISE, ADVERTISE_ALL |
+ ADVERTISE_PAUSE_CAP |
+ ADVERTISE_PAUSE_ASYM);
+ mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ }
+
+ ar40xx_phy_poll_reset(priv);
+}
+
+static void
+ar40xx_port_phy_linkdown(struct ar40xx_priv *priv)
+{
+ struct mii_bus *bus;
+ int i;
+ u16 val;
+
+ bus = priv->mii_bus;
+ for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
+ mdiobus_write(bus, i, MII_CTRL1000, 0);
+ mdiobus_write(bus, i, MII_ADVERTISE, 0);
+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);
+ val |= AR40XX_PHY_MANU_CTRL_EN;
+ ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);
+ /* disable transmit */
+ ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_2, &val);
+ val &= 0xf00f;
+ ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_2, val);
+ }
+}
+
+static void
+ar40xx_set_mirror_regs(struct ar40xx_priv *priv)
+{
+ int port;
+
+ /* reset all mirror registers */
+ ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,
+ AR40XX_FWD_CTRL0_MIRROR_PORT,
+ (0xF << AR40XX_FWD_CTRL0_MIRROR_PORT_S));
+ for (port = 0; port < AR40XX_NUM_PORTS; port++) {
+ ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(port),
+ AR40XX_PORT_LOOKUP_ING_MIRROR_EN, 0);
+
+ ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(port),
+ AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN, 0);
+ }
+
+ /* now enable mirroring if necessary */
+ if (priv->source_port >= AR40XX_NUM_PORTS ||
+ priv->monitor_port >= AR40XX_NUM_PORTS ||
+ priv->source_port == priv->monitor_port) {
+ return;
+ }
+
+ ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,
+ AR40XX_FWD_CTRL0_MIRROR_PORT,
+ (priv->monitor_port << AR40XX_FWD_CTRL0_MIRROR_PORT_S));
+
+ if (priv->mirror_rx)
+ ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(priv->source_port), 0,
+ AR40XX_PORT_LOOKUP_ING_MIRROR_EN);
+
+ if (priv->mirror_tx)
+ ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(priv->source_port),
+ 0, AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN);
+}
+
+static int
+ar40xx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+ u8 ports = priv->vlan_table[val->port_vlan];
+ int i;
+
+ val->len = 0;
+ for (i = 0; i < dev->ports; i++) {
+ struct switch_port *p;
+
+ if (!(ports & BIT(i)))
+ continue;
+
+ p = &val->value.ports[val->len++];
+ p->id = i;
+ if ((priv->vlan_tagged & BIT(i)) ||
+ (priv->pvid[i] != val->port_vlan))
+ p->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
+ else
+ p->flags = 0;
+ }
+ return 0;
+}
+
+static int
+ar40xx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+ u8 *vt = &priv->vlan_table[val->port_vlan];
+ int i;
+
+ *vt = 0;
+ for (i = 0; i < val->len; i++) {
+ struct switch_port *p = &val->value.ports[i];
+
+ if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
+ if (val->port_vlan == priv->pvid[p->id])
+ priv->vlan_tagged |= BIT(p->id);
+ } else {
+ priv->vlan_tagged &= ~BIT(p->id);
+ priv->pvid[p->id] = val->port_vlan;
+ }
+
+ *vt |= BIT(p->id);
+ }
+ return 0;
+}
+
+static int
+ar40xx_reg_wait(struct ar40xx_priv *priv, u32 reg, u32 mask, u32 val,
+ unsigned timeout)
+{
+ int i;
+
+ for (i = 0; i < timeout; i++) {
+ u32 t;
+
+ t = ar40xx_read(priv, reg);
+ if ((t & mask) == val)
+ return 0;
+
+ usleep_range(1000, 2000);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int
+ar40xx_mib_op(struct ar40xx_priv *priv, u32 op)
+{
+ int ret;
+
+ lockdep_assert_held(&priv->mib_lock);
+
+ /* Capture the hardware statistics for all ports */
+ ar40xx_rmw(priv, AR40XX_REG_MIB_FUNC,
+ AR40XX_MIB_FUNC, (op << AR40XX_MIB_FUNC_S));
+
+ /* Wait for the capturing to complete. */
+ ret = ar40xx_reg_wait(priv, AR40XX_REG_MIB_FUNC,
+ AR40XX_MIB_BUSY, 0, 10);
+
+ return ret;
+}
+
+static void
+ar40xx_mib_fetch_port_stat(struct ar40xx_priv *priv, int port, bool flush)
+{
+ unsigned int base;
+ u64 *mib_stats;
+ int i;
+ u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
+
+ WARN_ON(port >= priv->dev.ports);
+
+ lockdep_assert_held(&priv->mib_lock);
+
+ base = AR40XX_REG_PORT_STATS_START +
+ AR40XX_REG_PORT_STATS_LEN * port;
+
+ mib_stats = &priv->mib_stats[port * num_mibs];
+ if (flush) {
+ u32 len;
+
+ len = num_mibs * sizeof(*mib_stats);
+ memset(mib_stats, 0, len);
+ return;
+ }
+ for (i = 0; i < num_mibs; i++) {
+ const struct ar40xx_mib_desc *mib;
+ u64 t;
+
+ mib = &ar40xx_mibs[i];
+ t = ar40xx_read(priv, base + mib->offset);
+ if (mib->size == 2) {
+ u64 hi;
+
+ hi = ar40xx_read(priv, base + mib->offset + 4);
+ t |= hi << 32;
+ }
+
+ mib_stats[i] += t;
+ }
+}
+
+static int
+ar40xx_mib_capture(struct ar40xx_priv *priv)
+{
+ return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_CAPTURE);
+}
+
+static int
+ar40xx_mib_flush(struct ar40xx_priv *priv)
+{
+ return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_FLUSH);
+}
+
+static int
+ar40xx_sw_set_reset_mibs(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+ unsigned int len;
+ int ret;
+ u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
+
+ mutex_lock(&priv->mib_lock);
+
+ len = priv->dev.ports * num_mibs * sizeof(*priv->mib_stats);
+ memset(priv->mib_stats, 0, len);
+ ret = ar40xx_mib_flush(priv);
+
+ mutex_unlock(&priv->mib_lock);
+ return ret;
+}
+
+static int
+ar40xx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ priv->vlan = !!val->value.i;
+ return 0;
+}
+
+static int
+ar40xx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ val->value.i = priv->vlan;
+ return 0;
+}
+
+static int
+ar40xx_sw_set_mirror_rx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ priv->mirror_rx = !!val->value.i;
+ ar40xx_set_mirror_regs(priv);
+ mutex_unlock(&priv->reg_mutex);
+
+ return 0;
+}
+
+static int
+ar40xx_sw_get_mirror_rx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ val->value.i = priv->mirror_rx;
+ mutex_unlock(&priv->reg_mutex);
+ return 0;
+}
+
+static int
+ar40xx_sw_set_mirror_tx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ priv->mirror_tx = !!val->value.i;
+ ar40xx_set_mirror_regs(priv);
+ mutex_unlock(&priv->reg_mutex);
+
+ return 0;
+}
+
+static int
+ar40xx_sw_get_mirror_tx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ val->value.i = priv->mirror_tx;
+ mutex_unlock(&priv->reg_mutex);
+ return 0;
+}
+
+static int
+ar40xx_sw_set_mirror_monitor_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ priv->monitor_port = val->value.i;
+ ar40xx_set_mirror_regs(priv);
+ mutex_unlock(&priv->reg_mutex);
+
+ return 0;
+}
+
+static int
+ar40xx_sw_get_mirror_monitor_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ val->value.i = priv->monitor_port;
+ mutex_unlock(&priv->reg_mutex);
+ return 0;
+}
+
+static int
+ar40xx_sw_set_mirror_source_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ priv->source_port = val->value.i;
+ ar40xx_set_mirror_regs(priv);
+ mutex_unlock(&priv->reg_mutex);
+
+ return 0;
+}
+
+static int
+ar40xx_sw_get_mirror_source_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ val->value.i = priv->source_port;
+ mutex_unlock(&priv->reg_mutex);
+ return 0;
+}
+
+static int
+ar40xx_sw_set_linkdown(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ if (val->value.i == 1)
+ ar40xx_port_phy_linkdown(priv);
+ else
+ ar40xx_phy_init(priv);
+
+ return 0;
+}
+
+static int
+ar40xx_sw_set_port_reset_mib(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+ int port;
+ int ret;
+
+ port = val->port_vlan;
+ if (port >= dev->ports)
+ return -EINVAL;
+
+ mutex_lock(&priv->mib_lock);
+ ret = ar40xx_mib_capture(priv);
+ if (ret)
+ goto unlock;
+
+ ar40xx_mib_fetch_port_stat(priv, port, true);
+
+unlock:
+ mutex_unlock(&priv->mib_lock);
+ return ret;
+}
+
+static int
+ar40xx_sw_get_port_mib(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+ u64 *mib_stats;
+ int port;
+ int ret;
+ char *buf = priv->buf;
+ int i, len = 0;
+ u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
+
+ port = val->port_vlan;
+ if (port >= dev->ports)
+ return -EINVAL;
+
+ mutex_lock(&priv->mib_lock);
+ ret = ar40xx_mib_capture(priv);
+ if (ret)
+ goto unlock;
+
+ ar40xx_mib_fetch_port_stat(priv, port, false);
+
+ len += snprintf(buf + len, sizeof(priv->buf) - len,
+ "Port %d MIB counters\n",
+ port);
+
+ mib_stats = &priv->mib_stats[port * num_mibs];
+ for (i = 0; i < num_mibs; i++)
+ len += snprintf(buf + len, sizeof(priv->buf) - len,
+ "%-12s: %llu\n",
+ ar40xx_mibs[i].name,
+ mib_stats[i]);
+
+ val->value.s = buf;
+ val->len = len;
+
+unlock:
+ mutex_unlock(&priv->mib_lock);
+ return ret;
+}
+
+static int
+ar40xx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ priv->vlan_id[val->port_vlan] = val->value.i;
+ return 0;
+}
+
+static int
+ar40xx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ val->value.i = priv->vlan_id[val->port_vlan];
+ return 0;
+}
+
+static int
+ar40xx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+ *vlan = priv->pvid[port];
+ return 0;
+}
+
+static int
+ar40xx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ /* make sure no invalid PVIDs get set */
+ if (vlan >= dev->vlans)
+ return -EINVAL;
+
+ priv->pvid[port] = vlan;
+ return 0;
+}
+
+static void
+ar40xx_read_port_link(struct ar40xx_priv *priv, int port,
+ struct switch_port_link *link)
+{
+ u32 status;
+ u32 speed;
+
+ memset(link, 0, sizeof(*link));
+
+ status = ar40xx_read(priv, AR40XX_REG_PORT_STATUS(port));
+
+ link->aneg = !!(status & AR40XX_PORT_AUTO_LINK_EN);
+ if (link->aneg || (port != AR40XX_PORT_CPU))
+ link->link = !!(status & AR40XX_PORT_STATUS_LINK_UP);
+ else
+ link->link = true;
+
+ if (!link->link)
+ return;
+
+ link->duplex = !!(status & AR40XX_PORT_DUPLEX);
+ link->tx_flow = !!(status & AR40XX_PORT_STATUS_TXFLOW);
+ link->rx_flow = !!(status & AR40XX_PORT_STATUS_RXFLOW);
+
+ speed = (status & AR40XX_PORT_SPEED) >>
+ AR40XX_PORT_STATUS_SPEED_S;
+
+ switch (speed) {
+ case AR40XX_PORT_SPEED_10M:
+ link->speed = SWITCH_PORT_SPEED_10;
+ break;
+ case AR40XX_PORT_SPEED_100M:
+ link->speed = SWITCH_PORT_SPEED_100;
+ break;
+ case AR40XX_PORT_SPEED_1000M:
+ link->speed = SWITCH_PORT_SPEED_1000;
+ break;
+ default:
+ link->speed = SWITCH_PORT_SPEED_UNKNOWN;
+ break;
+ }
+}
+
+static int
+ar40xx_sw_get_port_link(struct switch_dev *dev, int port,
+ struct switch_port_link *link)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+
+ ar40xx_read_port_link(priv, port, link);
+ return 0;
+}
+
+static const struct switch_attr ar40xx_sw_attr_globals[] = {
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_vlan",
+ .description = "Enable VLAN mode",
+ .set = ar40xx_sw_set_vlan,
+ .get = ar40xx_sw_get_vlan,
+ .max = 1
+ },
+ {
+ .type = SWITCH_TYPE_NOVAL,
+ .name = "reset_mibs",
+ .description = "Reset all MIB counters",
+ .set = ar40xx_sw_set_reset_mibs,
+ },
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_mirror_rx",
+ .description = "Enable mirroring of RX packets",
+ .set = ar40xx_sw_set_mirror_rx_enable,
+ .get = ar40xx_sw_get_mirror_rx_enable,
+ .max = 1
+ },
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_mirror_tx",
+ .description = "Enable mirroring of TX packets",
+ .set = ar40xx_sw_set_mirror_tx_enable,
+ .get = ar40xx_sw_get_mirror_tx_enable,
+ .max = 1
+ },
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "mirror_monitor_port",
+ .description = "Mirror monitor port",
+ .set = ar40xx_sw_set_mirror_monitor_port,
+ .get = ar40xx_sw_get_mirror_monitor_port,
+ .max = AR40XX_NUM_PORTS - 1
+ },
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "mirror_source_port",
+ .description = "Mirror source port",
+ .set = ar40xx_sw_set_mirror_source_port,
+ .get = ar40xx_sw_get_mirror_source_port,
+ .max = AR40XX_NUM_PORTS - 1
+ },
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "linkdown",
+ .description = "Link down all the PHYs",
+ .set = ar40xx_sw_set_linkdown,
+ .max = 1
+ },
+};
+
+static const struct switch_attr ar40xx_sw_attr_port[] = {
+ {
+ .type = SWITCH_TYPE_NOVAL,
+ .name = "reset_mib",
+ .description = "Reset single port MIB counters",
+ .set = ar40xx_sw_set_port_reset_mib,
+ },
+ {
+ .type = SWITCH_TYPE_STRING,
+ .name = "mib",
+ .description = "Get port's MIB counters",
+ .set = NULL,
+ .get = ar40xx_sw_get_port_mib,
+ },
+};
+
+const struct switch_attr ar40xx_sw_attr_vlan[] = {
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "vid",
+ .description = "VLAN ID (0-4094)",
+ .set = ar40xx_sw_set_vid,
+ .get = ar40xx_sw_get_vid,
+ .max = 4094,
+ },
+};
+
+/* End of swconfig support */
+
+static int
+ar40xx_wait_bit(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)
+{
+ int timeout = 20;
+ u32 t;
+
+ while (1) {
+ t = ar40xx_read(priv, reg);
+ if ((t & mask) == val)
+ return 0;
+
+ if (timeout-- <= 0)
+ break;
+
+ usleep_range(10, 20);
+ }
+
+ pr_err("ar40xx: timeout for reg %08x: %08x & %08x != %08x\n",
+ (unsigned int)reg, t, mask, val);
+ return -ETIMEDOUT;
+}
+
+static int
+ar40xx_atu_flush(struct ar40xx_priv *priv)
+{
+ int ret;
+
+ ret = ar40xx_wait_bit(priv, AR40XX_REG_ATU_FUNC,
+ AR40XX_ATU_FUNC_BUSY, 0);
+ if (!ret)
+ ar40xx_write(priv, AR40XX_REG_ATU_FUNC,
+ AR40XX_ATU_FUNC_OP_FLUSH |
+ AR40XX_ATU_FUNC_BUSY);
+
+ return ret;
+}
+
+static void
+ar40xx_ess_reset(struct ar40xx_priv *priv)
+{
+ reset_control_assert(priv->ess_rst);
+ mdelay(10);
+ reset_control_deassert(priv->ess_rst);
+ /* Waiting for all inner tables init done.
+ * It cost 5~10ms.
+ */
+ mdelay(10);
+
+ pr_info("ESS reset ok!\n");
+}
+
+/* Start of psgmii self test */
+
+static void
+ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv)
+{
+ u32 n;
+ struct mii_bus *bus = priv->mii_bus;
+ /* reset phy psgmii */
+ /* fix phy psgmii RX 20bit */
+ mdiobus_write(bus, 5, 0x0, 0x005b);
+ /* reset phy psgmii */
+ mdiobus_write(bus, 5, 0x0, 0x001b);
+ /* release reset phy psgmii */
+ mdiobus_write(bus, 5, 0x0, 0x005b);
+
+ for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
+ u16 status;
+
+ status = ar40xx_phy_mmd_read(priv, 5, 1, 0x28);
+ if (status & BIT(0))
+ break;
+ /* Polling interval to check PSGMII PLL in malibu is ready
+ * the worst time is 8.67ms
+ * for 25MHz reference clock
+ * [512+(128+2048)*49]*80ns+100us
+ */
+ mdelay(2);
+ }
+
+ /*check malibu psgmii calibration done end..*/
+
+ /*freeze phy psgmii RX CDR*/
+ mdiobus_write(bus, 5, 0x1a, 0x2230);
+
+ ar40xx_ess_reset(priv);
+
+ /*check psgmii calibration done start*/
+ for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
+ u32 status;
+
+ status = ar40xx_psgmii_read(priv, 0xa0);
+ if (status & BIT(0))
+ break;
+ /* Polling interval to check PSGMII PLL in ESS is ready */
+ mdelay(2);
+ }
+
+ /* check dakota psgmii calibration done end..*/
+
+ /* relesae phy psgmii RX CDR */
+ mdiobus_write(bus, 5, 0x1a, 0x3230);
+ /* release phy psgmii RX 20bit */
+ mdiobus_write(bus, 5, 0x0, 0x005f);
+}
+
+static void
+ar40xx_psgmii_single_phy_testing(struct ar40xx_priv *priv, int phy)
+{
+ int j;
+ u32 tx_ok, tx_error;
+ u32 rx_ok, rx_error;
+ u32 tx_ok_high16;
+ u32 rx_ok_high16;
+ u32 tx_all_ok, rx_all_ok;
+ struct mii_bus *bus = priv->mii_bus;
+
+ mdiobus_write(bus, phy, 0x0, 0x9000);
+ mdiobus_write(bus, phy, 0x0, 0x4140);
+
+ for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
+ u16 status;
+
+ status = mdiobus_read(bus, phy, 0x11);
+ if (status & AR40XX_PHY_SPEC_STATUS_LINK)
+ break;
+ /* the polling interval to check if the PHY link up or not
+ * maxwait_timer: 750 ms +/-10 ms
+ * minwait_timer : 1 us +/- 0.1us
+ * time resides in minwait_timer ~ maxwait_timer
+ * see IEEE 802.3 section 40.4.5.2
+ */
+ mdelay(8);
+ }
+
+ /* enable check */
+ ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0000);
+ ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0003);
+
+ /* start traffic */
+ ar40xx_phy_mmd_write(priv, phy, 7, 0x8020, 0xa000);
+ /* wait for all traffic end
+ * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
+ */
+ mdelay(50);
+
+ /* check counter */
+ tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);
+ tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);
+ tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);
+ rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);
+ rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);
+ rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);
+ tx_all_ok = tx_ok + (tx_ok_high16 << 16);
+ rx_all_ok = rx_ok + (rx_ok_high16 << 16);
+ if (tx_all_ok == 0x1000 && tx_error == 0) {
+ /* success */
+ priv->phy_t_status &= (~BIT(phy));
+ } else {
+ pr_info("PHY %d single test PSGMII issue happen!\n", phy);
+ priv->phy_t_status |= BIT(phy);
+ }
+
+ mdiobus_write(bus, phy, 0x0, 0x1840);
+}
+
+static void
+ar40xx_psgmii_all_phy_testing(struct ar40xx_priv *priv)
+{
+ int phy, j;
+ struct mii_bus *bus = priv->mii_bus;
+
+ mdiobus_write(bus, 0x1f, 0x0, 0x9000);
+ mdiobus_write(bus, 0x1f, 0x0, 0x4140);
+
+ for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
+ u16 status;
+
+ status = mdiobus_read(bus, phy, 0x11);
+ if (!(status & BIT(10)))
+ break;
+ }
+
+ if (phy >= (AR40XX_NUM_PORTS - 1))
+ break;
+ /* The polling interva to check if the PHY link up or not */
+ mdelay(8);
+ }
+ /* enable check */
+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0000);
+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0003);
+
+ /* start traffic */
+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0xa000);
+ /* wait for all traffic end
+ * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
+ */
+ mdelay(50);
+
+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
+ u32 tx_ok, tx_error;
+ u32 rx_ok, rx_error;
+ u32 tx_ok_high16;
+ u32 rx_ok_high16;
+ u32 tx_all_ok, rx_all_ok;
+
+ /* check counter */
+ tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);
+ tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);
+ tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);
+ rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);
+ rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);
+ rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);
+ tx_all_ok = tx_ok + (tx_ok_high16<<16);
+ rx_all_ok = rx_ok + (rx_ok_high16<<16);
+ if (tx_all_ok == 0x1000 && tx_error == 0) {
+ /* success */
+ priv->phy_t_status &= ~BIT(phy + 8);
+ } else {
+ pr_info("PHY%d test see issue!\n", phy);
+ priv->phy_t_status |= BIT(phy + 8);
+ }
+ }
+
+ pr_debug("PHY all test 0x%x \r\n", priv->phy_t_status);
+}
+
+void
+ar40xx_psgmii_self_test(struct ar40xx_priv *priv)
+{
+ u32 i, phy;
+ struct mii_bus *bus = priv->mii_bus;
+
+ ar40xx_malibu_psgmii_ess_reset(priv);
+
+ /* switch to access MII reg for copper */
+ mdiobus_write(bus, 4, 0x1f, 0x8500);
+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
+ /*enable phy mdio broadcast write*/
+ ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x801f);
+ }
+ /* force no link by power down */
+ mdiobus_write(bus, 0x1f, 0x0, 0x1840);
+ /*packet number*/
+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x1000);
+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8062, 0x05e0);
+
+ /*fix mdi status */
+ mdiobus_write(bus, 0x1f, 0x10, 0x6800);
+ for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {
+ priv->phy_t_status = 0;
+
+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
+ ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
+ AR40XX_PORT_LOOKUP_LOOPBACK,
+ AR40XX_PORT_LOOKUP_LOOPBACK);
+ }
+
+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++)
+ ar40xx_psgmii_single_phy_testing(priv, phy);
+
+ ar40xx_psgmii_all_phy_testing(priv);
+
+ if (priv->phy_t_status)
+ ar40xx_malibu_psgmii_ess_reset(priv);
+ else
+ break;
+ }
+
+ if (i >= AR40XX_PSGMII_CALB_NUM)
+ pr_info("PSGMII cannot recover\n");
+ else
+ pr_debug("PSGMII recovered after %d times reset\n", i);
+
+ /* configuration recover */
+ /* packet number */
+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x0);
+ /* disable check */
+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0);
+ /* disable traffic */
+ ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0x0);
+}
+
+void
+ar40xx_psgmii_self_test_clean(struct ar40xx_priv *priv)
+{
+ int phy;
+ struct mii_bus *bus = priv->mii_bus;
+
+ /* disable phy internal loopback */
+ mdiobus_write(bus, 0x1f, 0x10, 0x6860);
+ mdiobus_write(bus, 0x1f, 0x0, 0x9040);
+
+ for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
+ /* disable mac loop back */
+ ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
+ AR40XX_PORT_LOOKUP_LOOPBACK, 0);
+ /* disable phy mdio broadcast write */
+ ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x001f);
+ }
+
+ /* clear fdb entry */
+ ar40xx_atu_flush(priv);
+}
+
+/* End of psgmii self test */
+
+static void
+ar40xx_mac_mode_init(struct ar40xx_priv *priv, u32 mode)
+{
+ if (mode == PORT_WRAPPER_PSGMII) {
+ ar40xx_psgmii_write(priv, AR40XX_PSGMII_MODE_CONTROL, 0x2200);
+ ar40xx_psgmii_write(priv, AR40XX_PSGMIIPHY_TX_CONTROL, 0x8380);
+ }
+}
+
+static
+int ar40xx_cpuport_setup(struct ar40xx_priv *priv)
+{
+ u32 t;
+
+ t = AR40XX_PORT_STATUS_TXFLOW |
+ AR40XX_PORT_STATUS_RXFLOW |
+ AR40XX_PORT_TXHALF_FLOW |
+ AR40XX_PORT_DUPLEX |
+ AR40XX_PORT_SPEED_1000M;
+ ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);
+ usleep_range(10, 20);
+
+ t |= AR40XX_PORT_TX_EN |
+ AR40XX_PORT_RX_EN;
+ ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);
+
+ return 0;
+}
+
+static void
+ar40xx_init_port(struct ar40xx_priv *priv, int port)
+{
+ u32 t;
+
+ ar40xx_write(priv, AR40XX_REG_PORT_STATUS(port), 0);
+
+ ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
+
+ ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0);
+
+ t = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH << AR40XX_PORT_VLAN1_OUT_MODE_S;
+ ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
+
+ t = AR40XX_PORT_LOOKUP_LEARN;
+ t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
+ ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);
+}
+
+void
+ar40xx_init_globals(struct ar40xx_priv *priv)
+{
+ u32 t;
+
+ /* enable CPU port and disable mirror port */
+ t = AR40XX_FWD_CTRL0_CPU_PORT_EN |
+ AR40XX_FWD_CTRL0_MIRROR_PORT;
+ ar40xx_write(priv, AR40XX_REG_FWD_CTRL0, t);
+
+ /* forward multicast and broadcast frames to CPU */
+ t = (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_UC_FLOOD_S) |
+ (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_MC_FLOOD_S) |
+ (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_BC_FLOOD_S);
+ ar40xx_write(priv, AR40XX_REG_FWD_CTRL1, t);
+
+ /* enable jumbo frames */
+ ar40xx_rmw(priv, AR40XX_REG_MAX_FRAME_SIZE,
+ AR40XX_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
+
+ /* Enable MIB counters */
+ ar40xx_rmw(priv, AR40XX_REG_MODULE_EN, 0,
+ AR40XX_MODULE_EN_MIB);
+
+ /* Disable AZ */
+ ar40xx_write(priv, AR40XX_REG_EEE_CTRL, 0);
+
+ /* set flowctrl thershold for cpu port */
+ t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) |
+ AR40XX_PORT0_FC_THRESH_OFF_DFLT;
+ ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t);
+}
+
+static int
+ar40xx_hw_init(struct ar40xx_priv *priv)
+{
+ u32 i;
+
+ ar40xx_ess_reset(priv);
+
+ if (!priv->mii_bus)
+ return -1;
+
+ ar40xx_psgmii_self_test(priv);
+ ar40xx_psgmii_self_test_clean(priv);
+
+ ar40xx_mac_mode_init(priv, priv->mac_mode);
+
+ for (i = 0; i < priv->dev.ports; i++)
+ ar40xx_init_port(priv, i);
+
+ ar40xx_init_globals(priv);
+
+ return 0;
+}
+
+/* Start of qm error WAR */
+
+static
+int ar40xx_force_1g_full(struct ar40xx_priv *priv, u32 port_id)
+{
+ u32 reg;
+
+ if (port_id < 0 || port_id > 6)
+ return -1;
+
+ reg = AR40XX_REG_PORT_STATUS(port_id);
+ return ar40xx_rmw(priv, reg, AR40XX_PORT_SPEED,
+ (AR40XX_PORT_SPEED_1000M | AR40XX_PORT_DUPLEX));
+}
+
+static
+int ar40xx_get_qm_status(struct ar40xx_priv *priv,
+ u32 port_id, u32 *qm_buffer_err)
+{
+ u32 reg;
+ u32 qm_val;
+
+ if (port_id < 1 || port_id > 5) {
+ *qm_buffer_err = 0;
+ return -1;
+ }
+
+ if (port_id < 4) {
+ reg = AR40XX_REG_QM_PORT0_3_QNUM;
+ ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
+ qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
+ /* every 8 bits for each port */
+ *qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF;
+ } else {
+ reg = AR40XX_REG_QM_PORT4_6_QNUM;
+ ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
+ qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
+ /* every 8 bits for each port */
+ *qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF;
+ }
+
+ return 0;
+}
+
+static void
+ar40xx_sw_mac_polling_task(struct ar40xx_priv *priv)
+{
+ static int task_count;
+ u32 i;
+ u32 reg, value;
+ u32 link, speed, duplex;
+ u32 qm_buffer_err;
+ u16 port_phy_status[AR40XX_NUM_PORTS];
+ static u32 qm_err_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
+ static u32 link_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
+ struct mii_bus *bus = NULL;
+
+ if (!priv || !priv->mii_bus)
+ return;
+
+ bus = priv->mii_bus;
+
+ ++task_count;
+
+ for (i = 1; i < AR40XX_NUM_PORTS; ++i) {
+ port_phy_status[i] =
+ mdiobus_read(bus, i-1, AR40XX_PHY_SPEC_STATUS);
+
+ speed = FIELD_GET(AR40XX_PHY_SPEC_STATUS_SPEED,
+ port_phy_status[i]);
+ link = FIELD_GET(AR40XX_PHY_SPEC_STATUS_LINK,
+ port_phy_status[i]);
+ duplex = FIELD_GET(AR40XX_PHY_SPEC_STATUS_DUPLEX,
+ port_phy_status[i]);
+
+ if (link != priv->ar40xx_port_old_link[i]) {
+ ++link_cnt[i];
+ /* Up --> Down */
+ if ((priv->ar40xx_port_old_link[i] ==
+ AR40XX_PORT_LINK_UP) &&
+ (link == AR40XX_PORT_LINK_DOWN)) {
+ /* LINK_EN disable(MAC force mode)*/
+ reg = AR40XX_REG_PORT_STATUS(i);
+ ar40xx_rmw(priv, reg,
+ AR40XX_PORT_AUTO_LINK_EN, 0);
+
+ /* Check queue buffer */
+ qm_err_cnt[i] = 0;
+ ar40xx_get_qm_status(priv, i, &qm_buffer_err);
+ if (qm_buffer_err) {
+ priv->ar40xx_port_qm_buf[i] =
+ AR40XX_QM_NOT_EMPTY;
+ } else {
+ u16 phy_val = 0;
+
+ priv->ar40xx_port_qm_buf[i] =
+ AR40XX_QM_EMPTY;
+ ar40xx_force_1g_full(priv, i);
+ /* Ref:QCA8337 Datasheet,Clearing
+ * MENU_CTRL_EN prevents phy to
+ * stuck in 100BT mode when
+ * bringing up the link
+ */
+ ar40xx_phy_dbg_read(priv, i-1,
+ AR40XX_PHY_DEBUG_0,
+ &phy_val);
+ phy_val &= (~AR40XX_PHY_MANU_CTRL_EN);
+ ar40xx_phy_dbg_write(priv, i-1,
+ AR40XX_PHY_DEBUG_0,
+ phy_val);
+ }
+ priv->ar40xx_port_old_link[i] = link;
+ } else if ((priv->ar40xx_port_old_link[i] ==
+ AR40XX_PORT_LINK_DOWN) &&
+ (link == AR40XX_PORT_LINK_UP)) {
+ /* Down --> Up */
+ if (priv->port_link_up[i] < 1) {
+ ++priv->port_link_up[i];
+ } else {
+ /* Change port status */
+ reg = AR40XX_REG_PORT_STATUS(i);
+ value = ar40xx_read(priv, reg);
+ priv->port_link_up[i] = 0;
+
+ value &= ~(AR40XX_PORT_DUPLEX |
+ AR40XX_PORT_SPEED);
+ value |= speed | (duplex ? BIT(6) : 0);
+ ar40xx_write(priv, reg, value);
+ /* clock switch need such time
+ * to avoid glitch
+ */
+ usleep_range(100, 200);
+
+ value |= AR40XX_PORT_AUTO_LINK_EN;
+ ar40xx_write(priv, reg, value);
+ /* HW need such time to make sure link
+ * stable before enable MAC
+ */
+ usleep_range(100, 200);
+
+ if (speed == AR40XX_PORT_SPEED_100M) {
+ u16 phy_val = 0;
+ /* Enable @100M, if down to 10M
+ * clock will change smoothly
+ */
+ ar40xx_phy_dbg_read(priv, i-1,
+ 0,
+ &phy_val);
+ phy_val |=
+ AR40XX_PHY_MANU_CTRL_EN;
+ ar40xx_phy_dbg_write(priv, i-1,
+ 0,
+ phy_val);
+ }
+ priv->ar40xx_port_old_link[i] = link;
+ }
+ }
+ }
+
+ if (priv->ar40xx_port_qm_buf[i] == AR40XX_QM_NOT_EMPTY) {
+ /* Check QM */
+ ar40xx_get_qm_status(priv, i, &qm_buffer_err);
+ if (qm_buffer_err) {
+ ++qm_err_cnt[i];
+ } else {
+ priv->ar40xx_port_qm_buf[i] =
+ AR40XX_QM_EMPTY;
+ qm_err_cnt[i] = 0;
+ ar40xx_force_1g_full(priv, i);
+ }
+ }
+ }
+}
+
+static void
+ar40xx_qm_err_check_work_task(struct work_struct *work)
+{
+ struct ar40xx_priv *priv = container_of(work, struct ar40xx_priv,
+ qm_dwork.work);
+
+ mutex_lock(&priv->qm_lock);
+
+ ar40xx_sw_mac_polling_task(priv);
+
+ mutex_unlock(&priv->qm_lock);
+
+ schedule_delayed_work(&priv->qm_dwork,
+ msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
+}
+
+static int
+ar40xx_qm_err_check_work_start(struct ar40xx_priv *priv)
+{
+ mutex_init(&priv->qm_lock);
+
+ INIT_DELAYED_WORK(&priv->qm_dwork, ar40xx_qm_err_check_work_task);
+
+ schedule_delayed_work(&priv->qm_dwork,
+ msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
+
+ return 0;
+}
+
+/* End of qm error WAR */
+
+static int
+ar40xx_vlan_init(struct ar40xx_priv *priv)
+{
+ int port;
+ unsigned long bmp;
+
+ /* By default Enable VLAN */
+ priv->vlan = 1;
+ priv->vlan_table[AR40XX_LAN_VLAN] = priv->cpu_bmp | priv->lan_bmp;
+ priv->vlan_table[AR40XX_WAN_VLAN] = priv->cpu_bmp | priv->wan_bmp;
+ priv->vlan_tagged = priv->cpu_bmp;
+ bmp = priv->lan_bmp;
+ for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)
+ priv->pvid[port] = AR40XX_LAN_VLAN;
+
+ bmp = priv->wan_bmp;
+ for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)
+ priv->pvid[port] = AR40XX_WAN_VLAN;
+
+ return 0;
+}
+
+static void
+ar40xx_mib_work_func(struct work_struct *work)
+{
+ struct ar40xx_priv *priv;
+ int err;
+
+ priv = container_of(work, struct ar40xx_priv, mib_work.work);
+
+ mutex_lock(&priv->mib_lock);
+
+ err = ar40xx_mib_capture(priv);
+ if (err)
+ goto next_port;
+
+ ar40xx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
+
+next_port:
+ priv->mib_next_port++;
+ if (priv->mib_next_port >= priv->dev.ports)
+ priv->mib_next_port = 0;
+
+ mutex_unlock(&priv->mib_lock);
+
+ schedule_delayed_work(&priv->mib_work,
+ msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));
+}
+
+static void
+ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members)
+{
+ u32 t;
+ u32 egress, ingress;
+ u32 pvid = priv->vlan_id[priv->pvid[port]];
+
+ if (priv->vlan) {
+ egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
+
+ ingress = AR40XX_IN_SECURE;
+ } else {
+ egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH;
+ ingress = AR40XX_IN_PORT_ONLY;
+ }
+
+ t = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;
+ t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;
+ ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t);
+
+ t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
+ t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
+
+ ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
+
+ t = members;
+ t |= AR40XX_PORT_LOOKUP_LEARN;
+ t |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S;
+ t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
+ ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);
+}
+
+static void
+ar40xx_vtu_op(struct ar40xx_priv *priv, u32 op, u32 val)
+{
+ if (ar40xx_wait_bit(priv, AR40XX_REG_VTU_FUNC1,
+ AR40XX_VTU_FUNC1_BUSY, 0))
+ return;
+
+ if ((op & AR40XX_VTU_FUNC1_OP) == AR40XX_VTU_FUNC1_OP_LOAD)
+ ar40xx_write(priv, AR40XX_REG_VTU_FUNC0, val);
+
+ op |= AR40XX_VTU_FUNC1_BUSY;
+ ar40xx_write(priv, AR40XX_REG_VTU_FUNC1, op);
+}
+
+static void
+ar40xx_vtu_load_vlan(struct ar40xx_priv *priv, u32 vid, u32 port_mask)
+{
+ u32 op;
+ u32 val;
+ int i;
+
+ op = AR40XX_VTU_FUNC1_OP_LOAD | (vid << AR40XX_VTU_FUNC1_VID_S);
+ val = AR40XX_VTU_FUNC0_VALID | AR40XX_VTU_FUNC0_IVL;
+ for (i = 0; i < AR40XX_NUM_PORTS; i++) {
+ u32 mode;
+
+ if ((port_mask & BIT(i)) == 0)
+ mode = AR40XX_VTU_FUNC0_EG_MODE_NOT;
+ else if (priv->vlan == 0)
+ mode = AR40XX_VTU_FUNC0_EG_MODE_KEEP;
+ else if ((priv->vlan_tagged & BIT(i)) ||
+ (priv->vlan_id[priv->pvid[i]] != vid))
+ mode = AR40XX_VTU_FUNC0_EG_MODE_TAG;
+ else
+ mode = AR40XX_VTU_FUNC0_EG_MODE_UNTAG;
+
+ val |= mode << AR40XX_VTU_FUNC0_EG_MODE_S(i);
+ }
+ ar40xx_vtu_op(priv, op, val);
+}
+
+static void
+ar40xx_vtu_flush(struct ar40xx_priv *priv)
+{
+ ar40xx_vtu_op(priv, AR40XX_VTU_FUNC1_OP_FLUSH, 0);
+}
+
+static int
+ar40xx_sw_hw_apply(struct switch_dev *dev)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+ u8 portmask[AR40XX_NUM_PORTS];
+ int i, j;
+
+ mutex_lock(&priv->reg_mutex);
+ /* flush all vlan entries */
+ ar40xx_vtu_flush(priv);
+
+ memset(portmask, 0, sizeof(portmask));
+ if (priv->vlan) {
+ for (j = 0; j < AR40XX_MAX_VLANS; j++) {
+ u8 vp = priv->vlan_table[j];
+
+ if (!vp)
+ continue;
+
+ for (i = 0; i < dev->ports; i++) {
+ u8 mask = BIT(i);
+
+ if (vp & mask)
+ portmask[i] |= vp & ~mask;
+ }
+
+ ar40xx_vtu_load_vlan(priv, priv->vlan_id[j],
+ priv->vlan_table[j]);
+ }
+ } else {
+ /* 8021q vlan disabled */
+ for (i = 0; i < dev->ports; i++) {
+ if (i == AR40XX_PORT_CPU)
+ continue;
+
+ portmask[i] = BIT(AR40XX_PORT_CPU);
+ portmask[AR40XX_PORT_CPU] |= BIT(i);
+ }
+ }
+
+ /* update the port destination mask registers and tag settings */
+ for (i = 0; i < dev->ports; i++)
+ ar40xx_setup_port(priv, i, portmask[i]);
+
+ ar40xx_set_mirror_regs(priv);
+
+ mutex_unlock(&priv->reg_mutex);
+ return 0;
+}
+
+static int
+ar40xx_sw_reset_switch(struct switch_dev *dev)
+{
+ struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
+ int i, rv;
+
+ mutex_lock(&priv->reg_mutex);
+ memset(&priv->vlan, 0, sizeof(struct ar40xx_priv) -
+ offsetof(struct ar40xx_priv, vlan));
+
+ for (i = 0; i < AR40XX_MAX_VLANS; i++)
+ priv->vlan_id[i] = i;
+
+ ar40xx_vlan_init(priv);
+
+ priv->mirror_rx = false;
+ priv->mirror_tx = false;
+ priv->source_port = 0;
+ priv->monitor_port = 0;
+
+ mutex_unlock(&priv->reg_mutex);
+
+ rv = ar40xx_sw_hw_apply(dev);
+ return rv;
+}
+
+static int
+ar40xx_start(struct ar40xx_priv *priv)
+{
+ int ret;
+
+ ret = ar40xx_hw_init(priv);
+ if (ret)
+ return ret;
+
+ ret = ar40xx_sw_reset_switch(&priv->dev);
+ if (ret)
+ return ret;
+
+ /* at last, setup cpu port */
+ ret = ar40xx_cpuport_setup(priv);
+ if (ret)
+ return ret;
+
+ schedule_delayed_work(&priv->mib_work,
+ msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));
+
+ ar40xx_qm_err_check_work_start(priv);
+
+ return 0;
+}
+
+static const struct switch_dev_ops ar40xx_sw_ops = {
+ .attr_global = {
+ .attr = ar40xx_sw_attr_globals,
+ .n_attr = ARRAY_SIZE(ar40xx_sw_attr_globals),
+ },
+ .attr_port = {
+ .attr = ar40xx_sw_attr_port,
+ .n_attr = ARRAY_SIZE(ar40xx_sw_attr_port),
+ },
+ .attr_vlan = {
+ .attr = ar40xx_sw_attr_vlan,
+ .n_attr = ARRAY_SIZE(ar40xx_sw_attr_vlan),
+ },
+ .get_port_pvid = ar40xx_sw_get_pvid,
+ .set_port_pvid = ar40xx_sw_set_pvid,
+ .get_vlan_ports = ar40xx_sw_get_ports,
+ .set_vlan_ports = ar40xx_sw_set_ports,
+ .apply_config = ar40xx_sw_hw_apply,
+ .reset_switch = ar40xx_sw_reset_switch,
+ .get_port_link = ar40xx_sw_get_port_link,
+};
+
+/* Platform driver probe function */
+
+static int ar40xx_probe(struct platform_device *pdev)
+{
+ struct device_node *switch_node;
+ struct device_node *psgmii_node;
+ struct device_node *mdio_node;
+ const __be32 *mac_mode;
+ struct clk *ess_clk;
+ struct switch_dev *swdev;
+ struct ar40xx_priv *priv;
+ u32 len;
+ u32 num_mibs;
+ struct resource psgmii_base = {0};
+ struct resource switch_base = {0};
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, priv);
+ ar40xx_priv = priv;
+
+ switch_node = of_node_get(pdev->dev.of_node);
+ if (of_address_to_resource(switch_node, 0, &switch_base) != 0)
+ return -EIO;
+
+ priv->hw_addr = devm_ioremap_resource(&pdev->dev, &switch_base);
+ if (IS_ERR(priv->hw_addr)) {
+ dev_err(&pdev->dev, "Failed to ioremap switch_base!\n");
+ return PTR_ERR(priv->hw_addr);
+ }
+
+ /*psgmii dts get*/
+ psgmii_node = of_find_node_by_name(NULL, "ess-psgmii");
+ if (!psgmii_node) {
+ dev_err(&pdev->dev, "Failed to find ess-psgmii node!\n");
+ return -EINVAL;
+ }
+
+ if (of_address_to_resource(psgmii_node, 0, &psgmii_base) != 0)
+ return -EIO;
+
+ priv->psgmii_hw_addr = devm_ioremap_resource(&pdev->dev, &psgmii_base);
+ if (IS_ERR(priv->psgmii_hw_addr)) {
+ dev_err(&pdev->dev, "psgmii ioremap fail!\n");
+ return PTR_ERR(priv->psgmii_hw_addr);
+ }
+
+ mac_mode = of_get_property(switch_node, "switch_mac_mode", &len);
+ if (!mac_mode) {
+ dev_err(&pdev->dev, "Failed to read switch_mac_mode\n");
+ return -EINVAL;
+ }
+ priv->mac_mode = be32_to_cpup(mac_mode);
+
+ ess_clk = of_clk_get_by_name(switch_node, "ess_clk");
+ if (ess_clk)
+ clk_prepare_enable(ess_clk);
+
+ priv->ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst");
+ if (IS_ERR(priv->ess_rst)) {
+ dev_err(&pdev->dev, "Failed to get ess_rst control!\n");
+ return PTR_ERR(priv->ess_rst);
+ }
+
+ if (of_property_read_u32(switch_node, "switch_cpu_bmp",
+ &priv->cpu_bmp) ||
+ of_property_read_u32(switch_node, "switch_lan_bmp",
+ &priv->lan_bmp) ||
+ of_property_read_u32(switch_node, "switch_wan_bmp",
+ &priv->wan_bmp)) {
+ dev_err(&pdev->dev, "Failed to read port properties\n");
+ return -EIO;
+ }
+
+ mutex_init(&priv->reg_mutex);
+ mutex_init(&priv->mib_lock);
+ INIT_DELAYED_WORK(&priv->mib_work, ar40xx_mib_work_func);
+
+ /* register switch */
+ swdev = &priv->dev;
+
+ mdio_node = of_find_compatible_node(NULL, NULL, "qcom,ipq4019-mdio");
+ if (!mdio_node) {
+ dev_err(&pdev->dev, "Probe failed - Cannot find mdio node by phandle!\n");
+ ret = -ENODEV;
+ goto err_missing_phy;
+ }
+
+ priv->mii_bus = of_mdio_find_bus(mdio_node);
+
+ if (priv->mii_bus == NULL) {
+ dev_err(&pdev->dev, "Probe failed - Missing PHYs!\n");
+ ret = -ENODEV;
+ goto err_missing_phy;
+ }
+
+ swdev->alias = dev_name(&priv->mii_bus->dev);
+
+ swdev->cpu_port = AR40XX_PORT_CPU;
+ swdev->name = "QCA AR40xx";
+ swdev->vlans = AR40XX_MAX_VLANS;
+ swdev->ports = AR40XX_NUM_PORTS;
+ swdev->ops = &ar40xx_sw_ops;
+ ret = register_switch(swdev, NULL);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Switch registration failed!\n");
+ return ret;
+ }
+
+ num_mibs = ARRAY_SIZE(ar40xx_mibs);
+ len = priv->dev.ports * num_mibs *
+ sizeof(*priv->mib_stats);
+ priv->mib_stats = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+ if (!priv->mib_stats) {
+ ret = -ENOMEM;
+ goto err_unregister_switch;
+ }
+
+ ar40xx_start(priv);
+
+ return 0;
+
+err_unregister_switch:
+ unregister_switch(&priv->dev);
+err_missing_phy:
+ platform_set_drvdata(pdev, NULL);
+ return ret;
+}
+
+static int ar40xx_remove(struct platform_device *pdev)
+{
+ struct ar40xx_priv *priv = platform_get_drvdata(pdev);
+
+ cancel_delayed_work_sync(&priv->qm_dwork);
+ cancel_delayed_work_sync(&priv->mib_work);
+
+ unregister_switch(&priv->dev);
+
+ return 0;
+}
+
+static const struct of_device_id ar40xx_of_mtable[] = {
+ {.compatible = "qcom,ess-switch" },
+ {}
+};
+
+struct platform_driver ar40xx_drv = {
+ .probe = ar40xx_probe,
+ .remove = ar40xx_remove,
+ .driver = {
+ .name = "ar40xx",
+ .of_match_table = ar40xx_of_mtable,
+ },
+};
+
+module_platform_driver(ar40xx_drv);
+
+MODULE_DESCRIPTION("IPQ40XX ESS driver");
+MODULE_LICENSE("Dual BSD/GPL");
--- /dev/null
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+ #ifndef __AR40XX_H
+#define __AR40XX_H
+
+#define AR40XX_MAX_VLANS 128
+#define AR40XX_NUM_PORTS 6
+#define AR40XX_NUM_PHYS 5
+
+#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
+
+struct ar40xx_priv {
+ struct switch_dev dev;
+
+ u8 __iomem *hw_addr;
+ u8 __iomem *psgmii_hw_addr;
+ u32 mac_mode;
+ struct reset_control *ess_rst;
+ u32 cpu_bmp;
+ u32 lan_bmp;
+ u32 wan_bmp;
+
+ struct mii_bus *mii_bus;
+ struct phy_device *phy;
+
+ /* mutex for qm task */
+ struct mutex qm_lock;
+ struct delayed_work qm_dwork;
+ u32 port_link_up[AR40XX_NUM_PORTS];
+ u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
+ u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
+
+ u32 phy_t_status;
+
+ /* mutex for switch reg access */
+ struct mutex reg_mutex;
+
+ /* mutex for mib task */
+ struct mutex mib_lock;
+ struct delayed_work mib_work;
+ int mib_next_port;
+ u64 *mib_stats;
+
+ char buf[2048];
+
+ /* all fields below will be cleared on reset */
+ bool vlan;
+ u16 vlan_id[AR40XX_MAX_VLANS];
+ u8 vlan_table[AR40XX_MAX_VLANS];
+ u8 vlan_tagged;
+ u16 pvid[AR40XX_NUM_PORTS];
+
+ /* mirror */
+ bool mirror_rx;
+ bool mirror_tx;
+ int source_port;
+ int monitor_port;
+};
+
+#define AR40XX_PORT_LINK_UP 1
+#define AR40XX_PORT_LINK_DOWN 0
+#define AR40XX_QM_NOT_EMPTY 1
+#define AR40XX_QM_EMPTY 0
+
+#define AR40XX_LAN_VLAN 1
+#define AR40XX_WAN_VLAN 2
+
+enum ar40xx_port_wrapper_cfg {
+ PORT_WRAPPER_PSGMII = 0,
+};
+
+struct ar40xx_mib_desc {
+ u32 size;
+ u32 offset;
+ const char *name;
+};
+
+#define AR40XX_PORT_CPU 0
+
+#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
+#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
+
+#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
+
+#define AR40XX_MII_ATH_MMD_ADDR 0x0d
+#define AR40XX_MII_ATH_MMD_DATA 0x0e
+#define AR40XX_MII_ATH_DBG_ADDR 0x1d
+#define AR40XX_MII_ATH_DBG_DATA 0x1e
+
+#define AR40XX_STATS_RXBROAD 0x00
+#define AR40XX_STATS_RXPAUSE 0x04
+#define AR40XX_STATS_RXMULTI 0x08
+#define AR40XX_STATS_RXFCSERR 0x0c
+#define AR40XX_STATS_RXALIGNERR 0x10
+#define AR40XX_STATS_RXRUNT 0x14
+#define AR40XX_STATS_RXFRAGMENT 0x18
+#define AR40XX_STATS_RX64BYTE 0x1c
+#define AR40XX_STATS_RX128BYTE 0x20
+#define AR40XX_STATS_RX256BYTE 0x24
+#define AR40XX_STATS_RX512BYTE 0x28
+#define AR40XX_STATS_RX1024BYTE 0x2c
+#define AR40XX_STATS_RX1518BYTE 0x30
+#define AR40XX_STATS_RXMAXBYTE 0x34
+#define AR40XX_STATS_RXTOOLONG 0x38
+#define AR40XX_STATS_RXGOODBYTE 0x3c
+#define AR40XX_STATS_RXBADBYTE 0x44
+#define AR40XX_STATS_RXOVERFLOW 0x4c
+#define AR40XX_STATS_FILTERED 0x50
+#define AR40XX_STATS_TXBROAD 0x54
+#define AR40XX_STATS_TXPAUSE 0x58
+#define AR40XX_STATS_TXMULTI 0x5c
+#define AR40XX_STATS_TXUNDERRUN 0x60
+#define AR40XX_STATS_TX64BYTE 0x64
+#define AR40XX_STATS_TX128BYTE 0x68
+#define AR40XX_STATS_TX256BYTE 0x6c
+#define AR40XX_STATS_TX512BYTE 0x70
+#define AR40XX_STATS_TX1024BYTE 0x74
+#define AR40XX_STATS_TX1518BYTE 0x78
+#define AR40XX_STATS_TXMAXBYTE 0x7c
+#define AR40XX_STATS_TXOVERSIZE 0x80
+#define AR40XX_STATS_TXBYTE 0x84
+#define AR40XX_STATS_TXCOLLISION 0x8c
+#define AR40XX_STATS_TXABORTCOL 0x90
+#define AR40XX_STATS_TXMULTICOL 0x94
+#define AR40XX_STATS_TXSINGLECOL 0x98
+#define AR40XX_STATS_TXEXCDEFER 0x9c
+#define AR40XX_STATS_TXDEFER 0xa0
+#define AR40XX_STATS_TXLATECOL 0xa4
+
+#define AR40XX_REG_MODULE_EN 0x030
+#define AR40XX_MODULE_EN_MIB BIT(0)
+
+#define AR40XX_REG_MIB_FUNC 0x034
+#define AR40XX_MIB_BUSY BIT(17)
+#define AR40XX_MIB_CPU_KEEP BIT(20)
+#define AR40XX_MIB_FUNC BITS(24, 3)
+#define AR40XX_MIB_FUNC_S 24
+#define AR40XX_MIB_FUNC_NO_OP 0x0
+#define AR40XX_MIB_FUNC_FLUSH 0x1
+
+#define AR40XX_ESS_SERVICE_TAG 0x48
+#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
+
+#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
+#define AR40XX_PORT_SPEED BITS(0, 2)
+#define AR40XX_PORT_STATUS_SPEED_S 0
+#define AR40XX_PORT_TX_EN BIT(2)
+#define AR40XX_PORT_RX_EN BIT(3)
+#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
+#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
+#define AR40XX_PORT_DUPLEX BIT(6)
+#define AR40XX_PORT_TXHALF_FLOW BIT(7)
+#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
+#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
+#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
+
+#define AR40XX_REG_MAX_FRAME_SIZE 0x078
+#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
+
+#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
+
+#define AR40XX_REG_EEE_CTRL 0x100
+#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
+
+#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
+#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
+#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
+#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
+#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
+
+#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
+#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
+#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
+#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
+#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
+#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
+#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
+#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
+#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
+#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
+
+#define AR40XX_REG_VTU_FUNC0 0x0610
+#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
+#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
+#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
+#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
+#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
+#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
+#define AR40XX_VTU_FUNC0_IVL BIT(19)
+#define AR40XX_VTU_FUNC0_VALID BIT(20)
+
+#define AR40XX_REG_VTU_FUNC1 0x0614
+#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
+#define AR40XX_VTU_FUNC1_OP_NOOP 0
+#define AR40XX_VTU_FUNC1_OP_FLUSH 1
+#define AR40XX_VTU_FUNC1_OP_LOAD 2
+#define AR40XX_VTU_FUNC1_OP_PURGE 3
+#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
+#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
+#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
+#define AR40XX_VTU_FUNC1_FULL BIT(4)
+#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
+#define AR40XX_VTU_FUNC1_PORT_S 8
+#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
+#define AR40XX_VTU_FUNC1_VID_S 16
+#define AR40XX_VTU_FUNC1_BUSY BIT(31)
+
+#define AR40XX_REG_FWD_CTRL0 0x620
+#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
+#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
+#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
+
+#define AR40XX_REG_FWD_CTRL1 0x624
+#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
+#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
+#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
+#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
+#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
+#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
+#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
+#define AR40XX_FWD_CTRL1_IGMP_S 24
+
+#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
+#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
+#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
+#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
+#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
+#define AR40XX_PORT_LOOKUP_STATE_S 16
+#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
+#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
+#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
+
+#define AR40XX_REG_ATU_FUNC 0x60c
+#define AR40XX_ATU_FUNC_OP BITS(0, 4)
+#define AR40XX_ATU_FUNC_OP_NOOP 0x0
+#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
+#define AR40XX_ATU_FUNC_OP_LOAD 0x2
+#define AR40XX_ATU_FUNC_OP_PURGE 0x3
+#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
+#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
+#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
+#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
+#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
+#define AR40XX_ATU_FUNC_BUSY BIT(31)
+
+#define AR40XX_REG_QM_DEBUG_ADDR 0x820
+#define AR40XX_REG_QM_DEBUG_VALUE 0x824
+#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
+#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
+
+#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
+#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
+
+#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
+#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
+#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
+
+#define AR40XX_PHY_DEBUG_0 0
+#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
+
+#define AR40XX_PHY_DEBUG_2 2
+
+#define AR40XX_PHY_SPEC_STATUS 0x11
+#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
+#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
+#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
+
+/* port forwarding state */
+enum {
+ AR40XX_PORT_STATE_DISABLED = 0,
+ AR40XX_PORT_STATE_BLOCK = 1,
+ AR40XX_PORT_STATE_LISTEN = 2,
+ AR40XX_PORT_STATE_LEARN = 3,
+ AR40XX_PORT_STATE_FORWARD = 4
+};
+
+/* ingress 802.1q mode */
+enum {
+ AR40XX_IN_PORT_ONLY = 0,
+ AR40XX_IN_PORT_FALLBACK = 1,
+ AR40XX_IN_VLAN_ONLY = 2,
+ AR40XX_IN_SECURE = 3
+};
+
+/* egress 802.1q mode */
+enum {
+ AR40XX_OUT_KEEP = 0,
+ AR40XX_OUT_STRIP_VLAN = 1,
+ AR40XX_OUT_ADD_VLAN = 2
+};
+
+/* port speed */
+enum {
+ AR40XX_PORT_SPEED_10M = 0,
+ AR40XX_PORT_SPEED_100M = 1,
+ AR40XX_PORT_SPEED_1000M = 2,
+ AR40XX_PORT_SPEED_ERR = 3,
+};
+
+#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
+
+#define AR40XX_QM_WORK_DELAY 100
+
+#define AR40XX_MIB_FUNC_CAPTURE 0x3
+
+#define AR40XX_REG_PORT_STATS_START 0x1000
+#define AR40XX_REG_PORT_STATS_LEN 0x100
+
+#define AR40XX_PORTS_ALL 0x3f
+
+#define AR40XX_PSGMII_ID 5
+#define AR40XX_PSGMII_CALB_NUM 100
+#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
+#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
+#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
+#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
+#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
+#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
+#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
+#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
+#define AR40XX_MALIBU_PHY_LAST_ADDR 4
+
+static inline struct ar40xx_priv *
+swdev_to_ar40xx(struct switch_dev *swdev)
+{
+ return container_of(swdev, struct ar40xx_priv, dev);
+}
+
+#endif
--- /dev/null
+From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Wed, 9 Sep 2020 18:38:31 +0200
+Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
+
+Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+Reviewed-by: Vinod Koul <vkoul@kernel.org>
+Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
+ 1 file changed, 74 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -605,5 +605,79 @@
+ reg = <4>;
+ };
+ };
++
++ usb3_ss_phy: ssphy@9a000 {
++ compatible = "qcom,usb-ss-ipq4019-phy";
++ #phy-cells = <0>;
++ reg = <0x9a000 0x800>;
++ reg-names = "phy_base";
++ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
++ reset-names = "por_rst";
++ status = "disabled";
++ };
++
++ usb3_hs_phy: hsphy@a6000 {
++ compatible = "qcom,usb-hs-ipq4019-phy";
++ #phy-cells = <0>;
++ reg = <0xa6000 0x40>;
++ reg-names = "phy_base";
++ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
++ reset-names = "por_rst", "srif_rst";
++ status = "disabled";
++ };
++
++ usb3: usb3@8af8800 {
++ compatible = "qcom,dwc3";
++ reg = <0x8af8800 0x100>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ clocks = <&gcc GCC_USB3_MASTER_CLK>,
++ <&gcc GCC_USB3_SLEEP_CLK>,
++ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
++ clock-names = "master", "sleep", "mock_utmi";
++ ranges;
++ status = "disabled";
++
++ dwc3@8a00000 {
++ compatible = "snps,dwc3";
++ reg = <0x8a00000 0xf8000>;
++ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
++ phy-names = "usb2-phy", "usb3-phy";
++ dr_mode = "host";
++ };
++ };
++
++ usb2_hs_phy: hsphy@a8000 {
++ compatible = "qcom,usb-hs-ipq4019-phy";
++ #phy-cells = <0>;
++ reg = <0xa8000 0x40>;
++ reg-names = "phy_base";
++ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
++ reset-names = "por_rst", "srif_rst";
++ status = "disabled";
++ };
++
++ usb2: usb2@60f8800 {
++ compatible = "qcom,dwc3";
++ reg = <0x60f8800 0x100>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ clocks = <&gcc GCC_USB2_MASTER_CLK>,
++ <&gcc GCC_USB2_SLEEP_CLK>,
++ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
++ clock-names = "master", "sleep", "mock_utmi";
++ ranges;
++ status = "disabled";
++
++ dwc3@6000000 {
++ compatible = "snps,dwc3";
++ reg = <0x6000000 0xf8000>;
++ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb2_hs_phy>;
++ phy-names = "usb2-phy";
++ dr_mode = "host";
++ };
++ };
+ };
+ };
--- /dev/null
+From d1ae4c808e7802008225078d93fbadd4aeea1e2d Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Wed, 9 Sep 2020 21:56:37 +0200
+Subject: [PATCH] ARM: dts: qcom: ipq4019: add more labels
+
+Lets add labels to more commonly used nodes for easier modification in board DTS files.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+Link: https://lore.kernel.org/r/20200909195640.3127341-2-robert.marko@sartura.hr
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -190,7 +190,7 @@
+ reg = <0x1800000 0x60000>;
+ };
+
+- rng@22000 {
++ prng: rng@22000 {
+ compatible = "qcom,prng";
+ reg = <0x22000 0x140>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+@@ -300,7 +300,7 @@
+ status = "disabled";
+ };
+
+- crypto@8e3a000 {
++ crypto: crypto@8e3a000 {
+ compatible = "qcom,crypto-v5.1";
+ reg = <0x08e3a000 0x6000>;
+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
+@@ -386,7 +386,7 @@
+ dma-names = "rx", "tx";
+ };
+
+- watchdog@b017000 {
++ watchdog: watchdog@b017000 {
+ compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
+ reg = <0xb017000 0x40>;
+ clocks = <&sleep_clk>;
--- /dev/null
+From e14775aa2feac18e7378cb8009b55c13d4236b50 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Mon, 7 Sep 2020 12:19:37 +0200
+Subject: [PATCH] ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO node
+
+Since we now have driver for the SDHCI VQMMC LDO needed
+for I/0 voltage levels lets introduce the necessary node for it.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Cc: Luka Perkov <luka.perkov@sartura.hr>
+Link: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -209,6 +209,16 @@
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
++ vqmmc: regulator@1948000 {
++ compatible = "qcom,vqmmc-ipq4019-regulator";
++ reg = <0x01948000 0x4>;
++ regulator-name = "vqmmc";
++ regulator-min-microvolt = <1500000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-always-on;
++ status = "disabled";
++ };
++
+ sdhci: sdhci@7824900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x7824900 0x11c>, <0x7824000 0x800>;
--- /dev/null
+From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@googlemail.com>
+Date: Sun, 11 Mar 2018 14:41:31 +0100
+Subject: [PATCH 2/2] clk: fix apss cpu overclocking
+
+There's an interaction issue between the clk changes:"
+clk: qcom: ipq4019: Add the apss cpu pll divider clock node
+clk: qcom: ipq4019: remove fixed clocks and add pll clocks
+" and the cpufreq-dt.
+
+cpufreq-dt is now spamming the kernel-log with the following:
+
+[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
+for freq 761142857 (-34)
+
+This only happens on certain devices like the Compex WPJ428
+and AVM FritzBox!4040. However, other devices like the Asus
+RT-AC58U and Meraki MR33 work just fine.
+
+The issue stem from the fact that all higher CPU-Clocks
+are achieved by switching the clock-parent to the P_DDRPLLAPSS
+(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
+as part of the DDR calibration.
+
+For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
+at round 533 MHz (ddrpllsdcc = 190285714 Hz).
+
+whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
+clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
+
+This patch attempts to fix the issue by modifying
+clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
+to use a new qcom_find_freq_close() function, which returns the closest
+matching frequency, instead of the next higher. This way, the SoC in
+the FB4040 (with its max clock speed of 710.4 MHz) will no longer
+try to overclock to 761 MHz.
+
+Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
+ 1 file changed, 31 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq4019.c
++++ b/drivers/clk/qcom/gcc-ipq4019.c
+@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
+ .reg = 0x2f020,
+ };
+
++
++const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
++ unsigned long rate)
++{
++ const struct freq_tbl *last = NULL;
++
++ for ( ; f->freq; f++) {
++ if (rate == f->freq)
++ return f;
++
++ if (f->freq > rate) {
++ if (!last ||
++ (f->freq - rate) < (rate - last->freq))
++ return f;
++ else
++ return last;
++ }
++ last = f;
++ }
++
++ return last;
++}
++
+ /*
+ * Round rate function for APSS CPU PLL Clock divider.
+ * It looks up the frequency table and returns the next higher frequency
+@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
+ struct clk_hw *p_hw;
+ const struct freq_tbl *f;
+
+- f = qcom_find_freq(pll->freq_tbl, rate);
++ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return -EINVAL;
+
+@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c
+ u32 mask;
+ int ret;
+
+- f = qcom_find_freq(pll->freq_tbl, rate);
++ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return -EINVAL;
+
+@@ -1305,6 +1328,7 @@ static unsigned long
+ clk_cpu_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+ {
++ const struct freq_tbl *f;
+ struct clk_fepll *pll = to_clk_fepll(hw);
+ u32 cdiv, pre_div;
+ u64 rate;
+@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
+ rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
+ do_div(rate, pre_div);
+
+- return rate;
++ f = qcom_find_freq_close(pll->freq_tbl, rate);
++ if (!f)
++ return rate;
++
++ return f->freq;
+ };
+
+ static const struct clk_ops clk_regmap_cpu_div_ops = {
--- /dev/null
+From a63c7162a1dae9f1185897641dc3e47e295563d6 Mon Sep 17 00:00:00 2001
+From: Pavel Kubelun <be.dissent@gmail.com>
+Date: Mon, 6 May 2019 20:55:16 +0300
+Subject: [PATCH] ARM: dts: qcom: ipq4019: fix sleep clock
+
+It seems like sleep_clk was copied from ipq806x.
+Fix ipq40xx sleep_clk to the value QSDK defines.
+
+Link: https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?id=d92ec59973484acc86dd24b67f10f8911b4b4b7d
+Link: https://patchwork.kernel.org/comment/22721613/
+Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> [clock-output-names]
+Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com> [just fixed the value]
+---
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -142,7 +142,8 @@
+ clocks {
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+- clock-frequency = <32768>;
++ clock-frequency = <32000>;
++ clock-output-names = "gcc_sleep_clk_src";
+ #clock-cells = <0>;
+ };
+
--- /dev/null
+From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001
+From: Ram Chandra Jangir <rjangir@codeaurora.org>
+Date: Tue, 28 Mar 2017 22:35:33 +0530
+Subject: [PATCH] clk: qcom: ipq4019: add ess reset
+
+Added the ESS reset in IPQ4019 GCC.
+
+Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
+---
+ drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++
+ include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++
+ 2 files changed, 22 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-ipq4019.c
++++ b/drivers/clk/qcom/gcc-ipq4019.c
+@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i
+ [GCC_TCSR_BCR] = {0x22000, 0},
+ [GCC_MPM_BCR] = {0x24000, 0},
+ [GCC_SPDM_BCR] = {0x25000, 0},
++ [ESS_MAC1_ARES] = {0x1200C, 0},
++ [ESS_MAC2_ARES] = {0x1200C, 1},
++ [ESS_MAC3_ARES] = {0x1200C, 2},
++ [ESS_MAC4_ARES] = {0x1200C, 3},
++ [ESS_MAC5_ARES] = {0x1200C, 4},
++ [ESS_PSGMII_ARES] = {0x1200C, 5},
++ [ESS_MAC1_CLK_DIS] = {0x1200C, 8},
++ [ESS_MAC2_CLK_DIS] = {0x1200C, 9},
++ [ESS_MAC3_CLK_DIS] = {0x1200C, 10},
++ [ESS_MAC4_CLK_DIS] = {0x1200C, 11},
++ [ESS_MAC5_CLK_DIS] = {0x1200C, 12},
+ };
+
+ static const struct regmap_config gcc_ipq4019_regmap_config = {
+--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
++++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+@@ -165,5 +165,16 @@
+ #define GCC_QDSS_BCR 69
+ #define GCC_MPM_BCR 70
+ #define GCC_SPDM_BCR 71
++#define ESS_MAC1_ARES 72
++#define ESS_MAC2_ARES 73
++#define ESS_MAC3_ARES 74
++#define ESS_MAC4_ARES 75
++#define ESS_MAC5_ARES 76
++#define ESS_PSGMII_ARES 77
++#define ESS_MAC1_CLK_DIS 78
++#define ESS_MAC2_CLK_DIS 79
++#define ESS_MAC3_CLK_DIS 80
++#define ESS_MAC4_CLK_DIS 81
++#define ESS_MAC5_CLK_DIS 82
+
+ #endif
--- /dev/null
+From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 30 Oct 2020 13:36:31 +0100
+Subject: [PATCH] arm: compressed: add appended DTB section
+
+This adds a appended_dtb section to the ARM decompressor
+linker script.
+
+This allows using the existing ARM zImage appended DTB support for
+appending a DTB to the raw ELF kernel.
+
+Its size is set to 1MB max to match the zImage appended DTB size limit.
+
+To use it to pass the DTB to the kernel, objcopy is used:
+
+objcopy --set-section-flags=.appended_dtb=alloc,contents \
+ --update-section=.appended_dtb=<target>.dtb vmlinux
+
+This is based off the following patch:
+https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/compressed/vmlinux.lds.S
++++ b/arch/arm/boot/compressed/vmlinux.lds.S
+@@ -101,6 +101,13 @@ SECTIONS
+
+ _edata = .;
+
++ .appended_dtb : {
++ /* leave space for appended DTB */
++ . += 0x100000;
++ }
++
++ _edata_dtb = .;
++
+ /*
+ * The image_end section appears after any additional loadable sections
+ * that the linker may decide to insert in the binary image. Having
+@@ -138,4 +145,4 @@ SECTIONS
+
+ ARM_ASSERTS
+ }
+-ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
++ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");
--- /dev/null
+From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
+From: John Thomson <git@johnthomson.fastmail.com.au>
+Date: Fri, 23 Oct 2020 19:42:36 +1000
+Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
+
+For IPQ40XX systems where the SoC watchdog is activated before linux,
+the watchdog timer may be too small for linux to finish uncompress,
+boot, and watchdog management start.
+If the watchdog is enabled, set the timeout for it to 30 seconds.
+The functionality and offsets were copied from:
+drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
+The watchdog memory address was taken from:
+arch/arm/boot/dts/qcom-ipq4019.dtsi
+
+This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
+RouterBoot bootloader.
+
+Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
+---
+ arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -602,6 +602,41 @@ not_relocated: mov r0, #0
+ bic r4, r4, #1
+ blne cache_on
+
++/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
++ * if it is enabled, so that there is time for kernel
++ * to decompress, boot, and take over the watchdog.
++ * data and functionality from drivers/watchdog/qcom-wdt.c
++ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
++ */
++#ifdef CONFIG_ARCH_IPQ40XX
++watchdog_set:
++ /* offsets:
++ * 0x04 reset (=1 resets countdown)
++ * 0x08 enable (=0 disables)
++ * 0x0c status (=1 when SoC was reset by watchdog)
++ * 0x10 bark (=timeout warning in ticks)
++ * 0x14 bite (=timeout reset in ticks)
++ * clock rate is 1<<15 hertz
++ */
++ .equ watchdog, 0x0b017000 @Store watchdog base address
++ movw r0, #:lower16:watchdog
++ movt r0, #:upper16:watchdog
++ ldr r1, [r0, #0x08] @Get enabled?
++ cmp r1, #1 @If not enabled, do not change
++ bne watchdog_finished
++ mov r1, #0
++ str r1, [r0, #0x08] @Disable the watchdog
++ mov r1, #1
++ str r1, [r0, #0x04] @Pet the watchdog
++ mov r1, #30 @30 seconds timeout
++ lsl r1, r1, #15 @converted to ticks
++ str r1, [r0, #0x10] @Set the bark timeout
++ str r1, [r0, #0x14] @Set the bite timeout
++ mov r1, #1
++ str r1, [r0, #0x08] @Enable the watchdog
++watchdog_finished:
++#endif /* CONFIG_ARCH_IPQ40XX */
++
+ /*
+ * The C runtime environment should now be setup sufficiently.
+ * Set up some pointers, and start decompressing.
--- /dev/null
+From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Mon, 14 Dec 2020 13:35:35 +0100
+Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
+
+When using sdhci_msm_set_clock clock setting will fail, so lets
+use the generic sdhci_set_clock.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ drivers/mmc/host/sdhci-msm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mmc/host/sdhci-msm.c
++++ b/drivers/mmc/host/sdhci-msm.c
+@@ -2191,7 +2191,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
+
+ static const struct sdhci_ops sdhci_msm_ops = {
+ .reset = sdhci_msm_reset,
+- .set_clock = sdhci_msm_set_clock,
++ .set_clock = sdhci_set_clock,
+ .get_min_clock = sdhci_msm_get_min_clock,
+ .get_max_clock = sdhci_msm_get_max_clock,
+ .set_bus_width = sdhci_set_bus_width,
--- /dev/null
+--- a/drivers/firmware/qcom_scm.c
++++ b/drivers/firmware/qcom_scm.c
+@@ -404,6 +404,20 @@ static int __qcom_scm_set_dload_mode(str
+ return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
+ }
+
++static int __qcom_scm_disable_sdi(struct device *dev)
++{
++ struct qcom_scm_desc desc = {
++ .svc = QCOM_SCM_SVC_BOOT,
++ .cmd = QCOM_SCM_BOOT_CONFIG_SDI,
++ .arginfo = QCOM_SCM_ARGS(2),
++ .args[0] = 1 /* 1: disable watchdog debug */,
++ .args[1] = 0 /* 0: disable SDI */,
++ .owner = ARM_SMCCC_OWNER_SIP,
++ };
++
++ return qcom_scm_call(__scm->dev, &desc, NULL);
++}
++
+ static void qcom_scm_set_download_mode(bool enable)
+ {
+ bool avail;
+@@ -1256,6 +1270,13 @@ static int qcom_scm_probe(struct platfor
+ if (download_mode)
+ qcom_scm_set_download_mode(true);
+
++ /*
++ * Factory firmware leaves SDI (a debug interface), which prevents
++ * clean reboot.
++ */
++ if (of_machine_is_compatible("google,wifi"))
++ __qcom_scm_disable_sdi(__scm->dev);
++
+ return 0;
+ }
+
+--- a/drivers/firmware/qcom_scm.h
++++ b/drivers/firmware/qcom_scm.h
+@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device
+ #define QCOM_SCM_SVC_BOOT 0x01
+ #define QCOM_SCM_BOOT_SET_ADDR 0x01
+ #define QCOM_SCM_BOOT_TERMINATE_PC 0x02
++#define QCOM_SCM_BOOT_CONFIG_SDI 0x09
+ #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
+ #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
+ #define QCOM_SCM_FLUSH_FLAG_MASK 0x3
--- /dev/null
+--- a/drivers/firmware/qcom_scm-legacy.c
++++ b/drivers/firmware/qcom_scm-legacy.c
+@@ -13,6 +13,9 @@
+ #include <linux/arm-smccc.h>
+ #include <linux/dma-mapping.h>
+
++#include <asm/cacheflush.h>
++#include <asm/outercache.h>
++
+ #include "qcom_scm.h"
+
+ static DEFINE_MUTEX(qcom_scm_lock);
+@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct
+ } while (res->a0 == QCOM_SCM_INTERRUPTED);
+ }
+
++static void qcom_scm_inv_range(unsigned long start, unsigned long end)
++{
++ u32 cacheline_size, ctr;
++
++ asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
++ cacheline_size = 4 << ((ctr >> 16) & 0xf);
++
++ start = round_down(start, cacheline_size);
++ end = round_up(end, cacheline_size);
++ outer_inv_range(start, end);
++ while (start < end) {
++ asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
++ : "memory");
++ start += cacheline_size;
++ }
++ dsb();
++ isb();
++}
++
+ /**
+ * qcom_scm_call() - Sends a command to the SCM and waits for the command to
+ * finish processing.
+@@ -160,10 +182,16 @@ int scm_legacy_call(struct device *dev,
+
+ rsp = scm_legacy_command_to_response(cmd);
+
+- cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
+- if (dma_mapping_error(dev, cmd_phys)) {
+- kfree(cmd);
+- return -ENOMEM;
++ if (dev) {
++ cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
++ if (dma_mapping_error(dev, cmd_phys)) {
++ kfree(cmd);
++ return -ENOMEM;
++ }
++ } else {
++ cmd_phys = virt_to_phys(cmd);
++ __cpuc_flush_dcache_area(cmd, alloc_len);
++ outer_flush_range(cmd_phys, cmd_phys + alloc_len);
+ }
+
+ smc.args[0] = 1;
+@@ -179,13 +207,26 @@ int scm_legacy_call(struct device *dev,
+ goto out;
+
+ do {
+- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
+- sizeof(*rsp), DMA_FROM_DEVICE);
++ if (dev) {
++ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +
++ cmd_len, sizeof(*rsp),
++ DMA_FROM_DEVICE);
++ } else {
++ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) +
++ cmd_len;
++ qcom_scm_inv_range(start, start + sizeof(*rsp));
++ }
+ } while (!rsp->is_complete);
+
+- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
+- le32_to_cpu(rsp->buf_offset),
+- resp_len, DMA_FROM_DEVICE);
++ if (dev) {
++ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
++ le32_to_cpu(rsp->buf_offset),
++ resp_len, DMA_FROM_DEVICE);
++ } else {
++ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +
++ le32_to_cpu(rsp->buf_offset);
++ qcom_scm_inv_range(start, start + resp_len);
++ }
+
+ if (res) {
+ res_buf = scm_legacy_get_response_buffer(rsp);
+@@ -193,7 +234,8 @@ int scm_legacy_call(struct device *dev,
+ res->result[i] = le32_to_cpu(res_buf[i]);
+ }
+ out:
+- dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
++ if (dev)
++ dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
+ kfree(cmd);
+ return ret;
+ }
+--- a/drivers/firmware/qcom_scm.c
++++ b/drivers/firmware/qcom_scm.c
+@@ -344,6 +344,17 @@ int qcom_scm_set_cold_boot_addr(void *en
+ desc.args[0] = flags;
+ desc.args[1] = virt_to_phys(entry);
+
++ /*
++ * Factory firmware doesn't support the atomic variant. Non-atomic SCMs
++ * require ugly DMA invalidation support that was dropped upstream a
++ * while ago. For more info, see:
++ *
++ * [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?
++ * https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/
++ */
++ if (of_machine_is_compatible("google,wifi"))
++ return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);
++
+ return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
+ }
+ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
--- /dev/null
+From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sun, 20 Nov 2016 02:20:54 +0100
+Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
+
+This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
+nodes which are needed for the ar40xx.c driver to initialize the
+switch.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -617,6 +617,29 @@
+ };
+ };
+
++ ess-switch@c000000 {
++ compatible = "qcom,ess-switch";
++ reg = <0xc000000 0x80000>;
++ switch_access_mode = "local bus";
++ resets = <&gcc ESS_RESET>;
++ reset-names = "ess_rst";
++ clocks = <&gcc GCC_ESS_CLK>;
++ clock-names = "ess_clk";
++ switch_cpu_bmp = <0x1>;
++ switch_lan_bmp = <0x1e>;
++ switch_wan_bmp = <0x20>;
++ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
++ switch_initvlas = <0x7c 0x54>;
++ status = "disabled";
++ };
++
++ ess-psgmii@98000 {
++ compatible = "qcom,ess-psgmii";
++ reg = <0x98000 0x800>;
++ psgmii_access_mode = "local bus";
++ status = "disabled";
++ };
++
+ usb3_ss_phy: ssphy@9a000 {
+ compatible = "qcom,usb-ss-ipq4019-phy";
+ #phy-cells = <0>;
--- /dev/null
+From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
+From: Rakesh Nair <ranair@codeaurora.org>
+Date: Wed, 20 Jul 2016 15:02:01 +0530
+Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
+ netdev_ops
+
+Add callback support to get default vlan tag and register
+receive flow steering filter.
+
+Used by IPQ4019 ess-edma driver.
+
+BUG=chrome-os-partner:33096
+TEST=none
+
+Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
+Signed-off-by: Rakesh Nair <ranair@codeaurora.org>
+Reviewed-on: https://chromium-review.googlesource.com/362203
+Commit-Ready: Grant Grundler <grundler@chromium.org>
+Tested-by: Grant Grundler <grundler@chromium.org>
+Reviewed-by: Grant Grundler <grundler@chromium.org>
+---
+ include/linux/netdevice.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -765,6 +765,16 @@ struct xps_map {
+ #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
+ - sizeof(struct xps_map)) / sizeof(u16))
+
++#ifdef CONFIG_RFS_ACCEL
++typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
++ __be32 src,
++ __be32 dst,
++ __be16 sport,
++ __be16 dport,
++ u8 proto,
++ u16 rxq_index,
++ u32 action);
++#endif
+ /*
+ * This structure holds all XPS maps for device. Maps are indexed by CPU.
+ */
+@@ -1445,6 +1455,9 @@ struct net_device_ops {
+ const struct sk_buff *skb,
+ u16 rxq_index,
+ u32 flow_id);
++ int (*ndo_register_rfs_filter)(struct net_device *dev,
++ set_rfs_filter_callback_t set_filter);
++ int (*ndo_get_default_vlan_tag)(struct net_device *net);
+ #endif
+ int (*ndo_add_slave)(struct net_device *dev,
+ struct net_device *slave_dev,
--- /dev/null
+--- a/drivers/net/mdio/Kconfig
++++ b/drivers/net/mdio/Kconfig
+@@ -27,6 +27,13 @@ config OF_MDIO
+ help
+ OpenFirmware MDIO bus (Ethernet PHY) accessors
+
++config AR40XX_PHY
++ tristate "Driver for Qualcomm Atheros IPQ40XX switches"
++ depends on HAS_IOMEM && OF && OF_MDIO
++ select SWCONFIG
++ help
++ This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
++
+ if MDIO_BUS
+
+ config MDIO_DEVRES
+--- a/drivers/net/mdio/Makefile
++++ b/drivers/net/mdio/Makefile
+@@ -21,6 +21,8 @@ obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.
+ obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o
+ obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o
+
++obj-$(CONFIG_AR40XX_PHY) += ar40xx.o
++
+ obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o
+ obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o
+ obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o
--- /dev/null
+From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Thu, 1 Oct 2020 15:05:35 +0200
+Subject: [PATCH] dt-bindings: net: add QCA807x PHY
+
+Add DT bindings for Qualcomm QCA807x PHY series.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+ create mode 100644 include/dt-bindings/net/qcom-qca807x.h
+
+--- /dev/null
++++ b/include/dt-bindings/net/qcom-qca807x.h
+@@ -0,0 +1,45 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++/*
++ * Device Tree constants for the Qualcomm QCA807X PHYs
++ */
++
++#ifndef _DT_BINDINGS_QCOM_QCA807X_H
++#define _DT_BINDINGS_QCOM_QCA807X_H
++
++#define PSGMII_QSGMII_TX_DRIVER_140MV 0
++#define PSGMII_QSGMII_TX_DRIVER_160MV 1
++#define PSGMII_QSGMII_TX_DRIVER_180MV 2
++#define PSGMII_QSGMII_TX_DRIVER_200MV 3
++#define PSGMII_QSGMII_TX_DRIVER_220MV 4
++#define PSGMII_QSGMII_TX_DRIVER_240MV 5
++#define PSGMII_QSGMII_TX_DRIVER_260MV 6
++#define PSGMII_QSGMII_TX_DRIVER_280MV 7
++#define PSGMII_QSGMII_TX_DRIVER_300MV 8
++#define PSGMII_QSGMII_TX_DRIVER_320MV 9
++#define PSGMII_QSGMII_TX_DRIVER_400MV 10
++#define PSGMII_QSGMII_TX_DRIVER_500MV 11
++/* Default value */
++#define PSGMII_QSGMII_TX_DRIVER_600MV 12
++
++/* Full amplitude, full bias current */
++#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0
++/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */
++#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1
++/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */
++#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2
++/* Both amplitude and bias current follow DSP */
++#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3
++/* Full amplitude, half bias current */
++#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4
++/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,
++ * otherwise half bias current
++ */
++#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5
++/* Full amplitude; same bias current setting with “010” and “011”,
++ * but half more bias is reduced when cable <10m
++ */
++#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6
++/* Amplitude follow DSP; same bias current setting with “110”, default value */
++#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7
++
++#endif
--- /dev/null
+From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Wed, 7 Oct 2020 17:38:48 +0200
+Subject: [PATCH] net: phy: Add Qualcom QCA807x driver
+
+This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
+
+They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.
+
+They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber.
+
+Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber.
+
+Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s.
+But some vendors used these to driver generic LED-s controlled by userspace,
+so lets enable registering each PHY as GPIO controller and add driver for it.
+
+These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ drivers/net/phy/Kconfig | 6 ++++++
+ drivers/net/phy/Makefile | 1 +
+ 2 files changed, 7 insertions(+)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -320,6 +320,12 @@ config AT803X_PHY
+ Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
+ QCA8337(Internal qca8k PHY) model
+
++config QCA807X_PHY
++ tristate "Qualcomm QCA807X PHYs"
++ depends on OF_MDIO
++ help
++ Currently supports the QCA8072 and QCA8075 models.
++
+ config QSEMI_PHY
+ tristate "Quality Semiconductor PHYs"
+ help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -86,6 +86,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/
+ obj-$(CONFIG_NATIONAL_PHY) += national.o
+ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
+ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
++obj-$(CONFIG_QCA807X_PHY) += qca807x.o
+ obj-$(CONFIG_REALTEK_PHY) += realtek.o
+ obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
+ obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
--- /dev/null
+From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Fri, 2 Oct 2020 10:43:26 +0200
+Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
+
+This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/net/qcom-qca807x.h>
+
+ / {
+ #address-cells = <1>;
+@@ -598,22 +599,39 @@
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
++
++ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
++
++ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
++
++ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy3: ethernet-phy@3 {
+ reg = <3>;
++
++ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ ethphy4: ethernet-phy@4 {
+ reg = <4>;
++
++ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
++ };
++
++ psgmiiphy: psgmii-phy@5 {
++ reg = <5>;
++
++ qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;
++ qcom,psgmii-az;
+ };
+ };
+
--- /dev/null
+From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@googlemail.com>
+Date: Thu, 19 Jan 2017 02:01:31 +0100
+Subject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ drivers/net/ethernet/qualcomm/Kconfig | 9 +++++++++
+ drivers/net/ethernet/qualcomm/Makefile | 1 +
+ 2 files changed, 10 insertions(+)
+
+--- a/drivers/net/ethernet/qualcomm/Kconfig
++++ b/drivers/net/ethernet/qualcomm/Kconfig
+@@ -62,4 +62,14 @@ config QCOM_EMAC
+
+ source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
+
++config ESSEDMA
++ tristate "Qualcomm Atheros ESS Edma support"
++ depends on OF_MDIO
++ help
++ This driver supports ethernet edma adapter.
++ Say Y to build this driver.
++
++ To compile this driver as a module, choose M here. The module
++ will be called essedma.ko.
++
+ endif # NET_VENDOR_QUALCOMM
+--- a/drivers/net/ethernet/qualcomm/Makefile
++++ b/drivers/net/ethernet/qualcomm/Makefile
+@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
+ qcauart-objs := qca_uart.o
+
+ obj-y += emac/
++obj-$(CONFIG_ESSEDMA) += essedma/
+
+ obj-$(CONFIG_RMNET) += rmnet/
--- /dev/null
+From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sun, 20 Nov 2016 01:01:10 +0100
+Subject: [PATCH] dts: ipq4019: add ethernet essedma node
+
+This patch adds the device-tree node for the ethernet
+interfaces.
+
+Note: The driver isn't anywhere close to be upstream,
+so the info might change.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -39,6 +39,8 @@
+ spi1 = &blsp1_spi2;
+ i2c0 = &blsp1_i2c3;
+ i2c1 = &blsp1_i2c4;
++ ethernet0 = &gmac0;
++ ethernet1 = &gmac1;
+ };
+
+ cpus {
+@@ -658,6 +660,64 @@
+ status = "disabled";
+ };
+
++ edma@c080000 {
++ compatible = "qcom,ess-edma";
++ reg = <0xc080000 0x8000>;
++ qcom,page-mode = <0>;
++ qcom,rx_head_buf_size = <1540>;
++ qcom,mdio_supported;
++ qcom,poll_required = <1>;
++ qcom,num_gmac = <2>;
++ interrupts = <0 65 IRQ_TYPE_EDGE_RISING
++ 0 66 IRQ_TYPE_EDGE_RISING
++ 0 67 IRQ_TYPE_EDGE_RISING
++ 0 68 IRQ_TYPE_EDGE_RISING
++ 0 69 IRQ_TYPE_EDGE_RISING
++ 0 70 IRQ_TYPE_EDGE_RISING
++ 0 71 IRQ_TYPE_EDGE_RISING
++ 0 72 IRQ_TYPE_EDGE_RISING
++ 0 73 IRQ_TYPE_EDGE_RISING
++ 0 74 IRQ_TYPE_EDGE_RISING
++ 0 75 IRQ_TYPE_EDGE_RISING
++ 0 76 IRQ_TYPE_EDGE_RISING
++ 0 77 IRQ_TYPE_EDGE_RISING
++ 0 78 IRQ_TYPE_EDGE_RISING
++ 0 79 IRQ_TYPE_EDGE_RISING
++ 0 80 IRQ_TYPE_EDGE_RISING
++ 0 240 IRQ_TYPE_EDGE_RISING
++ 0 241 IRQ_TYPE_EDGE_RISING
++ 0 242 IRQ_TYPE_EDGE_RISING
++ 0 243 IRQ_TYPE_EDGE_RISING
++ 0 244 IRQ_TYPE_EDGE_RISING
++ 0 245 IRQ_TYPE_EDGE_RISING
++ 0 246 IRQ_TYPE_EDGE_RISING
++ 0 247 IRQ_TYPE_EDGE_RISING
++ 0 248 IRQ_TYPE_EDGE_RISING
++ 0 249 IRQ_TYPE_EDGE_RISING
++ 0 250 IRQ_TYPE_EDGE_RISING
++ 0 251 IRQ_TYPE_EDGE_RISING
++ 0 252 IRQ_TYPE_EDGE_RISING
++ 0 253 IRQ_TYPE_EDGE_RISING
++ 0 254 IRQ_TYPE_EDGE_RISING
++ 0 255 IRQ_TYPE_EDGE_RISING>;
++
++ status = "disabled";
++
++ gmac0: gmac0 {
++ local-mac-address = [00 00 00 00 00 00];
++ vlan_tag = <1 0x1f>;
++ };
++
++ gmac1: gmac1 {
++ local-mac-address = [00 00 00 00 00 00];
++ qcom,phy_mdio_addr = <4>;
++ qcom,poll_required = <1>;
++ qcom,forced_speed = <1000>;
++ qcom,forced_duplex = <1>;
++ vlan_tag = <2 0x20>;
++ };
++ };
++
+ usb3_ss_phy: ssphy@9a000 {
+ compatible = "qcom,usb-ss-ipq4019-phy";
+ #phy-cells = <0>;
--- /dev/null
+From: Christian Lamparter <chunkeey@googlemail.com>
+Subject: SoC: add qualcomm syscon
+--- a/drivers/soc/qcom/Makefile
++++ b/drivers/soc/qcom/Makefile
+@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
+ obj-$(CONFIG_QCOM_SMSM) += smsm.o
+ obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
+ obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
++obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
+ obj-$(CONFIG_QCOM_APR) += apr.o
+ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
+ obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
+--- a/drivers/soc/qcom/Kconfig
++++ b/drivers/soc/qcom/Kconfig
+@@ -189,6 +189,13 @@ config QCOM_SOCINFO
+ Say yes here to support the Qualcomm socinfo driver, providing
+ information about the SoC to user space.
+
++config QCOM_TCSR
++ tristate "QCOM Top Control and Status Registers"
++ depends on ARCH_QCOM
++ help
++ Say y here to enable TCSR support. The TCSR provides control
++ functions for various peripherals.
++
+ config QCOM_WCNSS_CTRL
+ tristate "Qualcomm WCNSS control driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+--- /dev/null
++++ b/drivers/soc/qcom/qcom_tcsr.c
+@@ -0,0 +1,98 @@
++/*
++ * Copyright (c) 2014, The Linux foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License rev 2 and
++ * only rev 2 as published by the free Software foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++
++#define TCSR_USB_PORT_SEL 0xb0
++#define TCSR_USB_HSPHY_CONFIG 0xC
++
++#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
++#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
++
++#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
++#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
++#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
++
++static int tcsr_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ const struct device_node *node = pdev->dev.of_node;
++ void __iomem *base;
++ u32 val;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
++ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
++ writel(val, base + TCSR_USB_PORT_SEL);
++ }
++
++ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
++ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
++ writel(val, base + TCSR_USB_HSPHY_CONFIG);
++ }
++
++ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
++ u32 tmp = 0;
++ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
++ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
++ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
++ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
++ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
++ }
++
++ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
++ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
++ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
++ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
++ }
++
++ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
++ dev_info(&pdev->dev,
++ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
++ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
++ }
++
++ return 0;
++}
++
++static const struct of_device_id tcsr_dt_match[] = {
++ { .compatible = "qcom,tcsr", },
++ { },
++};
++
++MODULE_DEVICE_TABLE(of, tcsr_dt_match);
++
++static struct platform_driver tcsr_driver = {
++ .driver = {
++ .name = "tcsr",
++ .owner = THIS_MODULE,
++ .of_match_table = tcsr_dt_match,
++ },
++ .probe = tcsr_probe,
++};
++
++module_platform_driver(tcsr_driver);
++
++MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
++MODULE_DESCRIPTION("QCOM TCSR driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/include/dt-bindings/soc/qcom,tcsr.h
+@@ -0,0 +1,48 @@
++/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++#ifndef __DT_BINDINGS_QCOM_TCSR_H
++#define __DT_BINDINGS_QCOM_TCSR_H
++
++#define TCSR_USB_SELECT_USB3_P0 0x1
++#define TCSR_USB_SELECT_USB3_P1 0x2
++#define TCSR_USB_SELECT_USB3_DUAL 0x3
++
++/* IPQ40xx HS PHY Mode Select */
++#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
++#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
++
++/* IPQ40xx ess interface mode select */
++#define TCSR_ESS_PSGMII 0
++#define TCSR_ESS_PSGMII_RGMII5 1
++#define TCSR_ESS_PSGMII_RMII0 2
++#define TCSR_ESS_PSGMII_RMII1 4
++#define TCSR_ESS_PSGMII_RMII0_RMII1 6
++#define TCSR_ESS_PSGMII_RGMII4 9
++
++/*
++ * IPQ40xx WiFi Global Config
++ * Bit 30:AXID_EN
++ * Enable AXI master bus Axid translating to confirm all txn submitted by order
++ * Bit 24: Use locally generated socslv_wxi_bvalid
++ * 1: use locally generate socslv_wxi_bvalid for performance.
++ * 0: use SNOC socslv_wxi_bvalid.
++ */
++#define TCSR_WIFI_GLB_CFG 0x41000000
++
++/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
++#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
++
++/* TCSR A/B REG */
++#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
++#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
++
++#endif
--- /dev/null
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -15,6 +15,7 @@
+ */
+
+ #include "qcom-ipq4019.dtsi"
++#include <dt-bindings/soc/qcom,tcsr.h>
+
+ / {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+@@ -29,6 +30,32 @@
+ };
+
+ soc {
++ tcsr@194b000 {
++ /* select hostmode */
++ compatible = "qcom,tcsr";
++ reg = <0x194b000 0x100>;
++ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
++ status = "okay";
++ };
++
++ ess_tcsr@1953000 {
++ compatible = "qcom,tcsr";
++ reg = <0x1953000 0x1000>;
++ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
++ };
++
++ tcsr@1949000 {
++ compatible = "qcom,tcsr";
++ reg = <0x1949000 0x100>;
++ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
++ };
++
++ tcsr@1957000 {
++ compatible = "qcom,tcsr";
++ reg = <0x1957000 0x100>;
++ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
++ };
++
+ rng@22000 {
+ status = "ok";
+ };
+@@ -74,14 +101,6 @@
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 54 0>;
+-
+- mx25l25635e@0 {
+- #address-cells = <1>;
+- #size-cells = <1>;
+- reg = <0>;
+- compatible = "mx25l25635e";
+- spi-max-frequency = <24000000>;
+- };
+ };
+
+ serial@78af000 {
+@@ -109,5 +128,41 @@
+ wifi@a800000 {
+ status = "ok";
+ };
++
++ mdio@90000 {
++ status = "okay";
++ };
++
++ ess-switch@c000000 {
++ status = "okay";
++ };
++
++ ess-psgmii@98000 {
++ status = "okay";
++ };
++
++ edma@c080000 {
++ status = "okay";
++ };
++
++ usb3_ss_phy: ssphy@9a000 {
++ status = "okay";
++ };
++
++ usb3_hs_phy: hsphy@a6000 {
++ status = "okay";
++ };
++
++ usb3: usb3@8af8800 {
++ status = "okay";
++ };
++
++ usb2_hs_phy: hsphy@a8000 {
++ status = "okay";
++ };
++
++ usb2: usb2@60f8800 {
++ status = "okay";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+@@ -18,5 +18,73 @@
+
+ / {
+ model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
++ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1";
+
++ memory {
++ device_type = "memory";
++ reg = <0x80000000 0x10000000>;
++ };
++};
++
++&blsp1_spi1 {
++ mx25l25635f@0 {
++ compatible = "mx25l25635f", "jedec,spi-nor";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0>;
++ spi-max-frequency = <24000000>;
++
++ SBL1@0 {
++ label = "SBL1";
++ reg = <0x0 0x40000>;
++ read-only;
++ };
++ MIBIB@40000 {
++ label = "MIBIB";
++ reg = <0x40000 0x20000>;
++ read-only;
++ };
++ QSEE@60000 {
++ label = "QSEE";
++ reg = <0x60000 0x60000>;
++ read-only;
++ };
++ CDT@c0000 {
++ label = "CDT";
++ reg = <0xc0000 0x10000>;
++ read-only;
++ };
++ DDRPARAMS@d0000 {
++ label = "DDRPARAMS";
++ reg = <0xd0000 0x10000>;
++ read-only;
++ };
++ APPSBLENV@e0000 {
++ label = "APPSBLENV";
++ reg = <0xe0000 0x10000>;
++ read-only;
++ };
++ APPSBL@f0000 {
++ label = "APPSBL";
++ reg = <0xf0000 0x80000>;
++ read-only;
++ };
++ ART@170000 {
++ label = "ART";
++ reg = <0x170000 0x10000>;
++ read-only;
++ };
++ kernel@180000 {
++ label = "kernel";
++ reg = <0x180000 0x400000>;
++ };
++ rootfs@580000 {
++ label = "rootfs";
++ reg = <0x580000 0x1600000>;
++ };
++ firmware@180000 {
++ label = "firmware";
++ reg = <0x180000 0x1a00000>;
++ };
++ };
+ };
--- /dev/null
+From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Thu, 9 Mar 2017 11:03:18 +0100
+Subject: [PATCH] arm: boot: add dts files
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -903,11 +903,76 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+ qcom-apq8074-dragonboard.dtb \
+ qcom-apq8084-ifc6540.dtb \
+ qcom-apq8084-mtp.dtb \
++ qcom-ipq4018-a42.dtb \
++ qcom-ipq4018-ap120c-ac.dtb \
++ qcom-ipq4018-dap-2610.dtb \
++ qcom-ipq4018-cs-w3-wd1200g-eup.dtb \
++ qcom-ipq4018-magic-2-wifi-next.dtb \
++ qcom-ipq4018-ea6350v3.dtb \
++ qcom-ipq4018-eap1300.dtb \
++ qcom-ipq4018-ecw5211.dtb \
++ qcom-ipq4018-emd1.dtb \
++ qcom-ipq4018-emr3500.dtb \
++ qcom-ipq4018-ens620ext.dtb \
++ qcom-ipq4018-ex6100v2.dtb \
++ qcom-ipq4018-ex6150v2.dtb \
++ qcom-ipq4018-fritzbox-4040.dtb \
++ qcom-ipq4018-gl-ap1300.dtb \
++ qcom-ipq4018-jalapeno.dtb \
++ qcom-ipq4018-meshpoint-one.dtb \
++ qcom-ipq4018-cap-ac.dtb \
++ qcom-ipq4018-hap-ac2.dtb \
++ qcom-ipq4018-sxtsq-5-ac.dtb \
++ qcom-ipq4018-nbg6617.dtb \
++ qcom-ipq4019-oap100.dtb \
++ qcom-ipq4018-pa1200.dtb \
++ qcom-ipq4018-rt-ac58u.dtb \
++ qcom-ipq4018-rutx10.dtb \
++ qcom-ipq4018-wac510.dtb \
++ qcom-ipq4018-wre6606.dtb \
++ qcom-ipq4018-wrtq-329acn.dtb \
+ qcom-ipq4019-ap.dk01.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c3.dtb \
+ qcom-ipq4019-ap.dk07.1-c1.dtb \
+ qcom-ipq4019-ap.dk07.1-c2.dtb \
++ qcom-ipq4019-a62.dtb \
++ qcom-ipq4019-cm520-79f.dtb \
++ qcom-ipq4019-e2600ac-c1.dtb \
++ qcom-ipq4019-e2600ac-c2.dtb \
++ qcom-ipq4019-ea8300.dtb \
++ qcom-ipq4019-eap2200.dtb \
++ qcom-ipq4019-fritzbox-7530.dtb \
++ qcom-ipq4019-fritzrepeater-1200.dtb \
++ qcom-ipq4019-fritzrepeater-3000.dtb \
++ qcom-ipq4019-habanero-dvk.dtb \
++ qcom-ipq4019-hap-ac3.dtb \
++ qcom-ipq4019-map-ac2200.dtb \
++ qcom-ipq4019-lhgg-60ad.dtb \
++ qcom-ipq4019-mf286d.dtb \
++ qcom-ipq4019-mr8300.dtb \
++ qcom-ipq4019-pa2200.dtb \
++ qcom-ipq4019-r619ac-64m.dtb \
++ qcom-ipq4019-r619ac-128m.dtb \
++ qcom-ipq4019-rbr50.dtb \
++ qcom-ipq4019-rbs50.dtb \
++ qcom-ipq4019-rt-ac42u.dtb \
++ qcom-ipq4019-rtl30vw.dtb \
++ qcom-ipq4019-srr60.dtb \
++ qcom-ipq4019-srs60.dtb \
++ qcom-ipq4019-u4019-32m.dtb \
++ qcom-ipq4019-wifi.dtb \
++ qcom-ipq4019-wpj419.dtb \
++ qcom-ipq4019-wtr-m2133hp.dtb \
++ qcom-ipq4019-x1pro.dtb \
++ qcom-ipq4028-wpj428.dtb \
++ qcom-ipq4029-ap-303.dtb \
++ qcom-ipq4029-ap-303h.dtb \
++ qcom-ipq4029-ap-365.dtb \
++ qcom-ipq4029-gl-b1300.dtb \
++ qcom-ipq4019-gl-b2200.dtb \
++ qcom-ipq4029-gl-s1300.dtb \
++ qcom-ipq4029-mr33.dtb \
+ qcom-ipq8064-ap148.dtb \
+ qcom-ipq8064-rb3011.dtb \
+ qcom-msm8660-surf.dtb \
--- /dev/null
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+@@ -17,53 +17,79 @@
+ stdout-path = "serial0:115200n8";
+ };
+
+- memory {
+- device_type = "memory";
+- reg = <0x80000000 0x10000000>; /* 256MB */
+- };
+-
+ soc {
++ rng@22000 {
++ status = "okay";
++ };
++
+ pinctrl@1000000 {
+ serial_0_pins: serial0-pinmux {
+- pins = "gpio16", "gpio17";
+- function = "blsp_uart0";
+- bias-disable;
++ mux {
++ pins = "gpio16", "gpio17";
++ function = "blsp_uart0";
++ bias-disable;
++ };
+ };
+
+ serial_1_pins: serial1-pinmux {
+- pins = "gpio8", "gpio9",
+- "gpio10", "gpio11";
+- function = "blsp_uart1";
+- bias-disable;
++ mux {
++ pins = "gpio8", "gpio9";
++ function = "blsp_uart1";
++ bias-disable;
++ };
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+- bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
++ };
++ pinconf {
++ pins = "gpio13", "gpio14", "gpio15";
++ drive-strength = <12>;
++ bias-disable;
++ };
++ pinconf_cs {
++ pins = "gpio12";
++ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+- pins = "gpio20", "gpio21";
+- function = "blsp_i2c0";
+- bias-disable;
++ pinmux {
++ function = "blsp_i2c0";
++ pins = "gpio10", "gpio11";
++ };
++ pinconf {
++ pins = "gpio10", "gpio11";
++ drive-strength = <16>;
++ bias-disable;
++ };
+ };
+
+ nand_pins: nand-pins {
+- pins = "gpio53", "gpio55", "gpio56",
+- "gpio57", "gpio58", "gpio59",
+- "gpio60", "gpio62", "gpio63",
+- "gpio64", "gpio65", "gpio66",
+- "gpio67", "gpio68", "gpio69";
+- function = "qpic";
++ pullups {
++ pins = "gpio52", "gpio53", "gpio58",
++ "gpio59";
++ function = "qpic";
++ bias-pull-up;
++ };
++
++ pulldowns {
++ pins = "gpio54", "gpio55", "gpio56",
++ "gpio57", "gpio60", "gpio61",
++ "gpio62", "gpio63", "gpio64",
++ "gpio65", "gpio66", "gpio67",
++ "gpio68", "gpio69";
++ function = "qpic";
++ bias-pull-down;
++ };
+ };
+ };
+
+@@ -89,11 +115,11 @@
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+- m25p80@0 {
++ mx25l25635e@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+- compatible = "n25q128a11";
++ compatible = "mx25l25635e";
+ spi-max-frequency = <24000000>;
+ };
+ };
+@@ -103,9 +129,48 @@
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
++ i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
++ pinctrl-0 = <&i2c_0_pins>;
++ pinctrl-names = "default";
++
++ status = "okay";
++ };
++
+ qpic-nand@79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ };
++
++ usb3_ss_phy: ssphy@9a000 {
++ status = "okay";
++ };
++
++ usb3_hs_phy: hsphy@a6000 {
++ status = "okay";
++ };
++
++ usb3: usb3@8af8800 {
++ status = "okay";
++ };
++
++ usb2_hs_phy: hsphy@a8000 {
++ status = "okay";
++ };
++
++ usb2: usb2@60f8800 {
++ status = "okay";
++ };
++
++ cryptobam: dma@8e04000 {
++ status = "okay";
++ };
++
++ crypto@8e3a000 {
++ status = "okay";
++ };
++
++ watchdog@b017000 {
++ status = "okay";
++ };
+ };
+ };
projects / openwrt / staging / chunkeey.git / commitdiff