drm: rcar-du: lvds: Adjust operating frequency for D3 and E3

The D3 and E3 SoCs have different pixel clock frequency limits for the
LVDS encoder than the other SoCs in the Gen3 family. Adjust the mode
fixup implementation accordingly.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>

diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c
index 9f5ff1acab4eb4c2762b17de00a21384c1bacc92..9d8058d5c20a8fc63e33c1121ac1d2fa36eb2f88 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
+++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
@@ -531,11 +531,16 @@ static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
                                 const struct drm_display_mode *mode,
                                 struct drm_display_mode *adjusted_mode)
 {
+       struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
+       int min_freq;
+
        /*
         * The internal LVDS encoder has a restricted clock frequency operating
-        * range (31MHz to 148.5MHz). Clamp the clock accordingly.
+        * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
+        * 148.5MHz on all other platforms. Clamp the clock accordingly.
         */
-       adjusted_mode->clock = clamp(adjusted_mode->clock, 31000, 148500);
+       min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
+       adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
 
        return true;
 }