Tegra210: se: disable SMMU before suspending SE block
authorSamuel Payne <spayne@nvidia.com>
Mon, 12 Jun 2017 23:38:23 +0000 (16:38 -0700)
committerVarun Wadekar <vwadekar@nvidia.com>
Fri, 18 Jan 2019 17:21:50 +0000 (09:21 -0800)
This patch disables SMMU hardware before suspending the SE
block, for the context save operation to complete. The NS
word will re-enable SMMU when we exit System Suspend.

Change-Id: I4d5cd982ea6780db5c38b124550d847e3928c60d
Signed-off-by: Samuel Payne <spayne@nvidia.com>
plat/nvidia/tegra/include/t210/tegra_def.h
plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c

index 8d71cae837a148876ad50bc138424397eca7fa00..cdd7ce79bce7b69b66ee3d37942d6bdf4fe73d88 100644 (file)
 #define MC_VIDEO_PROTECT_BASE_LO       U(0x648)
 #define MC_VIDEO_PROTECT_SIZE_MB       U(0x64c)
 
+/* SMMU configuration registers*/
+#define MC_SMMU_PPCS_ASID_0            0x270UL
+#define  PPCS_SMMU_ENABLE              (0x1U << 31)
+
 /*******************************************************************************
  * Tegra SE constants
  ******************************************************************************/
index c59ec75f1cd1be1d94aa105a8640f5ff1750aeda..64c17364b7ada609a2a3790bb340b45c6277814a 100644 (file)
@@ -401,6 +401,14 @@ void tegra_se_init(void)
 int32_t tegra_se_suspend(void)
 {
        int32_t ret = 0;
+       uint32_t val = 0;
+
+       /* SE does not use SMMU in EL3, disable SMMU.
+        * This will be re-enabled by kernel on resume */
+       val = mmio_read_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0);
+       val &= ~PPCS_SMMU_ENABLE;
+       mmio_write_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0, val);
+
 
        /* Atomic context save se2 and pka1 */
        INFO("%s: SE2/PKA1 atomic context save\n", __func__);