clk: qcom: ipq4019: Add all the frequencies for apss cpu

The APSS CPU clock does not contain all the frequencies in its
frequency table so this patch adds the same.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 62a36e05dcde6721d95660fcd905d4fee59309af..b87297b9923db2b118764461faa03da611cc7fc3 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -568,10 +568,20 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
 };
 
 static const struct freq_tbl ftbl_gcc_apps_clk[] = {
-       F(48000000, P_XO,          1, 0, 0),
+       F(48000000,  P_XO,         1, 0, 0),
        F(200000000, P_FEPLL200,   1, 0, 0),
+       F(384000000, P_DDRPLLAPSS, 1, 0, 0),
+       F(413000000, P_DDRPLLAPSS, 1, 0, 0),
+       F(448000000, P_DDRPLLAPSS, 1, 0, 0),
+       F(488000000, P_DDRPLLAPSS, 1, 0, 0),
        F(500000000, P_FEPLL500,   1, 0, 0),
-       F(626000000, P_DDRPLLAPSS, 1, 0, 0),
+       F(512000000, P_DDRPLLAPSS, 1, 0, 0),
+       F(537000000, P_DDRPLLAPSS, 1, 0, 0),
+       F(565000000, P_DDRPLLAPSS, 1, 0, 0),
+       F(597000000, P_DDRPLLAPSS, 1, 0, 0),
+       F(632000000, P_DDRPLLAPSS, 1, 0, 0),
+       F(672000000, P_DDRPLLAPSS, 1, 0, 0),
+       F(716000000, P_DDRPLLAPSS, 1, 0, 0),
        { }
 };