drm/i915/psr: Don't name status or debug registers like control registers.

Avoids some typo pitfalls.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171220201021.17619-1-dhinakaran.pandiyan@intel.com

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index cc659b4b2a450f7bf55ec3583e74c40a996c443f..80dc679c0f0169098b096c164dba2333584b7069 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2591,9 +2591,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
                seq_printf(m, "Performance_Counter: %u\n", psrperf);
        }
        if (dev_priv->psr.psr2_support) {
-               u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
+               u32 psr2 = I915_READ(EDP_PSR2_STATUS);
 
-               seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
+               seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
                           psr2, psr2_live_status(psr2));
        }
        mutex_unlock(&dev_priv->psr.lock);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 43ac9be7c7460d15876eb3a41ed86728b7d35691..3dd72d4bb4e0e78a3ffb8816c28cac24a8d3f130 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4071,7 +4071,7 @@ enum {
 #define EDP_PSR_AUX_CTL                                _MMIO(dev_priv->psr_mmio_base + 0x10)
 #define EDP_PSR_AUX_DATA(i)                    _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
 
-#define EDP_PSR_STATUS_CTL                     _MMIO(dev_priv->psr_mmio_base + 0x40)
+#define EDP_PSR_STATUS                         _MMIO(dev_priv->psr_mmio_base + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK            (7<<29)
 #define   EDP_PSR_STATUS_STATE_IDLE            (0<<29)
 #define   EDP_PSR_STATUS_STATE_SRDONACK                (1<<29)
@@ -4098,7 +4098,7 @@ enum {
 #define EDP_PSR_PERF_CNT               _MMIO(dev_priv->psr_mmio_base + 0x44)
 #define   EDP_PSR_PERF_CNT_MASK                0xffffff
 
-#define EDP_PSR_DEBUG_CTL              _MMIO(dev_priv->psr_mmio_base + 0x60)
+#define EDP_PSR_DEBUG                          _MMIO(dev_priv->psr_mmio_base + 0x60)
 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
 #define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
@@ -4121,7 +4121,7 @@ enum {
 #define   EDP_PSR2_IDLE_MASK           0xf
 #define   EDP_PSR2_FRAME_BEFORE_SU(a)  ((a)<<4)
 
-#define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
+#define EDP_PSR2_STATUS                        _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
 #define EDP_PSR2_STATUS_STATE_SHIFT    28
 

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 8636503664256f612ac6612ecdbd107d24ee07d7..e9feffdea899cf869f192263695f02384e23daa6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -465,7 +465,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
                        chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
                I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
 
-               I915_WRITE(EDP_PSR_DEBUG_CTL,
+               I915_WRITE(EDP_PSR_DEBUG,
                           EDP_PSR_DEBUG_MASK_MEMUP |
                           EDP_PSR_DEBUG_MASK_HPD |
                           EDP_PSR_DEBUG_MASK_LPSP |
@@ -479,7 +479,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
                 * preventing  other hw tracking issues now we can rely
                 * on frontbuffer tracking.
                 */
-               I915_WRITE(EDP_PSR_DEBUG_CTL,
+               I915_WRITE(EDP_PSR_DEBUG,
                           EDP_PSR_DEBUG_MASK_MEMUP |
                           EDP_PSR_DEBUG_MASK_HPD |
                           EDP_PSR_DEBUG_MASK_LPSP);
@@ -589,7 +589,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
                                        0);
 
                if (dev_priv->psr.psr2_support) {
-                       psr_status = EDP_PSR2_STATUS_CTL;
+                       psr_status = EDP_PSR2_STATUS;
                        psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
 
                        I915_WRITE(EDP_PSR2_CTL,
@@ -597,7 +597,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
                                   ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
 
                } else {
-                       psr_status = EDP_PSR_STATUS_CTL;
+                       psr_status = EDP_PSR_STATUS;
                        psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
 
                        I915_WRITE(EDP_PSR_CTL,
@@ -672,19 +672,19 @@ static void intel_psr_work(struct work_struct *work)
        if (HAS_DDI(dev_priv)) {
                if (dev_priv->psr.psr2_support) {
                        if (intel_wait_for_register(dev_priv,
-                                               EDP_PSR2_STATUS_CTL,
-                                               EDP_PSR2_STATUS_STATE_MASK,
-                                               0,
-                                               50)) {
+                                                   EDP_PSR2_STATUS,
+                                                   EDP_PSR2_STATUS_STATE_MASK,
+                                                   0,
+                                                   50)) {
                                DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
                                return;
                        }
                } else {
                        if (intel_wait_for_register(dev_priv,
-                                               EDP_PSR_STATUS_CTL,
-                                               EDP_PSR_STATUS_STATE_MASK,
-                                               0,
-                                               50)) {
+                                                   EDP_PSR_STATUS,
+                                                   EDP_PSR_STATUS_STATE_MASK,
+                                                   0,
+                                                   50)) {
                                DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
                                return;
                        }