to make sure it is in the clear state.
Signed-off-by: Jason Wu <huanyu@xilinx.com>
debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__,
bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
+ writel(SPISSR_RESET_VALUE, &xilspi->regs->srr);
+
return &xilspi->slave;
}
#define SPIRFOR_OCYVAL_POS 0
#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS)
+/* SPI Software Reset Register (ssr) */
+#define SPISSR_RESET_VALUE 0x0a
+
struct xilinx_spi_slave {
struct spi_slave slave;
struct xilinx_spi_reg *regs;