Tegra: fix offset used to dump GICD registers from crash handler

The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the GICD registers,
32-bits at a time, from the paltform's crash handler.

Change-Id: If3d6608529684ecc02be6a1b715012310813b2a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/include/plat_macros.S b/plat/nvidia/tegra/include/plat_macros.S
index 01ae821e4dde48c4229b1f64df9b693b5ef55b23..2796c5d272457f2c00e17df8ffdbbfefbe835bfc 100644 (file)
--- a/plat/nvidia/tegra/include/plat_macros.S
+++ b/plat/nvidia/tegra/include/plat_macros.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -50,7 +50,7 @@ spacer:
        bl      asm_print_hex
        adr     x4, spacer
        bl      asm_print_str
-       ldr     x4, [x7], #8
+       ldr     w4, [x7], #4
        bl      asm_print_hex
        adr     x4, newline
        bl      asm_print_str