drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.

By moving the check from psr_compute_config() to psr_init_dpcd(), we get
to set the dev_priv->psr.sink_support flag only when the panel is
capable of changing power state. An additional benefit is that the check
will be performed only at init time instead of every atomic_check.

This should change the psr_basic IGT failures on HSW to skips.

v2: Return early when SET_POWER_CAPABLE bit is 0 (Jose)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106217
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106346
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180511195145.3829-2-dhinakaran.pandiyan@intel.com

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ce07bd794aed59ea807ab76aa75549e69c9c63af..37b9f62aeb6e80b5d27561282ce501efda026945 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3730,8 +3730,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
                dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
                        DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
 
-       intel_psr_init_dpcd(intel_dp);
-
        /*
         * Read the eDP display control registers.
         *
@@ -3747,6 +3745,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
                DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
                              intel_dp->edp_dpcd);
 
+       /*
+        * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
+        * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
+        */
+       intel_psr_init_dpcd(intel_dp);
+
        /* Read the eDP 1.4+ supported link rates. */
        if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
                __le16 sink_rates[DP_MAX_SUPPORTED_RATES];

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index f0ff005bc86a31edac3d6230207f747e0db5eb35..26dbb6097981cceb8c0e1f10d4ecceb98e9c0867 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -248,9 +248,13 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 
        if (!intel_dp->psr_dpcd[0])
                return;
-
        DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
                      intel_dp->psr_dpcd[0]);
+
+       if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
+               DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
+               return;
+       }
        dev_priv->psr.sink_support = true;
 
        if (INTEL_GEN(dev_priv) >= 9 &&
@@ -570,11 +574,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
                return;
        }
 
-       if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
-               DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n");
-               return;
-       }
-
        crtc_state->has_psr = true;
        crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
        DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");