arm64: dts: fsl: ls1028a: Enable eth port1 on the ls1028a QDS board

LS1028a has one Ethernet management interface. On the QDS board, the
MDIO signals are multiplexed to either on-board AR8035 PHY device or
to 4 PCIe slots allowing for SGMII cards.
To enable the Ethernet ENETC Port 1, which can only be connected to a
RGMII PHY, the multiplexer needs to be configured to route the MDIO to
the AR8035 PHY.  The MDIO/MDC routing is controlled by bits 7:4 of FPGA
board config register 0x54, and value 0 selects the on-board RGMII PHY.
The FPGA board config registers are accessible on the i2c bus, at address
0x66.

The PF3 MDIO PCIe integrated endpoint device allows for centralized access
to the MDIO bus.  Add the corresponding devicetree node and set it to be
the MDIO bus parent.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index de6ef39f3118ac27fe0a61ed347cf66b0080ab3f..663c4b728c078959b000fcf2146d340b838428ac 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -85,6 +85,26 @@
                        system-clock-frequency = <25000000>;
                };
        };
+
+       mdio-mux {
+               compatible = "mdio-mux-multiplexer";
+               mux-controls = <&mux 0>;
+               mdio-parent-bus = <&enetc_mdio_pf3>;
+               #address-cells=<1>;
+               #size-cells = <0>;
+
+               /* on-board RGMII PHY */
+               mdio@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0>;
+
+                       qds_phy1: ethernet-phy@5 {
+                               /* Atheros 8035 */
+                               reg = <5>;
+                       };
+               };
+       };
 };
 
 &duart0 {
@@ -164,6 +184,26 @@
                        };
                };
        };
+
+       fpga@66 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
+                            "simple-mfd";
+               reg = <0x66>;
+
+               mux: mux-controller {
+                       compatible = "reg-mux";
+                       #mux-control-cells = <1>;
+                       mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
+               };
+       };
+
+};
+
+&enetc_port1 {
+       phy-handle = <&qds_phy1>;
+       phy-connection-type = "rgmii-id";
 };
 
 &sai1 {

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 7975519b4f5616f9b43c180224c20ddf438ea185..de71153fda006ddf226bdeea10f7c831f9958685 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -536,6 +536,12 @@
                                compatible = "fsl,enetc";
                                reg = <0x000100 0 0 0 0>;
                        };
+                       enetc_mdio_pf3: mdio@0,3 {
+                               compatible = "fsl,enetc-mdio";
+                               reg = <0x000300 0 0 0 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
                        ethernet@0,4 {
                                compatible = "fsl,enetc-ptp";
                                reg = <0x000400 0 0 0 0>;