drm/amd/amdgpu: Tidy up gmc_v9_0_gart_enable()

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 1cb7aa2af6837ac0d7df265d0fb88347997a6de8..d7cfee80728773aac37a23215142f50cbea98653 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -719,14 +719,11 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
        if (r)
                return r;
 
-       tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
-       tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
-       WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
+       WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
 
        tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
        WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
 
-
        if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
                value = false;
        else
@@ -734,7 +731,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 
        gfxhub_v1_0_set_fault_enable_default(adev, value);
        mmhub_v1_0_set_fault_enable_default(adev, value);
-
        gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
 
        DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",