qualcommax: 301w: correct AQR reset GPIO-s

It seems that the reset GPIO-s defined for the two AQR PHY-s are actually
reversed.

Manually testing confirmed that GPIO44 is actually reset GPIO of AQR at 0,
while GPIO59 is reset of AQR at 8:
root@OpenWrt:~# mdio 9*
 DEV      PHY-ID  LINK
0x00  0x00000000  down
0x08  0x00000000  down
0x10  0x004dd0b1  down
0x11  0x004dd0b1  down
0x12  0x004dd0b1  down
0x13  0x004dd0b1  up
0x14  0x004dd0b1  down
0x15  0x04820a05  down
root@OpenWrt:~# gpioset gpiochip0 44=0
root@OpenWrt:~# mdio 9*
 DEV      PHY-ID  LINK
0x08  0x00000000  down
0x10  0x004dd0b1  down
0x11  0x004dd0b1  down
0x12  0x004dd0b1  down
0x13  0x004dd0b1  up
0x14  0x004dd0b1  down
0x15  0x04820a05  down
root@OpenWrt:~# gpioset gpiochip0 44=1
root@OpenWrt:~# mdio 9*
 DEV      PHY-ID  LINK
0x00  0x00000000  down
0x08  0x00000000  down
0x10  0x004dd0b1  down
0x11  0x004dd0b1  down
0x12  0x004dd0b1  down
0x13  0x004dd0b1  up
0x14  0x004dd0b1  down
0x15  0x04820a05  down
root@OpenWrt:~# gpioset gpiochip0 59=0
root@OpenWrt:~# mdio 9*
 DEV      PHY-ID  LINK
0x00  0x00000000  down
0x10  0x004dd0b1  down
0x11  0x004dd0b1  down
0x12  0x004dd0b1  down
0x13  0x004dd0b1  up
0x14  0x004dd0b1  down
0x15  0x04820a05  down
root@OpenWrt:~# gpioset gpiochip0 59=1
root@OpenWrt:~# mdio 9*
 DEV      PHY-ID  LINK
0x00  0x00000000  down
0x08  0x00000000  down
0x10  0x004dd0b1  down
0x11  0x004dd0b1  down
0x12  0x004dd0b1  down
0x13  0x004dd0b1  up
0x14  0x004dd0b1  down
0x15  0x04820a05  down

Signed-off-by: Robert Marko <robimarko@gmail.com>

diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
index 8ce22c1c06943ff01753d7006b0635e326d08300..8b392c0fbabf71148fe74201bbb3eee65ef90a36 100644 (file)
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
@@ -275,14 +275,14 @@
        aqr113c_0: ethernet-phy@0 {
                compatible ="ethernet-phy-ieee802.3-c45";
                reg = <0>;
-               reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+               reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
                firmware-name = "marvell/AQR-G4_v5.4.C-AQR_CIG_WF-1945_0x0_ID44778_VER1630.cld";
        };
 
        aqr113c_8: ethernet-phy@8 {
                compatible ="ethernet-phy-ieee802.3-c45";
                reg = <8>;
-               reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+               reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
                firmware-name = "marvell/AQR-G4_v5.4.C-AQR_CIG_WF-1945_0x8_ID44776_VER1630.cld";
        };