return err;
}
+ mutex_lock(&dc->regs_mutex);
+
/* program display mode */
tegra_dc_set_timings(dc, mode);
tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_NOKEY);
tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_1WIN);
+ mutex_unlock(&dc->regs_mutex);
+
return 0;
}
else
syncpt = SYNCPT_VBLANK0;
+ mutex_lock(&dc->regs_mutex);
+
/* initialize display controller */
tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
+
+ mutex_unlock(&dc->regs_mutex);
}
static void tegra_crtc_commit(struct drm_crtc *crtc)
update_mask = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
+ mutex_lock(&dc->regs_mutex);
+
tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
value = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
+
+ mutex_unlock(&dc->regs_mutex);
}
static void tegra_crtc_load_lut(struct drm_crtc *crtc)
return -ENOMEM;
INIT_LIST_HEAD(&dc->list);
+ mutex_init(&dc->regs_mutex);
dc->dev = &pdev->dev;
dc->clk = devm_clk_get(&pdev->dev, NULL);