Different targets have different cache line sizes.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45163
FLASH_OFFS :=
FLASH_MAX :=
PLATFORM :=
+CACHELINE_SIZE := 32
CC := $(CROSS_COMPILE)gcc
LD := $(CROSS_COMPILE)ld
-fno-common -ffreestanding -fhonour-copts \
-mabi=32 -march=mips32r2 \
-Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap \
- -DCONFIG_CACHELINE_SIZE=32 -DKERNEL_ADDR=$(KERNEL_ADDR)
+ -DCONFIG_CACHELINE_SIZE=$(CACHELINE_SIZE) \
+ -DKERNEL_ADDR=$(KERNEL_ADDR)
ASFLAGS = $(CFLAGS) -D__ASSEMBLY__