ipq806x: force 2nd pci slot into gen1 mode
authorPavel Kubelun <be.dissent@gmail.com>
Thu, 6 Jul 2017 14:20:18 +0000 (17:20 +0300)
committerFelix Fietkau <nbd@nbd.name>
Wed, 17 Jan 2018 10:02:05 +0000 (11:02 +0100)
According to QSDK and OEM tarballs (checked c2600, r7500v2, r7800) 2nd pci slot (pci1, 2,4 GHz card)) on ap148 based boards should operate in gen1 mode.
EA8500 is an exception and according to GPL pcie0 should operate in gen1 mode.

In previous commit we've added the support for this option, so enable it in DT for affected devices.

QSDK ref:
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?h=release/endive_preview_cc&id=f3b07fe309027c52fc163149500cedddd707c506

While at it move the phy transmit termination offset value into dtsi file as it's platform specific.

Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8065-r7800.dts

index fa4f05bdbeb4195784c246444b8c347ee8b73c9f..39a0d96563cb921c4f98de95208b46379d4ce48c 100644 (file)
 
                pcie0: pci@1b500000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
 
                pcie1: pci@1b700000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
+                       force_gen1 = <1>;
                };
 
                nand@1ac00000 {
index 80bc5dfa04677f46d49e922f2fd52968743c1a28..a4fd13429c29948796b5cc2b8b057c4a373910f3 100644 (file)
 
                pcie0: pci@1b500000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
 
                pcie1: pci@1b700000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
+                       force_gen1 = <1>;
                };
 
                mdio0: mdio {
index c1a4c82a285ea74f94af276f752e2851eaf0d54e..b7c49cc816b13d3e2a140ec6679bc381cac38ccb 100644 (file)
                        reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
                        pinctrl-0 = <&pcie1_pins>;
                        pinctrl-names = "default";
+                       force_gen1 = <1>;
                };
 
                nand@1ac00000 {
index 761fa43179f6347c7fc1c6b3a3a48621ff56997e..a8628ff938e4bea21c5ff20b5bc8bb024fe371e8 100644 (file)
 
                pcie0: pci@1b500000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
+                       force_gen1 = <1>;
                };
 
                pcie1: pci@1b700000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
-               
+
                pcie2: pci@1b900000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
-               
+
                nand@1ac00000 {
                        status = "ok";
 
index 2ea856d88b5bed17a870120b6b3617ce9c686484..3445a79251e7d675867edc54b91d4799f548614f 100644 (file)
 
                pcie1: pci@1b700000 {
                        status = "ok";
+                       force_gen1 = <1>;
                };
 
                nand@1ac00000 {
index a21cf18bee6df5bc6a6c444da7d44d1165e1dfa3..c4b0c4b5a7f7dfc8cf01b85b3e0e3388ad2c69bf 100644 (file)
                        reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
                        pinctrl-0 = <&pcie1_pins>;
                        pinctrl-names = "default";
+                       force_gen1 = <1>;
                };
 
                nand@1ac00000 {
index b55a98d229c03e1deec578f9d4302bfa6b09725c..561c49aaa67b0cc8ec157180dce675aef90708df 100644 (file)
 
                pcie0: pci@1b500000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
 
                pcie1: pci@1b700000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
+                       force_gen1 = <1>;
                };
 
                mdio0: mdio {
index 9996bd74151a3db1d9516a178e07e6470b134373..4b93fea98aa1da3eaf2ecf7a70158d7b55c59430 100644 (file)
 
                        perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
 
+                       phy-tx0-term-offset = <7>;
+
                        status = "disabled";
                };
 
 
                        perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
 
+                       phy-tx0-term-offset = <7>;
+
                        status = "disabled";
                };
 
 
                        perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
 
+                       phy-tx0-term-offset = <7>;
+
                        status = "disabled";
                };
 
index 15165b9b72d9352386cb1fbef8239b3d4946628e..987ee852cc8fa5222cfd2e18fa712f8cf72d21b3 100644 (file)
                        reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
                        pinctrl-0 = <&pcie1_pins>;
                        pinctrl-names = "default";
+                       force_gen1 = <1>;
                };
 
                mdio0: mdio {
index 403054cc97fe4be1909f600fe94c785e2c98bd1b..4c89dcf76f873aceb792a2d8a6c346a4c633b731 100644 (file)
 
                pcie0: pci@1b500000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
                };
 
                pcie1: pci@1b700000 {
                        status = "ok";
-                       phy-tx0-term-offset = <7>;
+                       force_gen1 = <1>;
                };
 
                nand@1ac00000 {