};
static const struct of_device_id tegra_fuse_match[] = {
+#ifdef CONFIG_ARCH_TEGRA_186_SOC
+ { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
+#endif
#ifdef CONFIG_ARCH_TEGRA_210_SOC
{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
#endif
defined(CONFIG_ARCH_TEGRA_114_SOC) || \
defined(CONFIG_ARCH_TEGRA_124_SOC) || \
defined(CONFIG_ARCH_TEGRA_132_SOC) || \
- defined(CONFIG_ARCH_TEGRA_210_SOC)
+ defined(CONFIG_ARCH_TEGRA_210_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_186_SOC)
static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
{
return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
fuse->read = tegra30_fuse_read;
tegra_init_revision();
- fuse->soc->speedo_init(&tegra_sku_info);
+
+ if (fuse->soc->speedo_init)
+ fuse->soc->speedo_init(&tegra_sku_info);
+
tegra30_fuse_add_randomness();
}
#endif
.info = &tegra210_fuse_info,
};
#endif
+
+#if defined(CONFIG_ARCH_TEGRA_186_SOC)
+static const struct tegra_fuse_info tegra186_fuse_info = {
+ .read = tegra30_fuse_read,
+ .size = 0x300,
+ .spare = 0x280,
+};
+
+const struct tegra_fuse_soc tegra186_fuse_soc = {
+ .init = tegra30_fuse_init,
+ .info = &tegra186_fuse_info,
+};
+#endif