clk: rockchip: add 400MHz to rk3066 clock rates table

We need this to init PLL_CPLL to 400MHz at boot.

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index a6d398f4b18f2df6544b241c2d834bdc69805ad1..062ef4960244a54ba1f8c85a45d4bc3449111f39 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3188_pll_rates[] = {
        RK3066_PLL_RATE( 504000000, 1, 84, 4),
        RK3066_PLL_RATE( 456000000, 1, 76, 4),
        RK3066_PLL_RATE( 408000000, 1, 68, 4),
+       RK3066_PLL_RATE( 400000000, 3, 100, 2),
        RK3066_PLL_RATE( 384000000, 2, 128, 4),
        RK3066_PLL_RATE( 360000000, 1, 60, 4),
        RK3066_PLL_RATE( 312000000, 1, 52, 4),