ddr: socfpga: Clean up EMIF reset

The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index b450a1b1be0a8f1d439fcbb9499ed761af0d8219..ff83c6100273a80cacc141402479c3c5880f47e3 100644 (file)
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -108,28 +108,6 @@ static int is_sdram_cal_success(void)
        return readl(&socfpga_ecc_hmc_base->ddrcalstat);
 }
 
-static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
-{
-       u32 reg = readl(ereg);
-
-       return (reg & BIT(bit)) ? 1 : 0;
-}
-
-static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
-                          u32 expected, u32 timeout_usec)
-{
-       u32 tmr;
-
-       for (tmr = 0; tmr < timeout_usec; tmr += 100) {
-               udelay(100);
-               WATCHDOG_RESET();
-               if (ddr_get_bit(ereg, bit) == expected)
-                       return 0;
-       }
-
-       return 1;
-}
-
 static int emif_clear(void)
 {
        writel(0, DDR_REG_CORE2SEQ);
@@ -162,13 +140,16 @@ static int emif_reset(void)
 
        writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 
-       if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+       ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
+                               SEQ2CORE_INT_RESP_BIT, false, 1000, false);
+       if (ret) {
                debug("emif_reset failed to see interrupt acknowledge\n");
-               return -EPERM;
-       } else {
-               debug("emif_reset interrupt acknowledged\n");
+               emif_clear();
+               return ret;
        }
 
+       mdelay(1);
+
        ret = emif_clear();
        if (ret) {
                debug("emif_clear() failed\n");