drm/amdgpu: Add first_non_cp and last_non_cp in amdgpu_doorbell_index
authorYong Zhao <Yong.Zhao@amd.com>
Wed, 13 Feb 2019 18:13:50 +0000 (13:13 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 18 Feb 2019 23:00:16 +0000 (18:00 -0500)
They will be used to inform KFD the doorbell range not usable for CP.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

index 43546500ec26c411d55235da6a1d9ce60d04800e..5587fac671bbe94848a527f662ff49ca1e4a891b 100644 (file)
@@ -69,6 +69,8 @@ struct amdgpu_doorbell_index {
                        uint32_t vce_ring6_7;
                } uvd_vce;
        };
+       uint32_t first_non_cp;
+       uint32_t last_non_cp;
        uint32_t max_assignment;
        /* Per engine SDMA doorbell size in dword */
        uint32_t sdma_doorbell_range;
@@ -139,6 +141,10 @@ typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
        AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3             = 0x18D,
        AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5             = 0x18E,
        AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7             = 0x18F,
+
+       AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP            = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0,
+       AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP             = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
+
        AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT            = 0x18F,
        AMDGPU_VEGA20_DOORBELL_INVALID                   = 0xFFFF
 } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
@@ -214,6 +220,9 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
        AMDGPU_DOORBELL64_VCE_RING4_5             = 0xFE,
        AMDGPU_DOORBELL64_VCE_RING6_7             = 0xFF,
 
+       AMDGPU_DOORBELL64_FIRST_NON_CP            = AMDGPU_DOORBELL64_sDMA_ENGINE0,
+       AMDGPU_DOORBELL64_LAST_NON_CP             = AMDGPU_DOORBELL64_VCE_RING6_7,
+
        AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,
        AMDGPU_DOORBELL64_INVALID                 = 0xFFFF
 } AMDGPU_DOORBELL64_ASSIGNMENT;
index 62f49c8953142737da71ac7ac0e21080029738dc..5e9e53143a8ea81edd9943d772b769c109b5654e 100644 (file)
@@ -79,6 +79,10 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
        adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3;
        adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5;
        adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
+
+       adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL64_FIRST_NON_CP;
+       adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP;
+
        /* In unit of dword doorbell */
        adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
        adev->doorbell_index.sdma_doorbell_range = 4;
index 1271e1702ad4472944754737a0f32f129e09c4ce..fb6398e38be97f2a73d43d65eded1e0ffeb4e9b9 100644 (file)
@@ -83,6 +83,10 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
        adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3;
        adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
        adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
+
+       adev->doorbell_index.first_non_cp = AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP;
+       adev->doorbell_index.last_non_cp = AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP;
+
        adev->doorbell_index.max_assignment = AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT << 1;
        adev->doorbell_index.sdma_doorbell_range = 20;
 }