Merge branch 'x86-microcode-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

* 'x86-microcode-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, microcode, AMD: Add microcode revision to /proc/cpuinfo
  x86, microcode: Correct microcode revision format
  coretemp: Get microcode revision from cpu_data
  x86, intel: Use c->microcode for Atom errata check
  x86, intel: Output microcode revision in /proc/cpuinfo
  x86, microcode: Don't request microcode from userspace unnecessarily

Fix up trivial conflicts in arch/x86/kernel/cpu/amd.c (conflict between
moving AMD BSP code to cpu_dev helper function and adding AMD microcode
revision to /proc/cpuinfo code)

diff --cc arch/x86/kernel/cpu/amd.c
index 13c6ec81254582e69eae8b6c69b703370b25fb18,d898fab0e125341907fd896242855ad108ec8095..46ae4f65fc7f915e9da6b0442a131f813a60fe2c
--- 1/arch/x86/kernel/cpu/amd.c
--- 2/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@@ -411,36 -410,10 +411,38 @@@ static void __cpuinit early_init_amd_mc
  #endif
  }
  
 +static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c)
 +{
 +      if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
 +
 +              if (c->x86 > 0x10 ||
 +                  (c->x86 == 0x10 && c->x86_model >= 0x2)) {
 +                      u64 val;
 +
 +                      rdmsrl(MSR_K7_HWCR, val);
 +                      if (!(val & BIT(24)))
 +                              printk(KERN_WARNING FW_BUG "TSC doesn't count "
 +                                      "with P0 frequency!\n");
 +              }
 +      }
 +
 +      if (c->x86 == 0x15) {
 +              unsigned long upperbit;
 +              u32 cpuid, assoc;
 +
 +              cpuid    = cpuid_edx(0x80000005);
 +              assoc    = cpuid >> 16 & 0xff;
 +              upperbit = ((cpuid >> 24) << 10) / assoc;
 +
 +              va_align.mask     = (upperbit - 1) & PAGE_MASK;
 +              va_align.flags    = ALIGN_VA_32 | ALIGN_VA_64;
 +      }
 +}
 +
  static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
  {
+       u32 dummy;
+ 
        early_init_amd_mc(c);
  
        /*
@@@ -470,6 -443,25 +472,8 @@@
                        set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
        }
  #endif
 -
 -      /* We need to do the following only once */
 -      if (c != &boot_cpu_data)
 -              return;
 -
 -      if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
 -
 -              if (c->x86 > 0x10 ||
 -                  (c->x86 == 0x10 && c->x86_model >= 0x2)) {
 -                      u64 val;
 -
 -                      rdmsrl(MSR_K7_HWCR, val);
 -                      if (!(val & BIT(24)))
 -                              printk(KERN_WARNING FW_BUG "TSC doesn't count "
 -                                      "with P0 frequency!\n");
 -              }
 -      }
+ 
+       rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
  }
  
  static void __cpuinit init_amd(struct cpuinfo_x86 *c)

diff --cc arch/x86/kernel/cpu/mcheck/mce.c
Simple merge