--- /dev/null
+From 6463c10bfdbd684ec7ecfd408ea541283215a088 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:06:28 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq8074: add A53 PLL node
+
+Add the required node for A53 PLL which will be used to provide the CPU
+clock via APCS for APSS scaling.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220628.339366-9-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -675,6 +675,14 @@
+ #mbox-cells = <1>;
+ };
+
++ a53pll: clock@b116000 {
++ compatible = "qcom,ipq8074-a53pll";
++ reg = <0x0b116000 0x40>;
++ #clock-cells = <0>;
++ clocks = <&xo>;
++ clock-names = "xo";
++ };
++
+ timer@b120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
--- /dev/null
+From e593e834fe8ba9bf314d8215ac05d8787f81efda Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:02:42 +0200
+Subject: [PATCH] thermal/drivers/tsens: Add support for combined interrupt
+
+Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
+signaling both up/low and critical trips.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220245.338396-2-robimarko@gmail.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/qcom/tsens-8960.c | 1 +
+ drivers/thermal/qcom/tsens-v0_1.c | 1 +
+ drivers/thermal/qcom/tsens-v1.c | 1 +
+ drivers/thermal/qcom/tsens-v2.c | 1 +
+ drivers/thermal/qcom/tsens.c | 38 ++++++++++++++++++++++++++-----
+ drivers/thermal/qcom/tsens.h | 2 ++
+ 6 files changed, 38 insertions(+), 6 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens-8960.c
++++ b/drivers/thermal/qcom/tsens-8960.c
+@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
+ static struct tsens_features tsens_8960_feat = {
+ .ver_major = VER_0,
+ .crit_int = 0,
++ .combo_int = 0,
+ .adc = 1,
+ .srot_split = 0,
+ .max_sensors = 11,
+--- a/drivers/thermal/qcom/tsens-v0_1.c
++++ b/drivers/thermal/qcom/tsens-v0_1.c
+@@ -549,6 +549,7 @@ static int __init init_8939(struct tsens
+ static struct tsens_features tsens_v0_1_feat = {
+ .ver_major = VER_0_1,
+ .crit_int = 0,
++ .combo_int = 0,
+ .adc = 1,
+ .srot_split = 1,
+ .max_sensors = 11,
+--- a/drivers/thermal/qcom/tsens-v1.c
++++ b/drivers/thermal/qcom/tsens-v1.c
+@@ -273,6 +273,7 @@ static int calibrate_8976(struct tsens_p
+ static struct tsens_features tsens_v1_feat = {
+ .ver_major = VER_1_X,
+ .crit_int = 0,
++ .combo_int = 0,
+ .adc = 1,
+ .srot_split = 1,
+ .max_sensors = 11,
+--- a/drivers/thermal/qcom/tsens-v2.c
++++ b/drivers/thermal/qcom/tsens-v2.c
+@@ -31,6 +31,7 @@
+ static struct tsens_features tsens_v2_feat = {
+ .ver_major = VER_2_X,
+ .crit_int = 1,
++ .combo_int = 0,
+ .adc = 0,
+ .srot_split = 1,
+ .max_sensors = 16,
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -532,6 +532,27 @@ static irqreturn_t tsens_irq_thread(int
+ return IRQ_HANDLED;
+ }
+
++/**
++ * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
++ * @irq: irq number
++ * @data: tsens controller private data
++ *
++ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
++ * critical handler first and then the up/low one.
++ *
++ * Return: IRQ_HANDLED
++ */
++static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
++{
++ irqreturn_t ret;
++
++ ret = tsens_critical_irq_thread(irq, data);
++ if (ret != IRQ_HANDLED)
++ return ret;
++
++ return tsens_irq_thread(irq, data);
++}
++
+ static int tsens_set_trips(struct thermal_zone_device *tz, int low, int high)
+ {
+ struct tsens_sensor *s = tz->devdata;
+@@ -1074,13 +1095,18 @@ static int tsens_register(struct tsens_p
+ tsens_mC_to_hw(priv->sensor, 0));
+ }
+
+- ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
+- if (ret < 0)
+- return ret;
++ if (priv->feat->combo_int) {
++ ret = tsens_register_irq(priv, "combined",
++ tsens_combined_irq_thread);
++ } else {
++ ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
++ if (ret < 0)
++ return ret;
+
+- if (priv->feat->crit_int)
+- ret = tsens_register_irq(priv, "critical",
+- tsens_critical_irq_thread);
++ if (priv->feat->crit_int)
++ ret = tsens_register_irq(priv, "critical",
++ tsens_critical_irq_thread);
++ }
+
+ return ret;
+ }
+--- a/drivers/thermal/qcom/tsens.h
++++ b/drivers/thermal/qcom/tsens.h
+@@ -493,6 +493,7 @@ enum regfield_ids {
+ * struct tsens_features - Features supported by the IP
+ * @ver_major: Major number of IP version
+ * @crit_int: does the IP support critical interrupts?
++ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
+ * @adc: do the sensors only output adc code (instead of temperature)?
+ * @srot_split: does the IP neatly splits the register space into SROT and TM,
+ * with SROT only being available to secure boot firmware?
+@@ -502,6 +503,7 @@ enum regfield_ids {
+ struct tsens_features {
+ unsigned int ver_major;
+ unsigned int crit_int:1;
++ unsigned int combo_int:1;
+ unsigned int adc:1;
+ unsigned int srot_split:1;
+ unsigned int has_watchdog:1;
--- /dev/null
+From 7805365fee582056b32c69cf35aafbb94b14a8ca Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:02:43 +0200
+Subject: [PATCH] thermal/drivers/tsens: Allow configuring min and max trips
+
+IPQ8074 and IPQ6018 dont support negative trip temperatures and support
+up to 204 degrees C as the max trip temperature.
+
+So, instead of always setting the -40 as min and 120 degrees C as max
+allow it to be configured as part of the features.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220818220245.338396-3-robimarko@gmail.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/qcom/tsens-8960.c | 2 ++
+ drivers/thermal/qcom/tsens-v0_1.c | 2 ++
+ drivers/thermal/qcom/tsens-v1.c | 2 ++
+ drivers/thermal/qcom/tsens-v2.c | 2 ++
+ drivers/thermal/qcom/tsens.c | 4 ++--
+ drivers/thermal/qcom/tsens.h | 4 ++++
+ 6 files changed, 14 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens-8960.c
++++ b/drivers/thermal/qcom/tsens-8960.c
+@@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_
+ .adc = 1,
+ .srot_split = 0,
+ .max_sensors = 11,
++ .trip_min_temp = -40000,
++ .trip_max_temp = 120000,
+ };
+
+ struct tsens_plat_data data_8960 = {
+--- a/drivers/thermal/qcom/tsens-v0_1.c
++++ b/drivers/thermal/qcom/tsens-v0_1.c
+@@ -553,6 +553,8 @@ static struct tsens_features tsens_v0_1_
+ .adc = 1,
+ .srot_split = 1,
+ .max_sensors = 11,
++ .trip_min_temp = -40000,
++ .trip_max_temp = 120000,
+ };
+
+ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
+--- a/drivers/thermal/qcom/tsens-v1.c
++++ b/drivers/thermal/qcom/tsens-v1.c
+@@ -277,6 +277,8 @@ static struct tsens_features tsens_v1_fe
+ .adc = 1,
+ .srot_split = 1,
+ .max_sensors = 11,
++ .trip_min_temp = -40000,
++ .trip_max_temp = 120000,
+ };
+
+ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
+--- a/drivers/thermal/qcom/tsens-v2.c
++++ b/drivers/thermal/qcom/tsens-v2.c
+@@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_fe
+ .adc = 0,
+ .srot_split = 1,
+ .max_sensors = 16,
++ .trip_min_temp = -40000,
++ .trip_max_temp = 120000,
+ };
+
+ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -573,8 +573,8 @@ static int tsens_set_trips(struct therma
+ dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
+ hw_id, __func__, low, high);
+
+- cl_high = clamp_val(high, -40000, 120000);
+- cl_low = clamp_val(low, -40000, 120000);
++ cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
++ cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
+
+ high_val = tsens_mC_to_hw(s, cl_high);
+ low_val = tsens_mC_to_hw(s, cl_low);
+--- a/drivers/thermal/qcom/tsens.h
++++ b/drivers/thermal/qcom/tsens.h
+@@ -499,6 +499,8 @@ enum regfield_ids {
+ * with SROT only being available to secure boot firmware?
+ * @has_watchdog: does this IP support watchdog functionality?
+ * @max_sensors: maximum sensors supported by this version of the IP
++ * @trip_min_temp: minimum trip temperature supported by this version of the IP
++ * @trip_max_temp: maximum trip temperature supported by this version of the IP
+ */
+ struct tsens_features {
+ unsigned int ver_major;
+@@ -508,6 +510,8 @@ struct tsens_features {
+ unsigned int srot_split:1;
+ unsigned int has_watchdog:1;
+ unsigned int max_sensors;
++ int trip_min_temp;
++ int trip_max_temp;
+ };
+
+ /**
--- /dev/null
+From 0164d794cbc58488a7321272e95958d10cf103a4 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:02:44 +0200
+Subject: [PATCH] thermal/drivers/tsens: Add IPQ8074 support
+
+Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP
+it only has one IRQ, that is used for up/low as well as critical.
+It also does not support negative trip temperatures.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220818220245.338396-4-robimarko@gmail.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++
+ drivers/thermal/qcom/tsens.c | 3 +++
+ drivers/thermal/qcom/tsens.h | 2 +-
+ 3 files changed, 21 insertions(+), 1 deletion(-)
+
+--- a/drivers/thermal/qcom/tsens-v2.c
++++ b/drivers/thermal/qcom/tsens-v2.c
+@@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_fe
+ .trip_max_temp = 120000,
+ };
+
++static struct tsens_features ipq8074_feat = {
++ .ver_major = VER_2_X,
++ .crit_int = 1,
++ .combo_int = 1,
++ .adc = 0,
++ .srot_split = 1,
++ .max_sensors = 16,
++ .trip_min_temp = 0,
++ .trip_max_temp = 204000,
++};
++
+ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
+ /* ----- SROT ------ */
+ /* VERSION */
+@@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = {
+ .fields = tsens_v2_regfields,
+ };
+
++struct tsens_plat_data data_ipq8074 = {
++ .ops = &ops_generic_v2,
++ .feat = &ipq8074_feat,
++ .fields = tsens_v2_regfields,
++};
++
+ /* Kept around for backward compatibility with old msm8996.dtsi */
+ struct tsens_plat_data data_8996 = {
+ .num_sensors = 13,
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -981,6 +981,9 @@ static const struct of_device_id tsens_t
+ .compatible = "qcom,ipq8064-tsens",
+ .data = &data_8960,
+ }, {
++ .compatible = "qcom,ipq8074-tsens",
++ .data = &data_ipq8074,
++ }, {
+ .compatible = "qcom,mdm9607-tsens",
+ .data = &data_9607,
+ }, {
+--- a/drivers/thermal/qcom/tsens.h
++++ b/drivers/thermal/qcom/tsens.h
+@@ -597,6 +597,6 @@ extern struct tsens_plat_data data_8916,
+ extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
+
+ /* TSENS v2 targets */
+-extern struct tsens_plat_data data_8996, data_tsens_v2;
++extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
+
+ #endif /* __QCOM_TSENS_H__ */
--- /dev/null
+From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:02:45 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
+
+IPQ8074 has a tsens v2.3.0 peripheral which monitors
+temperatures around the various subsystems on the
+die.
+
+So lets add the tsens and thermal zone nodes, passive
+CPU cooling will come in later patches after CPU frequency
+scaling is supported.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
+ 1 file changed, 96 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -274,6 +274,16 @@
+ status = "disabled";
+ };
+
++ tsens: thermal-sensor@4a9000 {
++ compatible = "qcom,ipq8074-tsens";
++ reg = <0x4a9000 0x1000>, /* TM */
++ <0x4a8000 0x1000>; /* SROT */
++ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "combined";
++ #qcom,sensors = <16>;
++ #thermal-sensor-cells = <1>;
++ };
++
+ cryptobam: dma-controller@704000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x00704000 0x20000>;
+@@ -874,4 +884,90 @@
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
++
++ thermal-zones {
++ nss-top-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 4>;
++ };
++
++ nss0-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 5>;
++ };
++
++ nss1-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 6>;
++ };
++
++ wcss-phya0-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 7>;
++ };
++
++ wcss-phya1-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 8>;
++ };
++
++ cpu0_thermal: cpu0-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 9>;
++ };
++
++ cpu1_thermal: cpu1-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 10>;
++ };
++
++ cpu2_thermal: cpu2-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 11>;
++ };
++
++ cpu3_thermal: cpu3-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 12>;
++ };
++
++ cluster_thermal: cluster-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 13>;
++ };
++
++ wcss-phyb0-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 14>;
++ };
++
++ wcss-phyb1-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&tsens 15>;
++ };
++ };
+ };
--- /dev/null
+From 0df592a0a1a3fff9133977192677aa915afc174f Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:08:49 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq8074: add clocks to APCS
+
+APCS now has support for providing the APSS clocks as the child device
+for IPQ8074.
+
+So, add the A53 PLL and XO clocks in order to use APCS as the CPU
+clocksource for APSS scaling.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -680,6 +680,8 @@
+ apcs_glb: mailbox@b111000 {
+ compatible = "qcom,ipq8074-apcs-apps-global";
+ reg = <0x0b111000 0x1000>;
++ clocks = <&a53pll>, <&xo>;
++ clock-names = "pll", "xo";
+
+ #clock-cells = <1>;
+ #mbox-cells = <1>;
--- /dev/null
+From e6c5115d6845f25eda7e162dcd783a2044215867 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sun, 30 Oct 2022 18:57:01 +0100
+Subject: [PATCH] clk: qcom: ipq8074: convert to parent data
+
+Convert the IPQ8074 GCC driver to use parent data instead of global
+name matching.
+
+Utilize ARRAY_SIZE for num_parents instead of hardcoding the value.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221030175703.1103224-1-robimarko@gmail.com
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 1781 +++++++++++++++-----------------
+ 1 file changed, 813 insertions(+), 968 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -49,349 +49,6 @@ enum {
+ P_UNIPHY2_TX,
+ };
+
+-static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
+- "xo",
+- "gpll0",
+- "gpll0_out_main_div2",
+-};
+-
+-static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+- { P_XO, 0 },
+- { P_GPLL0, 1 },
+- { P_GPLL0_DIV2, 4 },
+-};
+-
+-static const struct parent_map gcc_xo_gpll0_map[] = {
+- { P_XO, 0 },
+- { P_GPLL0, 1 },
+-};
+-
+-static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
+- "xo",
+- "gpll0",
+- "gpll2",
+- "gpll0_out_main_div2",
+-};
+-
+-static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
+- { P_XO, 0 },
+- { P_GPLL0, 1 },
+- { P_GPLL2, 2 },
+- { P_GPLL0_DIV2, 4 },
+-};
+-
+-static const char * const gcc_xo_gpll0_sleep_clk[] = {
+- "xo",
+- "gpll0",
+- "sleep_clk",
+-};
+-
+-static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
+- { P_XO, 0 },
+- { P_GPLL0, 2 },
+- { P_SLEEP_CLK, 6 },
+-};
+-
+-static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
+- "xo",
+- "gpll6",
+- "gpll0",
+- "gpll0_out_main_div2",
+-};
+-
+-static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
+- { P_XO, 0 },
+- { P_GPLL6, 1 },
+- { P_GPLL0, 3 },
+- { P_GPLL0_DIV2, 4 },
+-};
+-
+-static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
+- "xo",
+- "gpll0_out_main_div2",
+- "gpll0",
+-};
+-
+-static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
+- { P_XO, 0 },
+- { P_GPLL0_DIV2, 2 },
+- { P_GPLL0, 1 },
+-};
+-
+-static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
+- "usb3phy_0_cc_pipe_clk",
+- "xo",
+-};
+-
+-static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
+- { P_USB3PHY_0_PIPE, 0 },
+- { P_XO, 2 },
+-};
+-
+-static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
+- "usb3phy_1_cc_pipe_clk",
+- "xo",
+-};
+-
+-static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
+- { P_USB3PHY_1_PIPE, 0 },
+- { P_XO, 2 },
+-};
+-
+-static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
+- "pcie20_phy0_pipe_clk",
+- "xo",
+-};
+-
+-static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
+- { P_PCIE20_PHY0_PIPE, 0 },
+- { P_XO, 2 },
+-};
+-
+-static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
+- "pcie20_phy1_pipe_clk",
+- "xo",
+-};
+-
+-static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
+- { P_PCIE20_PHY1_PIPE, 0 },
+- { P_XO, 2 },
+-};
+-
+-static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
+- "xo",
+- "gpll0",
+- "gpll6",
+- "gpll0_out_main_div2",
+-};
+-
+-static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
+- { P_XO, 0 },
+- { P_GPLL0, 1 },
+- { P_GPLL6, 2 },
+- { P_GPLL0_DIV2, 4 },
+-};
+-
+-static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
+- "xo",
+- "gpll0",
+- "gpll6",
+- "gpll0_out_main_div2",
+-};
+-
+-static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
+- { P_XO, 0 },
+- { P_GPLL0, 1 },
+- { P_GPLL6, 2 },
+- { P_GPLL0_DIV2, 3 },
+-};
+-
+-static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
+- "xo",
+- "bias_pll_nss_noc_clk",
+- "gpll0",
+- "gpll2",
+-};
+-
+-static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
+- { P_XO, 0 },
+- { P_BIAS_PLL_NSS_NOC, 1 },
+- { P_GPLL0, 2 },
+- { P_GPLL2, 3 },
+-};
+-
+-static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
+- "xo",
+- "nss_crypto_pll",
+- "gpll0",
+-};
+-
+-static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
+- { P_XO, 0 },
+- { P_NSS_CRYPTO_PLL, 1 },
+- { P_GPLL0, 2 },
+-};
+-
+-static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
+- "xo",
+- "ubi32_pll",
+- "gpll0",
+- "gpll2",
+- "gpll4",
+- "gpll6",
+-};
+-
+-static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
+- { P_XO, 0 },
+- { P_UBI32_PLL, 1 },
+- { P_GPLL0, 2 },
+- { P_GPLL2, 3 },
+- { P_GPLL4, 4 },
+- { P_GPLL6, 5 },
+-};
+-
+-static const char * const gcc_xo_gpll0_out_main_div2[] = {
+- "xo",
+- "gpll0_out_main_div2",
+-};
+-
+-static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
+- { P_XO, 0 },
+- { P_GPLL0_DIV2, 1 },
+-};
+-
+-static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+- "xo",
+- "bias_pll_cc_clk",
+- "gpll0",
+- "gpll4",
+- "nss_crypto_pll",
+- "ubi32_pll",
+-};
+-
+-static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
+- { P_XO, 0 },
+- { P_BIAS_PLL, 1 },
+- { P_GPLL0, 2 },
+- { P_GPLL4, 3 },
+- { P_NSS_CRYPTO_PLL, 4 },
+- { P_UBI32_PLL, 5 },
+-};
+-
+-static const char * const gcc_xo_gpll0_gpll4[] = {
+- "xo",
+- "gpll0",
+- "gpll4",
+-};
+-
+-static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+- { P_XO, 0 },
+- { P_GPLL0, 1 },
+- { P_GPLL4, 2 },
+-};
+-
+-static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
+- "xo",
+- "uniphy0_gcc_rx_clk",
+- "uniphy0_gcc_tx_clk",
+- "ubi32_pll",
+- "bias_pll_cc_clk",
+-};
+-
+-static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
+- { P_XO, 0 },
+- { P_UNIPHY0_RX, 1 },
+- { P_UNIPHY0_TX, 2 },
+- { P_UBI32_PLL, 5 },
+- { P_BIAS_PLL, 6 },
+-};
+-
+-static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
+- "xo",
+- "uniphy0_gcc_tx_clk",
+- "uniphy0_gcc_rx_clk",
+- "ubi32_pll",
+- "bias_pll_cc_clk",
+-};
+-
+-static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
+- { P_XO, 0 },
+- { P_UNIPHY0_TX, 1 },
+- { P_UNIPHY0_RX, 2 },
+- { P_UBI32_PLL, 5 },
+- { P_BIAS_PLL, 6 },
+-};
+-
+-static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+- "xo",
+- "uniphy0_gcc_rx_clk",
+- "uniphy0_gcc_tx_clk",
+- "uniphy1_gcc_rx_clk",
+- "uniphy1_gcc_tx_clk",
+- "ubi32_pll",
+- "bias_pll_cc_clk",
+-};
+-
+-static const struct parent_map
+-gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
+- { P_XO, 0 },
+- { P_UNIPHY0_RX, 1 },
+- { P_UNIPHY0_TX, 2 },
+- { P_UNIPHY1_RX, 3 },
+- { P_UNIPHY1_TX, 4 },
+- { P_UBI32_PLL, 5 },
+- { P_BIAS_PLL, 6 },
+-};
+-
+-static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
+- "xo",
+- "uniphy0_gcc_tx_clk",
+- "uniphy0_gcc_rx_clk",
+- "uniphy1_gcc_tx_clk",
+- "uniphy1_gcc_rx_clk",
+- "ubi32_pll",
+- "bias_pll_cc_clk",
+-};
+-
+-static const struct parent_map
+-gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
+- { P_XO, 0 },
+- { P_UNIPHY0_TX, 1 },
+- { P_UNIPHY0_RX, 2 },
+- { P_UNIPHY1_TX, 3 },
+- { P_UNIPHY1_RX, 4 },
+- { P_UBI32_PLL, 5 },
+- { P_BIAS_PLL, 6 },
+-};
+-
+-static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
+- "xo",
+- "uniphy2_gcc_rx_clk",
+- "uniphy2_gcc_tx_clk",
+- "ubi32_pll",
+- "bias_pll_cc_clk",
+-};
+-
+-static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
+- { P_XO, 0 },
+- { P_UNIPHY2_RX, 1 },
+- { P_UNIPHY2_TX, 2 },
+- { P_UBI32_PLL, 5 },
+- { P_BIAS_PLL, 6 },
+-};
+-
+-static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
+- "xo",
+- "uniphy2_gcc_tx_clk",
+- "uniphy2_gcc_rx_clk",
+- "ubi32_pll",
+- "bias_pll_cc_clk",
+-};
+-
+-static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
+- { P_XO, 0 },
+- { P_UNIPHY2_TX, 1 },
+- { P_UNIPHY2_RX, 2 },
+- { P_UBI32_PLL, 5 },
+- { P_BIAS_PLL, 6 },
+-};
+-
+-static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
+- "xo",
+- "gpll0",
+- "gpll6",
+- "gpll0_out_main_div2",
+- "sleep_clk",
+-};
+-
+-static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
+- { P_XO, 0 },
+- { P_GPLL0, 1 },
+- { P_GPLL6, 2 },
+- { P_GPLL0_DIV2, 4 },
+- { P_SLEEP_CLK, 6 },
+-};
+-
+ static struct clk_alpha_pll gpll0_main = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+@@ -400,8 +57,9 @@ static struct clk_alpha_pll gpll0_main =
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_main",
+- .parent_names = (const char *[]){
+- "xo"
++ .parent_data = &(const struct clk_parent_data){
++ .fw_name = "xo",
++ .name = "xo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+@@ -414,9 +72,8 @@ static struct clk_fixed_factor gpll0_out
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_out_main_div2",
+- .parent_names = (const char *[]){
+- "gpll0_main"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gpll0_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -429,9 +86,8 @@ static struct clk_alpha_pll_postdiv gpll
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+- .parent_names = (const char *[]){
+- "gpll0_main"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gpll0_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ },
+@@ -445,8 +101,9 @@ static struct clk_alpha_pll gpll2_main =
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll2_main",
+- .parent_names = (const char *[]){
+- "xo"
++ .parent_data = &(const struct clk_parent_data){
++ .fw_name = "xo",
++ .name = "xo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+@@ -461,9 +118,8 @@ static struct clk_alpha_pll_postdiv gpll
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll2",
+- .parent_names = (const char *[]){
+- "gpll2_main"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gpll2_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -478,8 +134,9 @@ static struct clk_alpha_pll gpll4_main =
+ .enable_mask = BIT(5),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_main",
+- .parent_names = (const char *[]){
+- "xo"
++ .parent_data = &(const struct clk_parent_data){
++ .fw_name = "xo",
++ .name = "xo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+@@ -494,9 +151,8 @@ static struct clk_alpha_pll_postdiv gpll
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll4",
+- .parent_names = (const char *[]){
+- "gpll4_main"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gpll4_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -512,8 +168,9 @@ static struct clk_alpha_pll gpll6_main =
+ .enable_mask = BIT(7),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll6_main",
+- .parent_names = (const char *[]){
+- "xo"
++ .parent_data = &(const struct clk_parent_data){
++ .fw_name = "xo",
++ .name = "xo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+@@ -528,9 +185,8 @@ static struct clk_alpha_pll_postdiv gpll
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll6",
+- .parent_names = (const char *[]){
+- "gpll6_main"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gpll6_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -542,9 +198,8 @@ static struct clk_fixed_factor gpll6_out
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll6_out_main_div2",
+- .parent_names = (const char *[]){
+- "gpll6_main"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gpll6_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -560,8 +215,9 @@ static struct clk_alpha_pll ubi32_pll_ma
+ .enable_mask = BIT(6),
+ .hw.init = &(struct clk_init_data){
+ .name = "ubi32_pll_main",
+- .parent_names = (const char *[]){
+- "xo"
++ .parent_data = &(const struct clk_parent_data){
++ .fw_name = "xo",
++ .name = "xo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_huayra_ops,
+@@ -575,9 +231,8 @@ static struct clk_alpha_pll_postdiv ubi3
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ubi32_pll",
+- .parent_names = (const char *[]){
+- "ubi32_pll_main"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &ubi32_pll_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -592,8 +247,9 @@ static struct clk_alpha_pll nss_crypto_p
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_crypto_pll_main",
+- .parent_names = (const char *[]){
+- "xo"
++ .parent_data = &(const struct clk_parent_data){
++ .fw_name = "xo",
++ .name = "xo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+@@ -607,9 +263,8 @@ static struct clk_alpha_pll_postdiv nss_
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_crypto_pll",
+- .parent_names = (const char *[]){
+- "nss_crypto_pll_main"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_crypto_pll_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -623,6 +278,18 @@ static const struct freq_tbl ftbl_pcnoc_
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &gpll0.clkr.hw},
++ { .hw = &gpll0_out_main_div2.hw},
++};
++
++static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
++ { P_XO, 0 },
++ { P_GPLL0, 1 },
++ { P_GPLL0_DIV2, 4 },
++};
++
+ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x27000,
+ .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
+@@ -630,8 +297,8 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcnoc_bfdcd_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+@@ -642,9 +309,8 @@ static struct clk_fixed_factor pcnoc_clk
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "pcnoc_clk_src",
+- .parent_names = (const char *[]){
+- "pcnoc_bfdcd_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_bfdcd_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -658,8 +324,9 @@ static struct clk_branch gcc_sleep_clk_s
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sleep_clk_src",
+- .parent_names = (const char *[]){
+- "sleep_clk"
++ .parent_data = &(const struct clk_parent_data){
++ .fw_name = "sleep_clk",
++ .name = "sleep_clk",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+@@ -682,8 +349,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -708,8 +375,8 @@ static struct clk_rcg2 blsp1_qup1_spi_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_spi_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -721,8 +388,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -735,8 +402,8 @@ static struct clk_rcg2 blsp1_qup2_spi_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_spi_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -748,8 +415,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -762,8 +429,8 @@ static struct clk_rcg2 blsp1_qup3_spi_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_spi_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -775,8 +442,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_i2c_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -789,8 +456,8 @@ static struct clk_rcg2 blsp1_qup4_spi_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_spi_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -802,8 +469,8 @@ static struct clk_rcg2 blsp1_qup5_i2c_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup5_i2c_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -816,8 +483,8 @@ static struct clk_rcg2 blsp1_qup5_spi_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup5_spi_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -829,8 +496,8 @@ static struct clk_rcg2 blsp1_qup6_i2c_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup6_i2c_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -843,8 +510,8 @@ static struct clk_rcg2 blsp1_qup6_spi_ap
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup6_spi_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -877,8 +544,8 @@ static struct clk_rcg2 blsp1_uart1_apps_
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart1_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -891,8 +558,8 @@ static struct clk_rcg2 blsp1_uart2_apps_
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart2_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -905,8 +572,8 @@ static struct clk_rcg2 blsp1_uart3_apps_
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart3_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -919,8 +586,8 @@ static struct clk_rcg2 blsp1_uart4_apps_
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart4_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -933,8 +600,8 @@ static struct clk_rcg2 blsp1_uart5_apps_
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart5_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -947,8 +614,8 @@ static struct clk_rcg2 blsp1_uart6_apps_
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart6_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -958,6 +625,11 @@ static const struct clk_parent_data gcc_
+ { .hw = &gpll0.clkr.hw },
+ };
+
++static const struct parent_map gcc_xo_gpll0_map[] = {
++ { P_XO, 0 },
++ { P_GPLL0, 1 },
++};
++
+ static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+@@ -972,7 +644,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie0_axi_clk_src",
+ .parent_data = gcc_xo_gpll0,
+- .num_parents = 2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -981,6 +653,18 @@ static const struct freq_tbl ftbl_pcie_a
+ F(19200000, P_XO, 1, 0, 0),
+ };
+
++static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &gpll0.clkr.hw },
++ { .fw_name = "sleep_clk", .name = "sleep_clk" },
++};
++
++static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
++ { P_XO, 0 },
++ { P_GPLL0, 2 },
++ { P_SLEEP_CLK, 6 },
++};
++
+ static struct clk_rcg2 pcie0_aux_clk_src = {
+ .cmd_rcgr = 0x75024,
+ .freq_tbl = ftbl_pcie_aux_clk_src,
+@@ -989,12 +673,22 @@ static struct clk_rcg2 pcie0_aux_clk_src
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie0_aux_clk_src",
+- .parent_names = gcc_xo_gpll0_sleep_clk,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_sleep_clk,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+
++static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
++ { .name = "pcie20_phy0_pipe_clk" },
++ { .fw_name = "xo", .name = "xo" },
++};
++
++static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
++ { P_PCIE20_PHY0_PIPE, 0 },
++ { P_XO, 2 },
++};
++
+ static struct clk_regmap_mux pcie0_pipe_clk_src = {
+ .reg = 0x7501c,
+ .shift = 8,
+@@ -1003,8 +697,8 @@ static struct clk_regmap_mux pcie0_pipe_
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie0_pipe_clk_src",
+- .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
+- .num_parents = 2,
++ .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
++ .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+@@ -1019,7 +713,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie1_axi_clk_src",
+ .parent_data = gcc_xo_gpll0,
+- .num_parents = 2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1032,12 +726,22 @@ static struct clk_rcg2 pcie1_aux_clk_src
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie1_aux_clk_src",
+- .parent_names = gcc_xo_gpll0_sleep_clk,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_sleep_clk,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+
++static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
++ { .name = "pcie20_phy1_pipe_clk" },
++ { .fw_name = "xo", .name = "xo" },
++};
++
++static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
++ { P_PCIE20_PHY1_PIPE, 0 },
++ { P_XO, 2 },
++};
++
+ static struct clk_regmap_mux pcie1_pipe_clk_src = {
+ .reg = 0x7601c,
+ .shift = 8,
+@@ -1046,8 +750,8 @@ static struct clk_regmap_mux pcie1_pipe_
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie1_pipe_clk_src",
+- .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
+- .num_parents = 2,
++ .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
++ .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+@@ -1066,6 +770,20 @@ static const struct freq_tbl ftbl_sdcc_a
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &gpll0.clkr.hw },
++ { .hw = &gpll2.clkr.hw },
++ { .hw = &gpll0_out_main_div2.hw },
++};
++
++static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
++ { P_XO, 0 },
++ { P_GPLL0, 1 },
++ { P_GPLL2, 2 },
++ { P_GPLL0_DIV2, 4 },
++};
++
+ static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x42004,
+ .freq_tbl = ftbl_sdcc_apps_clk_src,
+@@ -1074,8 +792,8 @@ static struct clk_rcg2 sdcc1_apps_clk_sr
+ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+- .num_parents = 4,
++ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
+ .ops = &clk_rcg2_floor_ops,
+ },
+ };
+@@ -1086,6 +804,20 @@ static const struct freq_tbl ftbl_sdcc_i
+ F(308570000, P_GPLL6, 3.5, 0, 0),
+ };
+
++static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &gpll0.clkr.hw },
++ { .hw = &gpll6.clkr.hw },
++ { .hw = &gpll0_out_main_div2.hw },
++};
++
++static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
++ { P_XO, 0 },
++ { P_GPLL0, 1 },
++ { P_GPLL6, 2 },
++ { P_GPLL0_DIV2, 4 },
++};
++
+ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x5d000,
+ .freq_tbl = ftbl_sdcc_ice_core_clk_src,
+@@ -1094,8 +826,8 @@ static struct clk_rcg2 sdcc1_ice_core_cl
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_ice_core_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
+- .num_parents = 4,
++ .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1108,8 +840,8 @@ static struct clk_rcg2 sdcc2_apps_clk_sr
+ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc2_apps_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+- .num_parents = 4,
++ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
+ .ops = &clk_rcg2_floor_ops,
+ },
+ };
+@@ -1121,6 +853,18 @@ static const struct freq_tbl ftbl_usb_ma
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &gpll0_out_main_div2.hw },
++ { .hw = &gpll0.clkr.hw },
++};
++
++static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
++ { P_XO, 0 },
++ { P_GPLL0_DIV2, 2 },
++ { P_GPLL0, 1 },
++};
++
+ static struct clk_rcg2 usb0_master_clk_src = {
+ .cmd_rcgr = 0x3e00c,
+ .freq_tbl = ftbl_usb_master_clk_src,
+@@ -1129,8 +873,8 @@ static struct clk_rcg2 usb0_master_clk_s
+ .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb0_master_clk_src",
+- .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1148,8 +892,8 @@ static struct clk_rcg2 usb0_aux_clk_src
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb0_aux_clk_src",
+- .parent_names = gcc_xo_gpll0_sleep_clk,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_sleep_clk,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1161,6 +905,20 @@ static const struct freq_tbl ftbl_usb_mo
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &gpll6.clkr.hw },
++ { .hw = &gpll0.clkr.hw },
++ { .hw = &gpll0_out_main_div2.hw },
++};
++
++static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
++ { P_XO, 0 },
++ { P_GPLL6, 1 },
++ { P_GPLL0, 3 },
++ { P_GPLL0_DIV2, 4 },
++};
++
+ static struct clk_rcg2 usb0_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x3e020,
+ .freq_tbl = ftbl_usb_mock_utmi_clk_src,
+@@ -1169,12 +927,22 @@ static struct clk_rcg2 usb0_mock_utmi_cl
+ .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb0_mock_utmi_clk_src",
+- .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
+- .num_parents = 4,
++ .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+
++static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
++ { .name = "usb3phy_0_cc_pipe_clk" },
++ { .fw_name = "xo", .name = "xo" },
++};
++
++static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
++ { P_USB3PHY_0_PIPE, 0 },
++ { P_XO, 2 },
++};
++
+ static struct clk_regmap_mux usb0_pipe_clk_src = {
+ .reg = 0x3e048,
+ .shift = 8,
+@@ -1183,8 +951,8 @@ static struct clk_regmap_mux usb0_pipe_c
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "usb0_pipe_clk_src",
+- .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
+- .num_parents = 2,
++ .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
++ .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+@@ -1199,8 +967,8 @@ static struct clk_rcg2 usb1_master_clk_s
+ .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb1_master_clk_src",
+- .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1213,8 +981,8 @@ static struct clk_rcg2 usb1_aux_clk_src
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb1_aux_clk_src",
+- .parent_names = gcc_xo_gpll0_sleep_clk,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_sleep_clk,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1227,12 +995,22 @@ static struct clk_rcg2 usb1_mock_utmi_cl
+ .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb1_mock_utmi_clk_src",
+- .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
+- .num_parents = 4,
++ .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+
++static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
++ { .name = "usb3phy_1_cc_pipe_clk" },
++ { .fw_name = "xo", .name = "xo" },
++};
++
++static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
++ { P_USB3PHY_1_PIPE, 0 },
++ { P_XO, 2 },
++};
++
+ static struct clk_regmap_mux usb1_pipe_clk_src = {
+ .reg = 0x3f048,
+ .shift = 8,
+@@ -1241,8 +1019,8 @@ static struct clk_regmap_mux usb1_pipe_c
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "usb1_pipe_clk_src",
+- .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
+- .num_parents = 2,
++ .parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
++ .num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+@@ -1256,8 +1034,9 @@ static struct clk_branch gcc_xo_clk_src
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_xo_clk_src",
+- .parent_names = (const char *[]){
+- "xo"
++ .parent_data = &(const struct clk_parent_data){
++ .fw_name = "xo",
++ .name = "xo",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+@@ -1271,9 +1050,8 @@ static struct clk_fixed_factor gcc_xo_di
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_xo_div4_clk_src",
+- .parent_names = (const char *[]){
+- "gcc_xo_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gcc_xo_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1291,6 +1069,20 @@ static const struct freq_tbl ftbl_system
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &gpll0.clkr.hw },
++ { .hw = &gpll6.clkr.hw },
++ { .hw = &gpll0_out_main_div2.hw },
++};
++
++static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
++ { P_XO, 0 },
++ { P_GPLL0, 1 },
++ { P_GPLL6, 2 },
++ { P_GPLL0_DIV2, 3 },
++};
++
+ static struct clk_rcg2 system_noc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x26004,
+ .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
+@@ -1298,8 +1090,8 @@ static struct clk_rcg2 system_noc_bfdcd_
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "system_noc_bfdcd_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
+- .num_parents = 4,
++ .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+@@ -1310,9 +1102,8 @@ static struct clk_fixed_factor system_no
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "system_noc_clk_src",
+- .parent_names = (const char *[]){
+- "system_noc_bfdcd_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &system_noc_bfdcd_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1333,7 +1124,7 @@ static struct clk_rcg2 nss_ce_clk_src =
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ce_clk_src",
+ .parent_data = gcc_xo_gpll0,
+- .num_parents = 2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1344,6 +1135,20 @@ static const struct freq_tbl ftbl_nss_no
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .name = "bias_pll_nss_noc_clk" },
++ { .hw = &gpll0.clkr.hw },
++ { .hw = &gpll2.clkr.hw },
++};
++
++static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
++ { P_XO, 0 },
++ { P_BIAS_PLL_NSS_NOC, 1 },
++ { P_GPLL0, 2 },
++ { P_GPLL2, 3 },
++};
++
+ static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x68088,
+ .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
+@@ -1351,8 +1156,8 @@ static struct clk_rcg2 nss_noc_bfdcd_clk
+ .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_noc_bfdcd_clk_src",
+- .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
+- .num_parents = 4,
++ .parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
++ .num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1362,9 +1167,8 @@ static struct clk_fixed_factor nss_noc_c
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_noc_clk_src",
+- .parent_names = (const char *[]){
+- "nss_noc_bfdcd_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_noc_bfdcd_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1377,6 +1181,18 @@ static const struct freq_tbl ftbl_nss_cr
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &nss_crypto_pll.clkr.hw },
++ { .hw = &gpll0.clkr.hw },
++};
++
++static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
++ { P_XO, 0 },
++ { P_NSS_CRYPTO_PLL, 1 },
++ { P_GPLL0, 2 },
++};
++
+ static struct clk_rcg2 nss_crypto_clk_src = {
+ .cmd_rcgr = 0x68144,
+ .freq_tbl = ftbl_nss_crypto_clk_src,
+@@ -1385,8 +1201,8 @@ static struct clk_rcg2 nss_crypto_clk_sr
+ .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_crypto_clk_src",
+- .parent_names = gcc_xo_nss_crypto_pll_gpll0,
+- .num_parents = 3,
++ .parent_data = gcc_xo_nss_crypto_pll_gpll0,
++ .num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1400,6 +1216,24 @@ static const struct freq_tbl ftbl_nss_ub
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &ubi32_pll.clkr.hw },
++ { .hw = &gpll0.clkr.hw },
++ { .hw = &gpll2.clkr.hw },
++ { .hw = &gpll4.clkr.hw },
++ { .hw = &gpll6.clkr.hw },
++};
++
++static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
++ { P_XO, 0 },
++ { P_UBI32_PLL, 1 },
++ { P_GPLL0, 2 },
++ { P_GPLL2, 3 },
++ { P_GPLL4, 4 },
++ { P_GPLL6, 5 },
++};
++
+ static struct clk_rcg2 nss_ubi0_clk_src = {
+ .cmd_rcgr = 0x68104,
+ .freq_tbl = ftbl_nss_ubi_clk_src,
+@@ -1407,8 +1241,8 @@ static struct clk_rcg2 nss_ubi0_clk_src
+ .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ubi0_clk_src",
+- .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
+- .num_parents = 6,
++ .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
++ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+@@ -1421,9 +1255,8 @@ static struct clk_regmap_div nss_ubi0_di
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_ubi0_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_ubi0_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ubi0_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1438,8 +1271,8 @@ static struct clk_rcg2 nss_ubi1_clk_src
+ .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ubi1_clk_src",
+- .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
+- .num_parents = 6,
++ .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
++ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+@@ -1452,9 +1285,8 @@ static struct clk_regmap_div nss_ubi1_di
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_ubi1_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_ubi1_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ubi1_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1468,6 +1300,16 @@ static const struct freq_tbl ftbl_ubi_mp
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &gpll0_out_main_div2.hw },
++};
++
++static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
++ { P_XO, 0 },
++ { P_GPLL0_DIV2, 1 },
++};
++
+ static struct clk_rcg2 ubi_mpt_clk_src = {
+ .cmd_rcgr = 0x68090,
+ .freq_tbl = ftbl_ubi_mpt_clk_src,
+@@ -1475,8 +1317,8 @@ static struct clk_rcg2 ubi_mpt_clk_src =
+ .parent_map = gcc_xo_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ubi_mpt_clk_src",
+- .parent_names = gcc_xo_gpll0_out_main_div2,
+- .num_parents = 2,
++ .parent_data = gcc_xo_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1487,6 +1329,18 @@ static const struct freq_tbl ftbl_nss_im
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &gpll0.clkr.hw },
++ { .hw = &gpll4.clkr.hw },
++};
++
++static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
++ { P_XO, 0 },
++ { P_GPLL0, 1 },
++ { P_GPLL4, 2 },
++};
++
+ static struct clk_rcg2 nss_imem_clk_src = {
+ .cmd_rcgr = 0x68158,
+ .freq_tbl = ftbl_nss_imem_clk_src,
+@@ -1494,8 +1348,8 @@ static struct clk_rcg2 nss_imem_clk_src
+ .parent_map = gcc_xo_gpll0_gpll4_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_imem_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll4,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll4,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1506,6 +1360,24 @@ static const struct freq_tbl ftbl_nss_pp
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .name = "bias_pll_cc_clk" },
++ { .hw = &gpll0.clkr.hw },
++ { .hw = &gpll4.clkr.hw },
++ { .hw = &nss_crypto_pll.clkr.hw },
++ { .hw = &ubi32_pll.clkr.hw },
++};
++
++static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
++ { P_XO, 0 },
++ { P_BIAS_PLL, 1 },
++ { P_GPLL0, 2 },
++ { P_GPLL4, 3 },
++ { P_NSS_CRYPTO_PLL, 4 },
++ { P_UBI32_PLL, 5 },
++};
++
+ static struct clk_rcg2 nss_ppe_clk_src = {
+ .cmd_rcgr = 0x68080,
+ .freq_tbl = ftbl_nss_ppe_clk_src,
+@@ -1513,8 +1385,8 @@ static struct clk_rcg2 nss_ppe_clk_src =
+ .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ppe_clk_src",
+- .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
+- .num_parents = 6,
++ .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
++ .num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1524,9 +1396,8 @@ static struct clk_fixed_factor nss_ppe_c
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_ppe_cdiv_clk_src",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1540,6 +1411,22 @@ static const struct freq_tbl ftbl_nss_po
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .name = "uniphy0_gcc_rx_clk" },
++ { .name = "uniphy0_gcc_tx_clk" },
++ { .hw = &ubi32_pll.clkr.hw },
++ { .name = "bias_pll_cc_clk" },
++};
++
++static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
++ { P_XO, 0 },
++ { P_UNIPHY0_RX, 1 },
++ { P_UNIPHY0_TX, 2 },
++ { P_UBI32_PLL, 5 },
++ { P_BIAS_PLL, 6 },
++};
++
+ static struct clk_rcg2 nss_port1_rx_clk_src = {
+ .cmd_rcgr = 0x68020,
+ .freq_tbl = ftbl_nss_port1_rx_clk_src,
+@@ -1547,8 +1434,8 @@ static struct clk_rcg2 nss_port1_rx_clk_
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port1_rx_clk_src",
+- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+- .num_parents = 5,
++ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1560,9 +1447,8 @@ static struct clk_regmap_div nss_port1_r
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port1_rx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port1_rx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port1_rx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1577,6 +1463,22 @@ static const struct freq_tbl ftbl_nss_po
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .name = "uniphy0_gcc_tx_clk" },
++ { .name = "uniphy0_gcc_rx_clk" },
++ { .hw = &ubi32_pll.clkr.hw },
++ { .name = "bias_pll_cc_clk" },
++};
++
++static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
++ { P_XO, 0 },
++ { P_UNIPHY0_TX, 1 },
++ { P_UNIPHY0_RX, 2 },
++ { P_UBI32_PLL, 5 },
++ { P_BIAS_PLL, 6 },
++};
++
+ static struct clk_rcg2 nss_port1_tx_clk_src = {
+ .cmd_rcgr = 0x68028,
+ .freq_tbl = ftbl_nss_port1_tx_clk_src,
+@@ -1584,8 +1486,8 @@ static struct clk_rcg2 nss_port1_tx_clk_
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port1_tx_clk_src",
+- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+- .num_parents = 5,
++ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1597,9 +1499,8 @@ static struct clk_regmap_div nss_port1_t
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port1_tx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port1_tx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port1_tx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1614,8 +1515,8 @@ static struct clk_rcg2 nss_port2_rx_clk_
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port2_rx_clk_src",
+- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+- .num_parents = 5,
++ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1627,9 +1528,8 @@ static struct clk_regmap_div nss_port2_r
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port2_rx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port2_rx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port2_rx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1644,8 +1544,8 @@ static struct clk_rcg2 nss_port2_tx_clk_
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port2_tx_clk_src",
+- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+- .num_parents = 5,
++ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1657,9 +1557,8 @@ static struct clk_regmap_div nss_port2_t
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port2_tx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port2_tx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port2_tx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1674,8 +1573,8 @@ static struct clk_rcg2 nss_port3_rx_clk_
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port3_rx_clk_src",
+- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+- .num_parents = 5,
++ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1687,9 +1586,8 @@ static struct clk_regmap_div nss_port3_r
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port3_rx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port3_rx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port3_rx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1704,8 +1602,8 @@ static struct clk_rcg2 nss_port3_tx_clk_
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port3_tx_clk_src",
+- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+- .num_parents = 5,
++ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1717,9 +1615,8 @@ static struct clk_regmap_div nss_port3_t
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port3_tx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port3_tx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port3_tx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1734,8 +1631,8 @@ static struct clk_rcg2 nss_port4_rx_clk_
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port4_rx_clk_src",
+- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+- .num_parents = 5,
++ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1747,9 +1644,8 @@ static struct clk_regmap_div nss_port4_r
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port4_rx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port4_rx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port4_rx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1764,8 +1660,8 @@ static struct clk_rcg2 nss_port4_tx_clk_
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port4_tx_clk_src",
+- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+- .num_parents = 5,
++ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1777,9 +1673,8 @@ static struct clk_regmap_div nss_port4_t
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port4_tx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port4_tx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port4_tx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1799,6 +1694,27 @@ static const struct freq_tbl ftbl_nss_po
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .name = "uniphy0_gcc_rx_clk" },
++ { .name = "uniphy0_gcc_tx_clk" },
++ { .name = "uniphy1_gcc_rx_clk" },
++ { .name = "uniphy1_gcc_tx_clk" },
++ { .hw = &ubi32_pll.clkr.hw },
++ { .name = "bias_pll_cc_clk" },
++};
++
++static const struct parent_map
++gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
++ { P_XO, 0 },
++ { P_UNIPHY0_RX, 1 },
++ { P_UNIPHY0_TX, 2 },
++ { P_UNIPHY1_RX, 3 },
++ { P_UNIPHY1_TX, 4 },
++ { P_UBI32_PLL, 5 },
++ { P_BIAS_PLL, 6 },
++};
++
+ static struct clk_rcg2 nss_port5_rx_clk_src = {
+ .cmd_rcgr = 0x68060,
+ .freq_tbl = ftbl_nss_port5_rx_clk_src,
+@@ -1806,8 +1722,8 @@ static struct clk_rcg2 nss_port5_rx_clk_
+ .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port5_rx_clk_src",
+- .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
+- .num_parents = 7,
++ .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1819,9 +1735,8 @@ static struct clk_regmap_div nss_port5_r
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port5_rx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port5_rx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port5_rx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1841,6 +1756,27 @@ static const struct freq_tbl ftbl_nss_po
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .name = "uniphy0_gcc_tx_clk" },
++ { .name = "uniphy0_gcc_rx_clk" },
++ { .name = "uniphy1_gcc_tx_clk" },
++ { .name = "uniphy1_gcc_rx_clk" },
++ { .hw = &ubi32_pll.clkr.hw },
++ { .name = "bias_pll_cc_clk" },
++};
++
++static const struct parent_map
++gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
++ { P_XO, 0 },
++ { P_UNIPHY0_TX, 1 },
++ { P_UNIPHY0_RX, 2 },
++ { P_UNIPHY1_TX, 3 },
++ { P_UNIPHY1_RX, 4 },
++ { P_UBI32_PLL, 5 },
++ { P_BIAS_PLL, 6 },
++};
++
+ static struct clk_rcg2 nss_port5_tx_clk_src = {
+ .cmd_rcgr = 0x68068,
+ .freq_tbl = ftbl_nss_port5_tx_clk_src,
+@@ -1848,8 +1784,8 @@ static struct clk_rcg2 nss_port5_tx_clk_
+ .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port5_tx_clk_src",
+- .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
+- .num_parents = 7,
++ .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1861,9 +1797,8 @@ static struct clk_regmap_div nss_port5_t
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port5_tx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port5_tx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port5_tx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1883,6 +1818,22 @@ static const struct freq_tbl ftbl_nss_po
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .name = "uniphy2_gcc_rx_clk" },
++ { .name = "uniphy2_gcc_tx_clk" },
++ { .hw = &ubi32_pll.clkr.hw },
++ { .name = "bias_pll_cc_clk" },
++};
++
++static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
++ { P_XO, 0 },
++ { P_UNIPHY2_RX, 1 },
++ { P_UNIPHY2_TX, 2 },
++ { P_UBI32_PLL, 5 },
++ { P_BIAS_PLL, 6 },
++};
++
+ static struct clk_rcg2 nss_port6_rx_clk_src = {
+ .cmd_rcgr = 0x68070,
+ .freq_tbl = ftbl_nss_port6_rx_clk_src,
+@@ -1890,8 +1841,8 @@ static struct clk_rcg2 nss_port6_rx_clk_
+ .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port6_rx_clk_src",
+- .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
+- .num_parents = 5,
++ .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1903,9 +1854,8 @@ static struct clk_regmap_div nss_port6_r
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port6_rx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port6_rx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port6_rx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1925,6 +1875,22 @@ static const struct freq_tbl ftbl_nss_po
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .name = "uniphy2_gcc_tx_clk" },
++ { .name = "uniphy2_gcc_rx_clk" },
++ { .hw = &ubi32_pll.clkr.hw },
++ { .name = "bias_pll_cc_clk" },
++};
++
++static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
++ { P_XO, 0 },
++ { P_UNIPHY2_TX, 1 },
++ { P_UNIPHY2_RX, 2 },
++ { P_UBI32_PLL, 5 },
++ { P_BIAS_PLL, 6 },
++};
++
+ static struct clk_rcg2 nss_port6_tx_clk_src = {
+ .cmd_rcgr = 0x68078,
+ .freq_tbl = ftbl_nss_port6_tx_clk_src,
+@@ -1932,8 +1898,8 @@ static struct clk_rcg2 nss_port6_tx_clk_
+ .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port6_tx_clk_src",
+- .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
+- .num_parents = 5,
++ .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
++ .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1945,9 +1911,8 @@ static struct clk_regmap_div nss_port6_t
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port6_tx_div_clk_src",
+- .parent_names = (const char *[]){
+- "nss_port6_tx_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port6_tx_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+@@ -1970,8 +1935,8 @@ static struct clk_rcg2 crypto_clk_src =
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "crypto_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+- .num_parents = 3,
++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -1981,6 +1946,22 @@ static struct freq_tbl ftbl_gp_clk_src[]
+ { }
+ };
+
++static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
++ { .fw_name = "xo", .name = "xo" },
++ { .hw = &gpll0.clkr.hw },
++ { .hw = &gpll6.clkr.hw },
++ { .hw = &gpll0_out_main_div2.hw },
++ { .fw_name = "sleep_clk", .name = "sleep_clk" },
++};
++
++static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
++ { P_XO, 0 },
++ { P_GPLL0, 1 },
++ { P_GPLL6, 2 },
++ { P_GPLL0_DIV2, 4 },
++ { P_SLEEP_CLK, 6 },
++};
++
+ static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x08004,
+ .freq_tbl = ftbl_gp_clk_src,
+@@ -1989,8 +1970,8 @@ static struct clk_rcg2 gp1_clk_src = {
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp1_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+- .num_parents = 5,
++ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -2003,8 +1984,8 @@ static struct clk_rcg2 gp2_clk_src = {
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp2_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+- .num_parents = 5,
++ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -2017,8 +1998,8 @@ static struct clk_rcg2 gp3_clk_src = {
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp3_clk_src",
+- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+- .num_parents = 5,
++ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+ };
+@@ -2030,9 +2011,8 @@ static struct clk_branch gcc_blsp1_ahb_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2047,9 +2027,8 @@ static struct clk_branch gcc_blsp1_qup1_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup1_i2c_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2064,9 +2043,8 @@ static struct clk_branch gcc_blsp1_qup1_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup1_spi_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2081,9 +2059,8 @@ static struct clk_branch gcc_blsp1_qup2_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup2_i2c_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2098,9 +2075,8 @@ static struct clk_branch gcc_blsp1_qup2_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup2_spi_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2115,9 +2091,8 @@ static struct clk_branch gcc_blsp1_qup3_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup3_i2c_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2132,9 +2107,8 @@ static struct clk_branch gcc_blsp1_qup3_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup3_spi_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2149,9 +2123,8 @@ static struct clk_branch gcc_blsp1_qup4_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup4_i2c_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2166,9 +2139,8 @@ static struct clk_branch gcc_blsp1_qup4_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_spi_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup4_spi_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2183,9 +2155,8 @@ static struct clk_branch gcc_blsp1_qup5_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup5_i2c_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup5_i2c_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2200,9 +2171,8 @@ static struct clk_branch gcc_blsp1_qup5_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup5_spi_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup5_spi_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2217,9 +2187,8 @@ static struct clk_branch gcc_blsp1_qup6_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup6_i2c_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup6_i2c_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2234,9 +2203,8 @@ static struct clk_branch gcc_blsp1_qup6_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup6_spi_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_qup6_spi_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2251,9 +2219,8 @@ static struct clk_branch gcc_blsp1_uart1
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart1_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_uart1_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_uart1_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2268,9 +2235,8 @@ static struct clk_branch gcc_blsp1_uart2
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart2_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_uart2_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_uart2_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2285,9 +2251,8 @@ static struct clk_branch gcc_blsp1_uart3
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart3_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_uart3_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_uart3_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2302,9 +2267,8 @@ static struct clk_branch gcc_blsp1_uart4
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart4_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_uart4_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_uart4_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2319,9 +2283,8 @@ static struct clk_branch gcc_blsp1_uart5
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart5_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_uart5_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_uart5_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2336,9 +2299,8 @@ static struct clk_branch gcc_blsp1_uart6
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart6_apps_clk",
+- .parent_names = (const char *[]){
+- "blsp1_uart6_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &blsp1_uart6_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2354,9 +2316,8 @@ static struct clk_branch gcc_prng_ahb_cl
+ .enable_mask = BIT(8),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2371,9 +2332,8 @@ static struct clk_branch gcc_qpic_ahb_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qpic_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2388,9 +2348,8 @@ static struct clk_branch gcc_qpic_clk =
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qpic_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2405,9 +2364,8 @@ static struct clk_branch gcc_pcie0_ahb_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2422,9 +2380,8 @@ static struct clk_branch gcc_pcie0_aux_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_aux_clk",
+- .parent_names = (const char *[]){
+- "pcie0_aux_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcie0_aux_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2439,9 +2396,8 @@ static struct clk_branch gcc_pcie0_axi_m
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_axi_m_clk",
+- .parent_names = (const char *[]){
+- "pcie0_axi_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcie0_axi_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2456,9 +2412,8 @@ static struct clk_branch gcc_pcie0_axi_s
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_axi_s_clk",
+- .parent_names = (const char *[]){
+- "pcie0_axi_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcie0_axi_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2474,9 +2429,8 @@ static struct clk_branch gcc_pcie0_pipe_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_pipe_clk",
+- .parent_names = (const char *[]){
+- "pcie0_pipe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcie0_pipe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2491,9 +2445,8 @@ static struct clk_branch gcc_sys_noc_pci
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_pcie0_axi_clk",
+- .parent_names = (const char *[]){
+- "pcie0_axi_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcie0_axi_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2508,9 +2461,8 @@ static struct clk_branch gcc_pcie1_ahb_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2525,9 +2477,8 @@ static struct clk_branch gcc_pcie1_aux_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_aux_clk",
+- .parent_names = (const char *[]){
+- "pcie1_aux_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcie1_aux_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2542,9 +2493,8 @@ static struct clk_branch gcc_pcie1_axi_m
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_axi_m_clk",
+- .parent_names = (const char *[]){
+- "pcie1_axi_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcie1_axi_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2559,9 +2509,8 @@ static struct clk_branch gcc_pcie1_axi_s
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_axi_s_clk",
+- .parent_names = (const char *[]){
+- "pcie1_axi_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcie1_axi_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2577,9 +2526,8 @@ static struct clk_branch gcc_pcie1_pipe_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_pipe_clk",
+- .parent_names = (const char *[]){
+- "pcie1_pipe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcie1_pipe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2594,9 +2542,8 @@ static struct clk_branch gcc_sys_noc_pci
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_pcie1_axi_clk",
+- .parent_names = (const char *[]){
+- "pcie1_axi_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcie1_axi_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2611,9 +2558,8 @@ static struct clk_branch gcc_usb0_aux_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_aux_clk",
+- .parent_names = (const char *[]){
+- "usb0_aux_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &usb0_aux_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2628,9 +2574,8 @@ static struct clk_branch gcc_sys_noc_usb
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_usb0_axi_clk",
+- .parent_names = (const char *[]){
+- "usb0_master_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &usb0_master_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2645,9 +2590,8 @@ static struct clk_branch gcc_usb0_master
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_master_clk",
+- .parent_names = (const char *[]){
+- "usb0_master_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &usb0_master_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2662,9 +2606,8 @@ static struct clk_branch gcc_usb0_mock_u
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_mock_utmi_clk",
+- .parent_names = (const char *[]){
+- "usb0_mock_utmi_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &usb0_mock_utmi_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2679,9 +2622,8 @@ static struct clk_branch gcc_usb0_phy_cf
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_phy_cfg_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2697,9 +2639,8 @@ static struct clk_branch gcc_usb0_pipe_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_pipe_clk",
+- .parent_names = (const char *[]){
+- "usb0_pipe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &usb0_pipe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2714,9 +2655,8 @@ static struct clk_branch gcc_usb0_sleep_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_sleep_clk",
+- .parent_names = (const char *[]){
+- "gcc_sleep_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gcc_sleep_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2731,9 +2671,8 @@ static struct clk_branch gcc_usb1_aux_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_aux_clk",
+- .parent_names = (const char *[]){
+- "usb1_aux_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &usb1_aux_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2748,9 +2687,8 @@ static struct clk_branch gcc_sys_noc_usb
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_usb1_axi_clk",
+- .parent_names = (const char *[]){
+- "usb1_master_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &usb1_master_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2765,9 +2703,8 @@ static struct clk_branch gcc_usb1_master
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_master_clk",
+- .parent_names = (const char *[]){
+- "usb1_master_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &usb1_master_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2782,9 +2719,8 @@ static struct clk_branch gcc_usb1_mock_u
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_mock_utmi_clk",
+- .parent_names = (const char *[]){
+- "usb1_mock_utmi_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &usb1_mock_utmi_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2799,9 +2735,8 @@ static struct clk_branch gcc_usb1_phy_cf
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_phy_cfg_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2817,9 +2752,8 @@ static struct clk_branch gcc_usb1_pipe_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_pipe_clk",
+- .parent_names = (const char *[]){
+- "usb1_pipe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &usb1_pipe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2834,9 +2768,8 @@ static struct clk_branch gcc_usb1_sleep_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_sleep_clk",
+- .parent_names = (const char *[]){
+- "gcc_sleep_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gcc_sleep_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2851,9 +2784,8 @@ static struct clk_branch gcc_sdcc1_ahb_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2868,9 +2800,8 @@ static struct clk_branch gcc_sdcc1_apps_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk",
+- .parent_names = (const char *[]){
+- "sdcc1_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &sdcc1_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2885,9 +2816,8 @@ static struct clk_branch gcc_sdcc1_ice_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ice_core_clk",
+- .parent_names = (const char *[]){
+- "sdcc1_ice_core_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &sdcc1_ice_core_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2902,9 +2832,8 @@ static struct clk_branch gcc_sdcc2_ahb_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2919,9 +2848,8 @@ static struct clk_branch gcc_sdcc2_apps_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_apps_clk",
+- .parent_names = (const char *[]){
+- "sdcc2_apps_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &sdcc2_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2936,9 +2864,8 @@ static struct clk_branch gcc_mem_noc_nss
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mem_noc_nss_axi_clk",
+- .parent_names = (const char *[]){
+- "nss_noc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_noc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2953,9 +2880,8 @@ static struct clk_branch gcc_nss_ce_apb_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ce_apb_clk",
+- .parent_names = (const char *[]){
+- "nss_ce_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ce_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2970,9 +2896,8 @@ static struct clk_branch gcc_nss_ce_axi_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ce_axi_clk",
+- .parent_names = (const char *[]){
+- "nss_ce_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ce_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -2987,9 +2912,8 @@ static struct clk_branch gcc_nss_cfg_clk
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_cfg_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3004,9 +2928,8 @@ static struct clk_branch gcc_nss_crypto_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_crypto_clk",
+- .parent_names = (const char *[]){
+- "nss_crypto_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_crypto_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3021,9 +2944,8 @@ static struct clk_branch gcc_nss_csr_clk
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_csr_clk",
+- .parent_names = (const char *[]){
+- "nss_ce_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ce_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3038,9 +2960,8 @@ static struct clk_branch gcc_nss_edma_cf
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_edma_cfg_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3055,9 +2976,8 @@ static struct clk_branch gcc_nss_edma_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_edma_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3072,9 +2992,8 @@ static struct clk_branch gcc_nss_imem_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_imem_clk",
+- .parent_names = (const char *[]){
+- "nss_imem_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_imem_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3089,9 +3008,8 @@ static struct clk_branch gcc_nss_noc_clk
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_noc_clk",
+- .parent_names = (const char *[]){
+- "nss_noc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_noc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3106,9 +3024,8 @@ static struct clk_branch gcc_nss_ppe_btq
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_btq_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3123,9 +3040,8 @@ static struct clk_branch gcc_nss_ppe_cfg
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_cfg_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3140,9 +3056,8 @@ static struct clk_branch gcc_nss_ppe_clk
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3157,9 +3072,8 @@ static struct clk_branch gcc_nss_ppe_ipe
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_ipe_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3174,9 +3088,8 @@ static struct clk_branch gcc_nss_ptp_ref
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ptp_ref_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_cdiv_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_cdiv_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3192,9 +3105,8 @@ static struct clk_branch gcc_crypto_ppe_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_ppe_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3209,9 +3121,8 @@ static struct clk_branch gcc_nssnoc_ce_a
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ce_apb_clk",
+- .parent_names = (const char *[]){
+- "nss_ce_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ce_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3226,9 +3137,8 @@ static struct clk_branch gcc_nssnoc_ce_a
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ce_axi_clk",
+- .parent_names = (const char *[]){
+- "nss_ce_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ce_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3243,9 +3153,8 @@ static struct clk_branch gcc_nssnoc_cryp
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_crypto_clk",
+- .parent_names = (const char *[]){
+- "nss_crypto_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_crypto_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3260,9 +3169,8 @@ static struct clk_branch gcc_nssnoc_ppe_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ppe_cfg_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3277,9 +3185,8 @@ static struct clk_branch gcc_nssnoc_ppe_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ppe_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3294,9 +3201,8 @@ static struct clk_branch gcc_nssnoc_qosg
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_qosgen_ref_clk",
+- .parent_names = (const char *[]){
+- "gcc_xo_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gcc_xo_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3311,9 +3217,8 @@ static struct clk_branch gcc_nssnoc_snoc
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_snoc_clk",
+- .parent_names = (const char *[]){
+- "system_noc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &system_noc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3328,9 +3233,8 @@ static struct clk_branch gcc_nssnoc_time
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_timeout_ref_clk",
+- .parent_names = (const char *[]){
+- "gcc_xo_div4_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gcc_xo_div4_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3345,9 +3249,8 @@ static struct clk_branch gcc_nssnoc_ubi0
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ubi0_ahb_clk",
+- .parent_names = (const char *[]){
+- "nss_ce_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ce_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3362,9 +3265,8 @@ static struct clk_branch gcc_nssnoc_ubi1
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ubi1_ahb_clk",
+- .parent_names = (const char *[]){
+- "nss_ce_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ce_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3380,9 +3282,8 @@ static struct clk_branch gcc_ubi0_ahb_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_ahb_clk",
+- .parent_names = (const char *[]){
+- "nss_ce_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ce_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3398,9 +3299,8 @@ static struct clk_branch gcc_ubi0_axi_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_axi_clk",
+- .parent_names = (const char *[]){
+- "nss_noc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_noc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3416,9 +3316,8 @@ static struct clk_branch gcc_ubi0_nc_axi
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_nc_axi_clk",
+- .parent_names = (const char *[]){
+- "nss_noc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_noc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3434,9 +3333,8 @@ static struct clk_branch gcc_ubi0_core_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_core_clk",
+- .parent_names = (const char *[]){
+- "nss_ubi0_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ubi0_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3452,9 +3350,8 @@ static struct clk_branch gcc_ubi0_mpt_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_mpt_clk",
+- .parent_names = (const char *[]){
+- "ubi_mpt_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &ubi_mpt_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3470,9 +3367,8 @@ static struct clk_branch gcc_ubi1_ahb_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_ahb_clk",
+- .parent_names = (const char *[]){
+- "nss_ce_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ce_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3488,9 +3384,8 @@ static struct clk_branch gcc_ubi1_axi_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_axi_clk",
+- .parent_names = (const char *[]){
+- "nss_noc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_noc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3506,9 +3401,8 @@ static struct clk_branch gcc_ubi1_nc_axi
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_nc_axi_clk",
+- .parent_names = (const char *[]){
+- "nss_noc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_noc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3524,9 +3418,8 @@ static struct clk_branch gcc_ubi1_core_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_core_clk",
+- .parent_names = (const char *[]){
+- "nss_ubi1_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ubi1_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3542,9 +3435,8 @@ static struct clk_branch gcc_ubi1_mpt_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_mpt_clk",
+- .parent_names = (const char *[]){
+- "ubi_mpt_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &ubi_mpt_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3559,9 +3451,8 @@ static struct clk_branch gcc_cmn_12gpll_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cmn_12gpll_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3576,9 +3467,8 @@ static struct clk_branch gcc_cmn_12gpll_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cmn_12gpll_sys_clk",
+- .parent_names = (const char *[]){
+- "gcc_xo_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gcc_xo_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3593,9 +3483,8 @@ static struct clk_branch gcc_mdio_ahb_cl
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mdio_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3610,9 +3499,8 @@ static struct clk_branch gcc_uniphy0_ahb
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3627,9 +3515,8 @@ static struct clk_branch gcc_uniphy0_sys
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_sys_clk",
+- .parent_names = (const char *[]){
+- "gcc_xo_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gcc_xo_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3644,9 +3531,8 @@ static struct clk_branch gcc_uniphy1_ahb
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3661,9 +3547,8 @@ static struct clk_branch gcc_uniphy1_sys
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_sys_clk",
+- .parent_names = (const char *[]){
+- "gcc_xo_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gcc_xo_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3678,9 +3563,8 @@ static struct clk_branch gcc_uniphy2_ahb
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3695,9 +3579,8 @@ static struct clk_branch gcc_uniphy2_sys
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_sys_clk",
+- .parent_names = (const char *[]){
+- "gcc_xo_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gcc_xo_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3712,9 +3595,8 @@ static struct clk_branch gcc_nss_port1_r
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port1_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port1_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port1_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3729,9 +3611,8 @@ static struct clk_branch gcc_nss_port1_t
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port1_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port1_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port1_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3746,9 +3627,8 @@ static struct clk_branch gcc_nss_port2_r
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port2_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port2_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port2_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3763,9 +3643,8 @@ static struct clk_branch gcc_nss_port2_t
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port2_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port2_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port2_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3780,9 +3659,8 @@ static struct clk_branch gcc_nss_port3_r
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port3_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port3_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port3_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3797,9 +3675,8 @@ static struct clk_branch gcc_nss_port3_t
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port3_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port3_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port3_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3814,9 +3691,8 @@ static struct clk_branch gcc_nss_port4_r
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port4_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port4_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port4_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3831,9 +3707,8 @@ static struct clk_branch gcc_nss_port4_t
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port4_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port4_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port4_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3848,9 +3723,8 @@ static struct clk_branch gcc_nss_port5_r
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port5_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port5_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port5_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3865,9 +3739,8 @@ static struct clk_branch gcc_nss_port5_t
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port5_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port5_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port5_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3882,9 +3755,8 @@ static struct clk_branch gcc_nss_port6_r
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port6_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port6_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port6_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3899,9 +3771,8 @@ static struct clk_branch gcc_nss_port6_t
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port6_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port6_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port6_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3916,9 +3787,8 @@ static struct clk_branch gcc_port1_mac_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port1_mac_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3933,9 +3803,8 @@ static struct clk_branch gcc_port2_mac_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port2_mac_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3950,9 +3819,8 @@ static struct clk_branch gcc_port3_mac_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port3_mac_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3967,9 +3835,8 @@ static struct clk_branch gcc_port4_mac_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port4_mac_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -3984,9 +3851,8 @@ static struct clk_branch gcc_port5_mac_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port5_mac_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4001,9 +3867,8 @@ static struct clk_branch gcc_port6_mac_c
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port6_mac_clk",
+- .parent_names = (const char *[]){
+- "nss_ppe_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_ppe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4018,9 +3883,8 @@ static struct clk_branch gcc_uniphy0_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port1_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port1_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port1_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4035,9 +3899,8 @@ static struct clk_branch gcc_uniphy0_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port1_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port1_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port1_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4052,9 +3915,8 @@ static struct clk_branch gcc_uniphy0_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port2_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port2_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port2_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4069,9 +3931,8 @@ static struct clk_branch gcc_uniphy0_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port2_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port2_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port2_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4086,9 +3947,8 @@ static struct clk_branch gcc_uniphy0_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port3_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port3_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port3_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4103,9 +3963,8 @@ static struct clk_branch gcc_uniphy0_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port3_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port3_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port3_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4120,9 +3979,8 @@ static struct clk_branch gcc_uniphy0_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port4_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port4_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port4_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4137,9 +3995,8 @@ static struct clk_branch gcc_uniphy0_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port4_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port4_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port4_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4154,9 +4011,8 @@ static struct clk_branch gcc_uniphy0_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port5_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port5_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port5_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4171,9 +4027,8 @@ static struct clk_branch gcc_uniphy0_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port5_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port5_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port5_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4188,9 +4043,8 @@ static struct clk_branch gcc_uniphy1_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_port5_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port5_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port5_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4205,9 +4059,8 @@ static struct clk_branch gcc_uniphy1_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_port5_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port5_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port5_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4222,9 +4075,8 @@ static struct clk_branch gcc_uniphy2_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_port6_rx_clk",
+- .parent_names = (const char *[]){
+- "nss_port6_rx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port6_rx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4239,9 +4091,8 @@ static struct clk_branch gcc_uniphy2_por
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_port6_tx_clk",
+- .parent_names = (const char *[]){
+- "nss_port6_tx_div_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &nss_port6_tx_div_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4257,9 +4108,8 @@ static struct clk_branch gcc_crypto_ahb_
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_ahb_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4275,9 +4125,8 @@ static struct clk_branch gcc_crypto_axi_
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_axi_clk",
+- .parent_names = (const char *[]){
+- "pcnoc_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &pcnoc_clk_src.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4293,9 +4142,8 @@ static struct clk_branch gcc_crypto_clk
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_clk",
+- .parent_names = (const char *[]){
+- "crypto_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &crypto_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4310,9 +4158,8 @@ static struct clk_branch gcc_gp1_clk = {
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp1_clk",
+- .parent_names = (const char *[]){
+- "gp1_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gp1_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4327,9 +4174,8 @@ static struct clk_branch gcc_gp2_clk = {
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp2_clk",
+- .parent_names = (const char *[]){
+- "gp2_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gp2_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4344,9 +4190,8 @@ static struct clk_branch gcc_gp3_clk = {
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp3_clk",
+- .parent_names = (const char *[]){
+- "gp3_clk_src"
+- },
++ .parent_hws = (const struct clk_hw *[]){
++ &gp3_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+@@ -4368,7 +4213,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie0_rchng_clk_src",
+ .parent_data = gcc_xo_gpll0,
+- .num_parents = 2,
++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+ };
--- /dev/null
+From 813ba3e427671ba3ff35c825087b03f0ad91cf02 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 7 Nov 2022 14:28:59 +0100
+Subject: [PATCH] clk: qcom: reset: support resetting multiple bits
+
+This patch adds the support for giving the complete bitmask
+in reset structure and reset operation will use this bitmask
+for all reset operations.
+
+Currently, reset structure only takes a single bit for each reset
+and then calculates the bitmask by using the BIT() macro.
+
+However, this is not sufficient anymore for newer SoC-s like IPQ8074,
+IPQ6018 and more, since their networking resets require multiple bits
+to be asserted in order to properly reset the HW block completely.
+
+So, in order to allow asserting multiple bits add "bitmask" field to
+qcom_reset_map, and then use that bitmask value if its populated in the
+driver, if its not populated, then we just default to existing behaviour
+and calculate the bitmask on the fly.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221107132901.489240-1-robimarko@gmail.com
+---
+ drivers/clk/qcom/reset.c | 4 ++--
+ drivers/clk/qcom/reset.h | 1 +
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/qcom/reset.c
++++ b/drivers/clk/qcom/reset.c
+@@ -30,7 +30,7 @@ qcom_reset_assert(struct reset_controlle
+
+ rst = to_qcom_reset_controller(rcdev);
+ map = &rst->reset_map[id];
+- mask = BIT(map->bit);
++ mask = map->bitmask ? map->bitmask : BIT(map->bit);
+
+ return regmap_update_bits(rst->regmap, map->reg, mask, mask);
+ }
+@@ -44,7 +44,7 @@ qcom_reset_deassert(struct reset_control
+
+ rst = to_qcom_reset_controller(rcdev);
+ map = &rst->reset_map[id];
+- mask = BIT(map->bit);
++ mask = map->bitmask ? map->bitmask : BIT(map->bit);
+
+ return regmap_update_bits(rst->regmap, map->reg, mask, 0);
+ }
+--- a/drivers/clk/qcom/reset.h
++++ b/drivers/clk/qcom/reset.h
+@@ -12,6 +12,7 @@ struct qcom_reset_map {
+ unsigned int reg;
+ u8 bit;
+ u8 udelay;
++ u32 bitmask;
+ };
+
+ struct regmap;
--- /dev/null
+From e78a40eb24187a8b4f9b89e2181f674df39c2013 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 7 Nov 2022 14:29:00 +0100
+Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add missing networking
+ resets
+
+Add bindings for the missing networking resets found in IPQ8074 GCC.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221107132901.489240-2-robimarko@gmail.com
+---
+ include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
++++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+@@ -367,6 +367,20 @@
+ #define GCC_PCIE1_AHB_ARES 129
+ #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
+ #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
++#define GCC_PPE_FULL_RESET 132
++#define GCC_UNIPHY0_SOFT_RESET 133
++#define GCC_UNIPHY0_XPCS_RESET 134
++#define GCC_UNIPHY1_SOFT_RESET 135
++#define GCC_UNIPHY1_XPCS_RESET 136
++#define GCC_UNIPHY2_SOFT_RESET 137
++#define GCC_UNIPHY2_XPCS_RESET 138
++#define GCC_EDMA_HW_RESET 139
++#define GCC_NSSPORT1_RESET 140
++#define GCC_NSSPORT2_RESET 141
++#define GCC_NSSPORT3_RESET 142
++#define GCC_NSSPORT4_RESET 143
++#define GCC_NSSPORT5_RESET 144
++#define GCC_NSSPORT6_RESET 145
+
+ #define USB0_GDSC 0
+ #define USB1_GDSC 1
--- /dev/null
+From da76cb63d04dc22ed32123b8c1d084c006d67bfb Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 7 Nov 2022 14:29:01 +0100
+Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets
+
+Downstream QCA 5.4 kernel defines networking resets which are not present
+in the mainline kernel but are required for the networking drivers.
+
+So, port the downstream resets and avoid using magic values for mask,
+construct mask for resets which require multiple bits to be set/cleared.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -4671,6 +4671,20 @@ static const struct qcom_reset_map gcc_i
+ [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
+ [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
+ [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
++ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
++ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
++ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
++ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
++ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
++ [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
++ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
++ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
++ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
++ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
++ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
++ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
++ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
++ [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
+ };
+
+ static struct gdsc *gcc_ipq8074_gdscs[] = {
--- /dev/null
+From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 16 Nov 2022 22:46:55 +0100
+Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
+
+It appears that having only .name populated in parent_data for clocks
+which are only globally searchable currently will not work as the clk core
+won't copy that name if there is no .fw_name present as well.
+
+So, populate .fw_name for all parent clocks in parent_data.
+
+Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
+
+Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
+ 1 file changed, 26 insertions(+), 26 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
+ };
+
+ static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
+- { .name = "pcie20_phy0_pipe_clk" },
++ { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
+ { .fw_name = "xo", .name = "xo" },
+ };
+
+@@ -733,7 +733,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
+ };
+
+ static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
+- { .name = "pcie20_phy1_pipe_clk" },
++ { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
+ { .fw_name = "xo", .name = "xo" },
+ };
+
+@@ -1137,7 +1137,7 @@ static const struct freq_tbl ftbl_nss_no
+
+ static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
+ { .fw_name = "xo", .name = "xo" },
+- { .name = "bias_pll_nss_noc_clk" },
++ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ };
+@@ -1362,7 +1362,7 @@ static const struct freq_tbl ftbl_nss_pp
+
+ static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ { .fw_name = "xo", .name = "xo" },
+- { .name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &nss_crypto_pll.clkr.hw },
+@@ -1413,10 +1413,10 @@ static const struct freq_tbl ftbl_nss_po
+
+ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+- { .name = "uniphy0_gcc_rx_clk" },
+- { .name = "uniphy0_gcc_tx_clk" },
++ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+- { .name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+
+ static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
+@@ -1465,10 +1465,10 @@ static const struct freq_tbl ftbl_nss_po
+
+ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+- { .name = "uniphy0_gcc_tx_clk" },
+- { .name = "uniphy0_gcc_rx_clk" },
++ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+- { .name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+
+ static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
+@@ -1696,12 +1696,12 @@ static const struct freq_tbl ftbl_nss_po
+
+ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+- { .name = "uniphy0_gcc_rx_clk" },
+- { .name = "uniphy0_gcc_tx_clk" },
+- { .name = "uniphy1_gcc_rx_clk" },
+- { .name = "uniphy1_gcc_tx_clk" },
++ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
++ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+- { .name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+
+ static const struct parent_map
+@@ -1758,12 +1758,12 @@ static const struct freq_tbl ftbl_nss_po
+
+ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+- { .name = "uniphy0_gcc_tx_clk" },
+- { .name = "uniphy0_gcc_rx_clk" },
+- { .name = "uniphy1_gcc_tx_clk" },
+- { .name = "uniphy1_gcc_rx_clk" },
++ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
++ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+- { .name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+
+ static const struct parent_map
+@@ -1820,10 +1820,10 @@ static const struct freq_tbl ftbl_nss_po
+
+ static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+- { .name = "uniphy2_gcc_rx_clk" },
+- { .name = "uniphy2_gcc_tx_clk" },
++ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
++ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+- { .name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+
+ static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
+@@ -1877,10 +1877,10 @@ static const struct freq_tbl ftbl_nss_po
+
+ static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+- { .name = "uniphy2_gcc_tx_clk" },
+- { .name = "uniphy2_gcc_rx_clk" },
++ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
++ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+- { .name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+
+ static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
--- /dev/null
+From 9033c3c86ea0dd35bd2ab957317573b755967298 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sun, 30 Oct 2022 18:57:03 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: pass XO and sleep clocks to GCC
+
+Pass XO and sleep clocks to the GCC controller so it does not have to
+find them by matching globaly by name.
+
+If not passed directly, driver maintains backwards compatibility by then
+falling back to global lookup.
+
+Since we are here, set cell numbers in decimal instead of hex.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -361,9 +361,11 @@
+ gcc: gcc@1800000 {
+ compatible = "qcom,gcc-ipq8074";
+ reg = <0x01800000 0x80000>;
+- #clock-cells = <0x1>;
++ clocks = <&xo>, <&sleep_clk>;
++ clock-names = "xo", "sleep_clk";
++ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+- #reset-cells = <0x1>;
++ #reset-cells = <1>;
+ };
+
+ tcsr_mutex: hwlock@1905000 {
--- /dev/null
+From fb76b808f8628215afebaf0f8af0bde635302590 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:18:14 +0200
+Subject: [PATCH] arm64: dts: qcom: add PMP8074 DTSI
+
+PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is
+controlled via SPMI.
+
+Add DTSI for it providing GPIO, regulator, RTC and VADC support.
+
+RTC is disabled by default as there is no built-in battery so it will
+loose time unless board vendor added a battery, so make it optional.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++
+ 1 file changed, 125 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
+@@ -0,0 +1,125 @@
++// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
++
++#include <dt-bindings/spmi/spmi.h>
++#include <dt-bindings/iio/qcom,spmi-vadc.h>
++
++&spmi_bus {
++ pmic@0 {
++ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
++ reg = <0x0 SPMI_USID>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ pmp8074_adc: adc@3100 {
++ compatible = "qcom,spmi-adc-rev2";
++ reg = <0x3100>;
++ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ #io-channel-cells = <1>;
++
++ ref-gnd@0 {
++ reg = <ADC5_REF_GND>;
++ qcom,pre-scaling = <1 1>;
++ };
++
++ vref-1p25@1 {
++ reg = <ADC5_1P25VREF>;
++ qcom,pre-scaling = <1 1>;
++ };
++
++ vref-vadc@2 {
++ reg = <ADC5_VREF_VADC>;
++ qcom,pre-scaling = <1 1>;
++ };
++
++ pmic_die: die-temp@6 {
++ reg = <ADC5_DIE_TEMP>;
++ qcom,pre-scaling = <1 1>;
++ };
++
++ xo_therm: xo-temp@76 {
++ reg = <ADC5_XO_THERM_100K_PU>;
++ qcom,ratiometric;
++ qcom,hw-settle-time = <200>;
++ qcom,pre-scaling = <1 1>;
++ };
++
++ pa_therm1: thermistor1@77 {
++ reg = <ADC5_AMUX_THM1_100K_PU>;
++ qcom,ratiometric;
++ qcom,hw-settle-time = <200>;
++ qcom,pre-scaling = <1 1>;
++ };
++
++ pa_therm2: thermistor2@78 {
++ reg = <ADC5_AMUX_THM2_100K_PU>;
++ qcom,ratiometric;
++ qcom,hw-settle-time = <200>;
++ qcom,pre-scaling = <1 1>;
++ };
++
++ pa_therm3: thermistor3@79 {
++ reg = <ADC5_AMUX_THM3_100K_PU>;
++ qcom,ratiometric;
++ qcom,hw-settle-time = <200>;
++ qcom,pre-scaling = <1 1>;
++ };
++
++ vph-pwr@131 {
++ reg = <ADC5_VPH_PWR>;
++ qcom,pre-scaling = <1 3>;
++ };
++ };
++
++ pmp8074_rtc: rtc@6000 {
++ compatible = "qcom,pm8941-rtc";
++ reg = <0x6000>;
++ reg-names = "rtc", "alarm";
++ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
++ allow-set-time;
++ status = "disabled";
++ };
++
++ pmp8074_gpios: gpio@c000 {
++ compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
++ reg = <0xc000>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pmp8074_gpios 0 0 12>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++ };
++
++ pmic@1 {
++ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
++ reg = <0x1 SPMI_USID>;
++
++ regulators {
++ compatible = "qcom,pmp8074-regulators";
++
++ s3: s3 {
++ regulator-name = "vdd_s3";
++ regulator-min-microvolt = <592000>;
++ regulator-max-microvolt = <1064000>;
++ regulator-always-on;
++ regulator-boot-on;
++ };
++
++ s4: s4 {
++ regulator-name = "vdd_s4";
++ regulator-min-microvolt = <712000>;
++ regulator-max-microvolt = <992000>;
++ regulator-always-on;
++ regulator-boot-on;
++ };
++
++ l11: l11 {
++ regulator-name = "l11";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++ };
++ };
++};
--- /dev/null
+From 2c394cfc1779886048feca7dc7f4075da5f6328c Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:18:15 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply
+
+Since now we have control over the PMP8074 PMIC providing various system
+voltages including L11 which provides the SDIO/eMMC I/O voltage set it as
+the SDHCI VQMMC supply.
+
+This allows SDHCI controller to switch to 1.8V I/O mode and support high
+speed modes like HS200 and HS400.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+@@ -3,6 +3,7 @@
+ /* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+ #include "ipq8074.dtsi"
++#include "pmp8074.dtsi"
+
+ / {
+ model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
+@@ -84,6 +85,7 @@
+
+ &sdhc_1 {
+ status = "okay";
++ vqmmc-supply = <&l11>;
+ };
+
+ &qusb_phy_0 {
--- /dev/null
+From 82ceb86227b1fc15c76d5fc691b2bf425f1a63b3 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 7 Nov 2022 10:29:30 +0100
+Subject: [PATCH] arm64: dts: qcom: hk01: use GPIO flags for tlmm
+
+Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of
+harcoding the cell value.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221107092930.33325-3-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+@@ -4,6 +4,7 @@
+ */
+ #include "ipq8074.dtsi"
+ #include "pmp8074.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+
+ / {
+ model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
+@@ -52,12 +53,12 @@
+
+ &pcie0 {
+ status = "okay";
+- perst-gpios = <&tlmm 61 0x1>;
++ perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+ };
+
+ &pcie1 {
+ status = "okay";
+- perst-gpios = <&tlmm 58 0x1>;
++ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ };
+
+ &pcie_qmp0 {
--- /dev/null
+From 1b1c1423ca3e740984aa883512a72c4ea08fbe28 Mon Sep 17 00:00:00 2001
+From: Konrad Dybcio <konrad.dybcio@linaro.org>
+Date: Mon, 7 Nov 2022 15:55:17 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074-*: Fix up comments
+
+Make sure all multiline C-style commends begin with just '/*' with
+the comment text starting on a new line.
+
+Also, fix up some whitespace within comments.
+
+Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221107145522.6706-8-konrad.dybcio@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 3 ++-
+ arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts | 3 ++-
+ arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts | 3 ++-
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++------
+ 4 files changed, 12 insertions(+), 9 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+@@ -1,6 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /dts-v1/;
+-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+ #include "ipq8074.dtsi"
+ #include "pmp8074.dtsi"
+--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
+@@ -1,5 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
++/*
++ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+ /dts-v1/;
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
+@@ -1,6 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /dts-v1/;
+-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
++/*
++ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+ #include "ipq8074-hk10.dtsi"
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -129,10 +129,10 @@
+ status = "disabled";
+
+ usb1_ssphy: phy@58200 {
+- reg = <0x00058200 0x130>, /* Tx */
++ reg = <0x00058200 0x130>, /* Tx */
+ <0x00058400 0x200>, /* Rx */
+- <0x00058800 0x1f8>, /* PCS */
+- <0x00058600 0x044>; /* PCS misc*/
++ <0x00058800 0x1f8>, /* PCS */
++ <0x00058600 0x044>; /* PCS misc */
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_USB1_PIPE_CLK>;
+@@ -172,10 +172,10 @@
+ status = "disabled";
+
+ usb0_ssphy: phy@78200 {
+- reg = <0x00078200 0x130>, /* Tx */
++ reg = <0x00078200 0x130>, /* Tx */
+ <0x00078400 0x200>, /* Rx */
+- <0x00078800 0x1f8>, /* PCS */
+- <0x00078600 0x044>; /* PCS misc*/
++ <0x00078800 0x1f8>, /* PCS */
++ <0x00078600 0x044>; /* PCS misc */
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
--- /dev/null
+From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Tue, 8 Nov 2022 15:23:57 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
+ DT schema
+
+DT schema expects TLMM pin configuration nodes to be named with
+'-state' suffix and their optional children with '-pins' suffix.
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -318,35 +318,35 @@
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+
+- serial_4_pins: serial4-pinmux {
++ serial_4_pins: serial4-state {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+- i2c_0_pins: i2c-0-pinmux {
++ i2c_0_pins: i2c-0-state {
+ pins = "gpio42", "gpio43";
+ function = "blsp1_i2c";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+- spi_0_pins: spi-0-pins {
++ spi_0_pins: spi-0-state {
+ pins = "gpio38", "gpio39", "gpio40", "gpio41";
+ function = "blsp0_spi";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+- hsuart_pins: hsuart-pins {
++ hsuart_pins: hsuart-state {
+ pins = "gpio46", "gpio47", "gpio48", "gpio49";
+ function = "blsp2_uart";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+- qpic_pins: qpic-pins {
++ qpic_pins: qpic-state {
+ pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
--- /dev/null
+From 77faa07c185c969e742cbb3e6aa487a11b0b616c Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Tue, 30 Aug 2022 09:57:42 +0300
+Subject: [PATCH] dt-bindings: arm: qcom: document qcom,msm-id and
+ qcom,board-id
+
+The top level qcom,msm-id and qcom,board-id properties are utilized by
+bootloaders on Qualcomm MSM platforms to determine which device tree
+should be used and passed to the kernel.
+
+The commit b32e592d3c28 ("devicetree: bindings: Document qcom board
+compatible format") from 2015 was a consensus during discussion about
+upstreaming qcom,msm-id and qcom,board-id fields. There are however still
+problems with that consensus:
+1. It was reached 7 years ago but it turned out its implementation did
+ not reach all possible products.
+
+2. Initially additional tool (dtbTool) was needed for parsing these
+ fields to create a QCDT image consisting of multiple DTBs, later the
+ bootloaders were improved and they use these qcom,msm-id and
+ qcom,board-id properties directly.
+
+3. Extracting relevant information from the board compatible requires
+ this additional tool (dtbTool), which makes the build process more
+ complicated and not easily reproducible (DTBs are modified after the
+ kernel build).
+
+4. Some versions of Qualcomm bootloaders expect these properties even
+ when booting with a single DTB. The community is stuck with these
+ bootloaders thus they require properties in the DTBs.
+
+Since several upstreamed Qualcomm SoC-based boards require these
+properties to properly boot and the properties are reportedly used by
+bootloaders, document them along with the bindings header with constants
+used by: bootloader, some DTS and socinfo driver.
+
+Link: https://lore.kernel.org/r/a3c932d1-a102-ce18-deea-18cbbd05ecab@linaro.org/
+Co-developed-by: Kumar Gala <galak@codeaurora.org>
+Signed-off-by: Kumar Gala <galak@codeaurora.org>
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220830065744.161163-2-krzysztof.kozlowski@linaro.org
+---
+ include/dt-bindings/arm/qcom,ids.h | 155 +++++++++++++++++++++++++++++
+ 1 file changed, 155 insertions(+)
+ create mode 100644 include/dt-bindings/arm/qcom,ids.h
+
+--- /dev/null
++++ b/include/dt-bindings/arm/qcom,ids.h
+@@ -0,0 +1,155 @@
++/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
++/*
++ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
++ * Copyright (c) 2022 Linaro Ltd
++ * Author: Krzysztof Kozlowski <krzk@kernel.org> based on previous work of Kumar Gala.
++ */
++#ifndef _DT_BINDINGS_ARM_QCOM_IDS_H
++#define _DT_BINDINGS_ARM_QCOM_IDS_H
++
++/*
++ * The MSM chipset and hardware revision used by Qualcomm bootloaders, DTS for
++ * older chipsets (qcom,msm-id) and in socinfo driver:
++ */
++#define QCOM_ID_MSM8960 87
++#define QCOM_ID_APQ8064 109
++#define QCOM_ID_MSM8660A 122
++#define QCOM_ID_MSM8260A 123
++#define QCOM_ID_APQ8060A 124
++#define QCOM_ID_MSM8974 126
++#define QCOM_ID_MPQ8064 130
++#define QCOM_ID_MSM8960AB 138
++#define QCOM_ID_APQ8060AB 139
++#define QCOM_ID_MSM8260AB 140
++#define QCOM_ID_MSM8660AB 141
++#define QCOM_ID_MSM8626 145
++#define QCOM_ID_MSM8610 147
++#define QCOM_ID_APQ8064AB 153
++#define QCOM_ID_MSM8226 158
++#define QCOM_ID_MSM8526 159
++#define QCOM_ID_MSM8110 161
++#define QCOM_ID_MSM8210 162
++#define QCOM_ID_MSM8810 163
++#define QCOM_ID_MSM8212 164
++#define QCOM_ID_MSM8612 165
++#define QCOM_ID_MSM8112 166
++#define QCOM_ID_MSM8225Q 168
++#define QCOM_ID_MSM8625Q 169
++#define QCOM_ID_MSM8125Q 170
++#define QCOM_ID_APQ8064AA 172
++#define QCOM_ID_APQ8084 178
++#define QCOM_ID_APQ8074 184
++#define QCOM_ID_MSM8274 185
++#define QCOM_ID_MSM8674 186
++#define QCOM_ID_MSM8974PRO_AC 194
++#define QCOM_ID_MSM8126 198
++#define QCOM_ID_APQ8026 199
++#define QCOM_ID_MSM8926 200
++#define QCOM_ID_MSM8326 205
++#define QCOM_ID_MSM8916 206
++#define QCOM_ID_MSM8994 207
++#define QCOM_ID_APQ8074PRO_AA 208
++#define QCOM_ID_APQ8074PRO_AB 209
++#define QCOM_ID_APQ8074PRO_AC 210
++#define QCOM_ID_MSM8274PRO_AA 211
++#define QCOM_ID_MSM8274PRO_AB 212
++#define QCOM_ID_MSM8274PRO_AC 213
++#define QCOM_ID_MSM8674PRO_AA 214
++#define QCOM_ID_MSM8674PRO_AB 215
++#define QCOM_ID_MSM8674PRO_AC 216
++#define QCOM_ID_MSM8974PRO_AA 217
++#define QCOM_ID_MSM8974PRO_AB 218
++#define QCOM_ID_APQ8028 219
++#define QCOM_ID_MSM8128 220
++#define QCOM_ID_MSM8228 221
++#define QCOM_ID_MSM8528 222
++#define QCOM_ID_MSM8628 223
++#define QCOM_ID_MSM8928 224
++#define QCOM_ID_MSM8510 225
++#define QCOM_ID_MSM8512 226
++#define QCOM_ID_MSM8936 233
++#define QCOM_ID_MSM8939 239
++#define QCOM_ID_APQ8036 240
++#define QCOM_ID_APQ8039 241
++#define QCOM_ID_MSM8996 246
++#define QCOM_ID_APQ8016 247
++#define QCOM_ID_MSM8216 248
++#define QCOM_ID_MSM8116 249
++#define QCOM_ID_MSM8616 250
++#define QCOM_ID_MSM8992 251
++#define QCOM_ID_APQ8094 253
++#define QCOM_ID_MDM9607 290
++#define QCOM_ID_APQ8096 291
++#define QCOM_ID_MSM8998 292
++#define QCOM_ID_MSM8953 293
++#define QCOM_ID_MDM8207 296
++#define QCOM_ID_MDM9207 297
++#define QCOM_ID_MDM9307 298
++#define QCOM_ID_MDM9628 299
++#define QCOM_ID_APQ8053 304
++#define QCOM_ID_MSM8996SG 305
++#define QCOM_ID_MSM8996AU 310
++#define QCOM_ID_APQ8096AU 311
++#define QCOM_ID_APQ8096SG 312
++#define QCOM_ID_SDM660 317
++#define QCOM_ID_SDM630 318
++#define QCOM_ID_APQ8098 319
++#define QCOM_ID_SDM845 321
++#define QCOM_ID_MDM9206 322
++#define QCOM_ID_IPQ8074 323
++#define QCOM_ID_SDA660 324
++#define QCOM_ID_SDM658 325
++#define QCOM_ID_SDA658 326
++#define QCOM_ID_SDA630 327
++#define QCOM_ID_SDM450 338
++#define QCOM_ID_SDA845 341
++#define QCOM_ID_IPQ8072 342
++#define QCOM_ID_IPQ8076 343
++#define QCOM_ID_IPQ8078 344
++#define QCOM_ID_SDM636 345
++#define QCOM_ID_SDA636 346
++#define QCOM_ID_SDM632 349
++#define QCOM_ID_SDA632 350
++#define QCOM_ID_SDA450 351
++#define QCOM_ID_SM8250 356
++#define QCOM_ID_IPQ8070 375
++#define QCOM_ID_IPQ8071 376
++#define QCOM_ID_IPQ8072A 389
++#define QCOM_ID_IPQ8074A 390
++#define QCOM_ID_IPQ8076A 391
++#define QCOM_ID_IPQ8078A 392
++#define QCOM_ID_SM6125 394
++#define QCOM_ID_IPQ8070A 395
++#define QCOM_ID_IPQ8071A 396
++#define QCOM_ID_IPQ6018 402
++#define QCOM_ID_IPQ6028 403
++#define QCOM_ID_IPQ6000 421
++#define QCOM_ID_IPQ6010 422
++#define QCOM_ID_SC7180 425
++#define QCOM_ID_SM6350 434
++#define QCOM_ID_SM8350 439
++#define QCOM_ID_SC8280XP 449
++#define QCOM_ID_IPQ6005 453
++#define QCOM_ID_QRB5165 455
++#define QCOM_ID_SM8450 457
++#define QCOM_ID_SM7225 459
++#define QCOM_ID_SA8295P 460
++#define QCOM_ID_SA8540P 461
++#define QCOM_ID_SM8450_2 480
++#define QCOM_ID_SM8450_3 482
++#define QCOM_ID_SC7280 487
++#define QCOM_ID_SC7180P 495
++#define QCOM_ID_SM6375 507
++
++/*
++ * The board type and revision information, used by Qualcomm bootloaders and
++ * DTS for older chipsets (qcom,board-id):
++ */
++#define QCOM_BOARD_ID(a, major, minor) \
++ (((major & 0xff) << 16) | ((minor & 0xff) << 8) | QCOM_BOARD_ID_##a)
++
++#define QCOM_BOARD_ID_MTP 8
++#define QCOM_BOARD_ID_DRAGONBOARD 10
++#define QCOM_BOARD_ID_SBC 24
++
++#endif /* _DT_BINDINGS_ARM_QCOM_IDS_H */
--- /dev/null
+From a4748d2850783d36f77ccf2b5fcc86ccf1800ef1 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 16 Nov 2022 22:48:36 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed
+
+Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
+generation limit.
+This allows the generic DWC code to configure the link speed correctly.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -766,6 +766,7 @@
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
++ max-link-speed = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
--- /dev/null
+From f356132229b18ceef5d5ef9103bbaa9bdeb84c8d Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 13 Jan 2023 17:44:47 +0100
+Subject: [PATCH] PCI: qcom: Add IPQ8074 Gen3 port support
+
+IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
+Add compatible for Gen3 port which uses the same controller as IPQ6018.
+
+Link: https://lore.kernel.org/r/20230113164449.906002-7-robimarko@gmail.com
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/controller/dwc/pcie-qcom.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/pci/controller/dwc/pcie-qcom.c
++++ b/drivers/pci/controller/dwc/pcie-qcom.c
+@@ -1745,6 +1745,7 @@ static const struct of_device_id qcom_pc
+ { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
+ { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
+ { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
++ { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
+ { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
+ { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
+ { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
--- /dev/null
+From 614d31c231c7707322b643f409eeb7e28adc7f8c Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sun, 8 Jan 2023 13:36:28 +0100
+Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for usb3phy-s
+
+Having only .name populated in parent_data for clocks which are only
+globally searchable currently will not work as the clk core won't copy
+that name if there is no .fw_name present as well.
+
+So, populate .fw_name for usb3phy clocks in parent_data as they were
+missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
+
+Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -934,7 +934,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
+ };
+
+ static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
+- { .name = "usb3phy_0_cc_pipe_clk" },
++ { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
+ { .fw_name = "xo", .name = "xo" },
+ };
+
+@@ -1002,7 +1002,7 @@ static struct clk_rcg2 usb1_mock_utmi_cl
+ };
+
+ static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
+- { .name = "usb3phy_1_cc_pipe_clk" },
++ { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
+ { .fw_name = "xo", .name = "xo" },
+ };
+
+++ /dev/null
-From 6463c10bfdbd684ec7ecfd408ea541283215a088 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:06:28 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add A53 PLL node
-
-Add the required node for A53 PLL which will be used to provide the CPU
-clock via APCS for APSS scaling.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220628.339366-9-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -675,6 +675,14 @@
- #mbox-cells = <1>;
- };
-
-+ a53pll: clock@b116000 {
-+ compatible = "qcom,ipq8074-a53pll";
-+ reg = <0x0b116000 0x40>;
-+ #clock-cells = <0>;
-+ clocks = <&xo>;
-+ clock-names = "xo";
-+ };
-+
- timer@b120000 {
- #address-cells = <1>;
- #size-cells = <1>;
+++ /dev/null
-From e593e834fe8ba9bf314d8215ac05d8787f81efda Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:02:42 +0200
-Subject: [PATCH] thermal/drivers/tsens: Add support for combined interrupt
-
-Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
-signaling both up/low and critical trips.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220245.338396-2-robimarko@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/qcom/tsens-8960.c | 1 +
- drivers/thermal/qcom/tsens-v0_1.c | 1 +
- drivers/thermal/qcom/tsens-v1.c | 1 +
- drivers/thermal/qcom/tsens-v2.c | 1 +
- drivers/thermal/qcom/tsens.c | 38 ++++++++++++++++++++++++++-----
- drivers/thermal/qcom/tsens.h | 2 ++
- 6 files changed, 38 insertions(+), 6 deletions(-)
-
---- a/drivers/thermal/qcom/tsens-8960.c
-+++ b/drivers/thermal/qcom/tsens-8960.c
-@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
- static struct tsens_features tsens_8960_feat = {
- .ver_major = VER_0,
- .crit_int = 0,
-+ .combo_int = 0,
- .adc = 1,
- .srot_split = 0,
- .max_sensors = 11,
---- a/drivers/thermal/qcom/tsens-v0_1.c
-+++ b/drivers/thermal/qcom/tsens-v0_1.c
-@@ -549,6 +549,7 @@ static int __init init_8939(struct tsens
- static struct tsens_features tsens_v0_1_feat = {
- .ver_major = VER_0_1,
- .crit_int = 0,
-+ .combo_int = 0,
- .adc = 1,
- .srot_split = 1,
- .max_sensors = 11,
---- a/drivers/thermal/qcom/tsens-v1.c
-+++ b/drivers/thermal/qcom/tsens-v1.c
-@@ -273,6 +273,7 @@ static int calibrate_8976(struct tsens_p
- static struct tsens_features tsens_v1_feat = {
- .ver_major = VER_1_X,
- .crit_int = 0,
-+ .combo_int = 0,
- .adc = 1,
- .srot_split = 1,
- .max_sensors = 11,
---- a/drivers/thermal/qcom/tsens-v2.c
-+++ b/drivers/thermal/qcom/tsens-v2.c
-@@ -31,6 +31,7 @@
- static struct tsens_features tsens_v2_feat = {
- .ver_major = VER_2_X,
- .crit_int = 1,
-+ .combo_int = 0,
- .adc = 0,
- .srot_split = 1,
- .max_sensors = 16,
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -532,6 +532,27 @@ static irqreturn_t tsens_irq_thread(int
- return IRQ_HANDLED;
- }
-
-+/**
-+ * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
-+ * @irq: irq number
-+ * @data: tsens controller private data
-+ *
-+ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
-+ * critical handler first and then the up/low one.
-+ *
-+ * Return: IRQ_HANDLED
-+ */
-+static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
-+{
-+ irqreturn_t ret;
-+
-+ ret = tsens_critical_irq_thread(irq, data);
-+ if (ret != IRQ_HANDLED)
-+ return ret;
-+
-+ return tsens_irq_thread(irq, data);
-+}
-+
- static int tsens_set_trips(struct thermal_zone_device *tz, int low, int high)
- {
- struct tsens_sensor *s = tz->devdata;
-@@ -1074,13 +1095,18 @@ static int tsens_register(struct tsens_p
- tsens_mC_to_hw(priv->sensor, 0));
- }
-
-- ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
-- if (ret < 0)
-- return ret;
-+ if (priv->feat->combo_int) {
-+ ret = tsens_register_irq(priv, "combined",
-+ tsens_combined_irq_thread);
-+ } else {
-+ ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
-+ if (ret < 0)
-+ return ret;
-
-- if (priv->feat->crit_int)
-- ret = tsens_register_irq(priv, "critical",
-- tsens_critical_irq_thread);
-+ if (priv->feat->crit_int)
-+ ret = tsens_register_irq(priv, "critical",
-+ tsens_critical_irq_thread);
-+ }
-
- return ret;
- }
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -493,6 +493,7 @@ enum regfield_ids {
- * struct tsens_features - Features supported by the IP
- * @ver_major: Major number of IP version
- * @crit_int: does the IP support critical interrupts?
-+ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
- * @adc: do the sensors only output adc code (instead of temperature)?
- * @srot_split: does the IP neatly splits the register space into SROT and TM,
- * with SROT only being available to secure boot firmware?
-@@ -502,6 +503,7 @@ enum regfield_ids {
- struct tsens_features {
- unsigned int ver_major;
- unsigned int crit_int:1;
-+ unsigned int combo_int:1;
- unsigned int adc:1;
- unsigned int srot_split:1;
- unsigned int has_watchdog:1;
+++ /dev/null
-From 7805365fee582056b32c69cf35aafbb94b14a8ca Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:02:43 +0200
-Subject: [PATCH] thermal/drivers/tsens: Allow configuring min and max trips
-
-IPQ8074 and IPQ6018 dont support negative trip temperatures and support
-up to 204 degrees C as the max trip temperature.
-
-So, instead of always setting the -40 as min and 120 degrees C as max
-allow it to be configured as part of the features.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220818220245.338396-3-robimarko@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/qcom/tsens-8960.c | 2 ++
- drivers/thermal/qcom/tsens-v0_1.c | 2 ++
- drivers/thermal/qcom/tsens-v1.c | 2 ++
- drivers/thermal/qcom/tsens-v2.c | 2 ++
- drivers/thermal/qcom/tsens.c | 4 ++--
- drivers/thermal/qcom/tsens.h | 4 ++++
- 6 files changed, 14 insertions(+), 2 deletions(-)
-
---- a/drivers/thermal/qcom/tsens-8960.c
-+++ b/drivers/thermal/qcom/tsens-8960.c
-@@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_
- .adc = 1,
- .srot_split = 0,
- .max_sensors = 11,
-+ .trip_min_temp = -40000,
-+ .trip_max_temp = 120000,
- };
-
- struct tsens_plat_data data_8960 = {
---- a/drivers/thermal/qcom/tsens-v0_1.c
-+++ b/drivers/thermal/qcom/tsens-v0_1.c
-@@ -553,6 +553,8 @@ static struct tsens_features tsens_v0_1_
- .adc = 1,
- .srot_split = 1,
- .max_sensors = 11,
-+ .trip_min_temp = -40000,
-+ .trip_max_temp = 120000,
- };
-
- static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
---- a/drivers/thermal/qcom/tsens-v1.c
-+++ b/drivers/thermal/qcom/tsens-v1.c
-@@ -277,6 +277,8 @@ static struct tsens_features tsens_v1_fe
- .adc = 1,
- .srot_split = 1,
- .max_sensors = 11,
-+ .trip_min_temp = -40000,
-+ .trip_max_temp = 120000,
- };
-
- static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
---- a/drivers/thermal/qcom/tsens-v2.c
-+++ b/drivers/thermal/qcom/tsens-v2.c
-@@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_fe
- .adc = 0,
- .srot_split = 1,
- .max_sensors = 16,
-+ .trip_min_temp = -40000,
-+ .trip_max_temp = 120000,
- };
-
- static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -573,8 +573,8 @@ static int tsens_set_trips(struct therma
- dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
- hw_id, __func__, low, high);
-
-- cl_high = clamp_val(high, -40000, 120000);
-- cl_low = clamp_val(low, -40000, 120000);
-+ cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
-+ cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
-
- high_val = tsens_mC_to_hw(s, cl_high);
- low_val = tsens_mC_to_hw(s, cl_low);
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -499,6 +499,8 @@ enum regfield_ids {
- * with SROT only being available to secure boot firmware?
- * @has_watchdog: does this IP support watchdog functionality?
- * @max_sensors: maximum sensors supported by this version of the IP
-+ * @trip_min_temp: minimum trip temperature supported by this version of the IP
-+ * @trip_max_temp: maximum trip temperature supported by this version of the IP
- */
- struct tsens_features {
- unsigned int ver_major;
-@@ -508,6 +510,8 @@ struct tsens_features {
- unsigned int srot_split:1;
- unsigned int has_watchdog:1;
- unsigned int max_sensors;
-+ int trip_min_temp;
-+ int trip_max_temp;
- };
-
- /**
+++ /dev/null
-From 0164d794cbc58488a7321272e95958d10cf103a4 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:02:44 +0200
-Subject: [PATCH] thermal/drivers/tsens: Add IPQ8074 support
-
-Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP
-it only has one IRQ, that is used for up/low as well as critical.
-It also does not support negative trip temperatures.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220818220245.338396-4-robimarko@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++
- drivers/thermal/qcom/tsens.c | 3 +++
- drivers/thermal/qcom/tsens.h | 2 +-
- 3 files changed, 21 insertions(+), 1 deletion(-)
-
---- a/drivers/thermal/qcom/tsens-v2.c
-+++ b/drivers/thermal/qcom/tsens-v2.c
-@@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_fe
- .trip_max_temp = 120000,
- };
-
-+static struct tsens_features ipq8074_feat = {
-+ .ver_major = VER_2_X,
-+ .crit_int = 1,
-+ .combo_int = 1,
-+ .adc = 0,
-+ .srot_split = 1,
-+ .max_sensors = 16,
-+ .trip_min_temp = 0,
-+ .trip_max_temp = 204000,
-+};
-+
- static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
- /* ----- SROT ------ */
- /* VERSION */
-@@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = {
- .fields = tsens_v2_regfields,
- };
-
-+struct tsens_plat_data data_ipq8074 = {
-+ .ops = &ops_generic_v2,
-+ .feat = &ipq8074_feat,
-+ .fields = tsens_v2_regfields,
-+};
-+
- /* Kept around for backward compatibility with old msm8996.dtsi */
- struct tsens_plat_data data_8996 = {
- .num_sensors = 13,
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -981,6 +981,9 @@ static const struct of_device_id tsens_t
- .compatible = "qcom,ipq8064-tsens",
- .data = &data_8960,
- }, {
-+ .compatible = "qcom,ipq8074-tsens",
-+ .data = &data_ipq8074,
-+ }, {
- .compatible = "qcom,mdm9607-tsens",
- .data = &data_9607,
- }, {
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -597,6 +597,6 @@ extern struct tsens_plat_data data_8916,
- extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
-
- /* TSENS v2 targets */
--extern struct tsens_plat_data data_8996, data_tsens_v2;
-+extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
-
- #endif /* __QCOM_TSENS_H__ */
+++ /dev/null
-From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:02:45 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
-
-IPQ8074 has a tsens v2.3.0 peripheral which monitors
-temperatures around the various subsystems on the
-die.
-
-So lets add the tsens and thermal zone nodes, passive
-CPU cooling will come in later patches after CPU frequency
-scaling is supported.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
- 1 file changed, 96 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -274,6 +274,16 @@
- status = "disabled";
- };
-
-+ tsens: thermal-sensor@4a9000 {
-+ compatible = "qcom,ipq8074-tsens";
-+ reg = <0x4a9000 0x1000>, /* TM */
-+ <0x4a8000 0x1000>; /* SROT */
-+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "combined";
-+ #qcom,sensors = <16>;
-+ #thermal-sensor-cells = <1>;
-+ };
-+
- cryptobam: dma-controller@704000 {
- compatible = "qcom,bam-v1.7.0";
- reg = <0x00704000 0x20000>;
-@@ -874,4 +884,90 @@
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-+
-+ thermal-zones {
-+ nss-top-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 4>;
-+ };
-+
-+ nss0-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 5>;
-+ };
-+
-+ nss1-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 6>;
-+ };
-+
-+ wcss-phya0-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 7>;
-+ };
-+
-+ wcss-phya1-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 8>;
-+ };
-+
-+ cpu0_thermal: cpu0-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 9>;
-+ };
-+
-+ cpu1_thermal: cpu1-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 10>;
-+ };
-+
-+ cpu2_thermal: cpu2-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 11>;
-+ };
-+
-+ cpu3_thermal: cpu3-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 12>;
-+ };
-+
-+ cluster_thermal: cluster-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 13>;
-+ };
-+
-+ wcss-phyb0-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 14>;
-+ };
-+
-+ wcss-phyb1-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 15>;
-+ };
-+ };
- };
+++ /dev/null
-From 0df592a0a1a3fff9133977192677aa915afc174f Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:08:49 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add clocks to APCS
-
-APCS now has support for providing the APSS clocks as the child device
-for IPQ8074.
-
-So, add the A53 PLL and XO clocks in order to use APCS as the CPU
-clocksource for APSS scaling.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -680,6 +680,8 @@
- apcs_glb: mailbox@b111000 {
- compatible = "qcom,ipq8074-apcs-apps-global";
- reg = <0x0b111000 0x1000>;
-+ clocks = <&a53pll>, <&xo>;
-+ clock-names = "pll", "xo";
-
- #clock-cells = <1>;
- #mbox-cells = <1>;
+++ /dev/null
-From e6c5115d6845f25eda7e162dcd783a2044215867 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 30 Oct 2022 18:57:01 +0100
-Subject: [PATCH] clk: qcom: ipq8074: convert to parent data
-
-Convert the IPQ8074 GCC driver to use parent data instead of global
-name matching.
-
-Utilize ARRAY_SIZE for num_parents instead of hardcoding the value.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221030175703.1103224-1-robimarko@gmail.com
----
- drivers/clk/qcom/gcc-ipq8074.c | 1781 +++++++++++++++-----------------
- 1 file changed, 813 insertions(+), 968 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -49,349 +49,6 @@ enum {
- P_UNIPHY2_TX,
- };
-
--static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const struct parent_map gcc_xo_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
--};
--
--static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll2",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL2, 2 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const char * const gcc_xo_gpll0_sleep_clk[] = {
-- "xo",
-- "gpll0",
-- "sleep_clk",
--};
--
--static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 2 },
-- { P_SLEEP_CLK, 6 },
--};
--
--static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll6",
-- "gpll0",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL6, 1 },
-- { P_GPLL0, 3 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
-- "xo",
-- "gpll0_out_main_div2",
-- "gpll0",
--};
--
--static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0_DIV2, 2 },
-- { P_GPLL0, 1 },
--};
--
--static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
-- "usb3phy_0_cc_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
-- { P_USB3PHY_0_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
-- "usb3phy_1_cc_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
-- { P_USB3PHY_1_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
-- "pcie20_phy0_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
-- { P_PCIE20_PHY0_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
-- "pcie20_phy1_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
-- { P_PCIE20_PHY1_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll6",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL6, 2 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll6",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL6, 2 },
-- { P_GPLL0_DIV2, 3 },
--};
--
--static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
-- "xo",
-- "bias_pll_nss_noc_clk",
-- "gpll0",
-- "gpll2",
--};
--
--static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
-- { P_XO, 0 },
-- { P_BIAS_PLL_NSS_NOC, 1 },
-- { P_GPLL0, 2 },
-- { P_GPLL2, 3 },
--};
--
--static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
-- "xo",
-- "nss_crypto_pll",
-- "gpll0",
--};
--
--static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_NSS_CRYPTO_PLL, 1 },
-- { P_GPLL0, 2 },
--};
--
--static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
-- "xo",
-- "ubi32_pll",
-- "gpll0",
-- "gpll2",
-- "gpll4",
-- "gpll6",
--};
--
--static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
-- { P_XO, 0 },
-- { P_UBI32_PLL, 1 },
-- { P_GPLL0, 2 },
-- { P_GPLL2, 3 },
-- { P_GPLL4, 4 },
-- { P_GPLL6, 5 },
--};
--
--static const char * const gcc_xo_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0_DIV2, 1 },
--};
--
--static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
-- "xo",
-- "bias_pll_cc_clk",
-- "gpll0",
-- "gpll4",
-- "nss_crypto_pll",
-- "ubi32_pll",
--};
--
--static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
-- { P_XO, 0 },
-- { P_BIAS_PLL, 1 },
-- { P_GPLL0, 2 },
-- { P_GPLL4, 3 },
-- { P_NSS_CRYPTO_PLL, 4 },
-- { P_UBI32_PLL, 5 },
--};
--
--static const char * const gcc_xo_gpll0_gpll4[] = {
-- "xo",
-- "gpll0",
-- "gpll4",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL4, 2 },
--};
--
--static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_rx_clk",
-- "uniphy0_gcc_tx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_RX, 1 },
-- { P_UNIPHY0_TX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_tx_clk",
-- "uniphy0_gcc_rx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_TX, 1 },
-- { P_UNIPHY0_RX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_rx_clk",
-- "uniphy0_gcc_tx_clk",
-- "uniphy1_gcc_rx_clk",
-- "uniphy1_gcc_tx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map
--gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_RX, 1 },
-- { P_UNIPHY0_TX, 2 },
-- { P_UNIPHY1_RX, 3 },
-- { P_UNIPHY1_TX, 4 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_tx_clk",
-- "uniphy0_gcc_rx_clk",
-- "uniphy1_gcc_tx_clk",
-- "uniphy1_gcc_rx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map
--gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_TX, 1 },
-- { P_UNIPHY0_RX, 2 },
-- { P_UNIPHY1_TX, 3 },
-- { P_UNIPHY1_RX, 4 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
-- "xo",
-- "uniphy2_gcc_rx_clk",
-- "uniphy2_gcc_tx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY2_RX, 1 },
-- { P_UNIPHY2_TX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
-- "xo",
-- "uniphy2_gcc_tx_clk",
-- "uniphy2_gcc_rx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY2_TX, 1 },
-- { P_UNIPHY2_RX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
-- "xo",
-- "gpll0",
-- "gpll6",
-- "gpll0_out_main_div2",
-- "sleep_clk",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL6, 2 },
-- { P_GPLL0_DIV2, 4 },
-- { P_SLEEP_CLK, 6 },
--};
--
- static struct clk_alpha_pll gpll0_main = {
- .offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
-@@ -400,8 +57,9 @@ static struct clk_alpha_pll gpll0_main =
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -414,9 +72,8 @@ static struct clk_fixed_factor gpll0_out
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_out_main_div2",
-- .parent_names = (const char *[]){
-- "gpll0_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll0_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -429,9 +86,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
-- .parent_names = (const char *[]){
-- "gpll0_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll0_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -445,8 +101,9 @@ static struct clk_alpha_pll gpll2_main =
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gpll2_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -461,9 +118,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll2",
-- .parent_names = (const char *[]){
-- "gpll2_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll2_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -478,8 +134,9 @@ static struct clk_alpha_pll gpll4_main =
- .enable_mask = BIT(5),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -494,9 +151,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll4",
-- .parent_names = (const char *[]){
-- "gpll4_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll4_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -512,8 +168,9 @@ static struct clk_alpha_pll gpll6_main =
- .enable_mask = BIT(7),
- .hw.init = &(struct clk_init_data){
- .name = "gpll6_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -528,9 +185,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 2,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll6",
-- .parent_names = (const char *[]){
-- "gpll6_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll6_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -542,9 +198,8 @@ static struct clk_fixed_factor gpll6_out
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "gpll6_out_main_div2",
-- .parent_names = (const char *[]){
-- "gpll6_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll6_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -560,8 +215,9 @@ static struct clk_alpha_pll ubi32_pll_ma
- .enable_mask = BIT(6),
- .hw.init = &(struct clk_init_data){
- .name = "ubi32_pll_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_huayra_ops,
-@@ -575,9 +231,8 @@ static struct clk_alpha_pll_postdiv ubi3
- .width = 2,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ubi32_pll",
-- .parent_names = (const char *[]){
-- "ubi32_pll_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &ubi32_pll_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -592,8 +247,9 @@ static struct clk_alpha_pll nss_crypto_p
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "nss_crypto_pll_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -607,9 +263,8 @@ static struct clk_alpha_pll_postdiv nss_
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_crypto_pll",
-- .parent_names = (const char *[]){
-- "nss_crypto_pll_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_crypto_pll_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -623,6 +278,18 @@ static const struct freq_tbl ftbl_pcnoc_
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw},
-+ { .hw = &gpll0_out_main_div2.hw},
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
- .cmd_rcgr = 0x27000,
- .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
-@@ -630,8 +297,8 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcnoc_bfdcd_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- .flags = CLK_IS_CRITICAL,
- },
-@@ -642,9 +309,8 @@ static struct clk_fixed_factor pcnoc_clk
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "pcnoc_clk_src",
-- .parent_names = (const char *[]){
-- "pcnoc_bfdcd_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_bfdcd_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -658,8 +324,9 @@ static struct clk_branch gcc_sleep_clk_s
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sleep_clk_src",
-- .parent_names = (const char *[]){
-- "sleep_clk"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "sleep_clk",
-+ .name = "sleep_clk",
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
-@@ -682,8 +349,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -708,8 +375,8 @@ static struct clk_rcg2 blsp1_qup1_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -721,8 +388,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -735,8 +402,8 @@ static struct clk_rcg2 blsp1_qup2_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -748,8 +415,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -762,8 +429,8 @@ static struct clk_rcg2 blsp1_qup3_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -775,8 +442,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -789,8 +456,8 @@ static struct clk_rcg2 blsp1_qup4_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -802,8 +469,8 @@ static struct clk_rcg2 blsp1_qup5_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -816,8 +483,8 @@ static struct clk_rcg2 blsp1_qup5_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -829,8 +496,8 @@ static struct clk_rcg2 blsp1_qup6_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -843,8 +510,8 @@ static struct clk_rcg2 blsp1_qup6_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -877,8 +544,8 @@ static struct clk_rcg2 blsp1_uart1_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -891,8 +558,8 @@ static struct clk_rcg2 blsp1_uart2_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -905,8 +572,8 @@ static struct clk_rcg2 blsp1_uart3_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -919,8 +586,8 @@ static struct clk_rcg2 blsp1_uart4_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -933,8 +600,8 @@ static struct clk_rcg2 blsp1_uart5_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart5_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -947,8 +614,8 @@ static struct clk_rcg2 blsp1_uart6_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart6_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -958,6 +625,11 @@ static const struct clk_parent_data gcc_
- { .hw = &gpll0.clkr.hw },
- };
-
-+static const struct parent_map gcc_xo_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+};
-+
- static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
-@@ -972,7 +644,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie0_axi_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -981,6 +653,18 @@ static const struct freq_tbl ftbl_pcie_a
- F(19200000, P_XO, 1, 0, 0),
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 2 },
-+ { P_SLEEP_CLK, 6 },
-+};
-+
- static struct clk_rcg2 pcie0_aux_clk_src = {
- .cmd_rcgr = 0x75024,
- .freq_tbl = ftbl_pcie_aux_clk_src,
-@@ -989,12 +673,22 @@ static struct clk_rcg2 pcie0_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie0_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
-+ { .name = "pcie20_phy0_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
-+ { P_PCIE20_PHY0_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux pcie0_pipe_clk_src = {
- .reg = 0x7501c,
- .shift = 8,
-@@ -1003,8 +697,8 @@ static struct clk_regmap_mux pcie0_pipe_
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "pcie0_pipe_clk_src",
-- .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1019,7 +713,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie1_axi_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1032,12 +726,22 @@ static struct clk_rcg2 pcie1_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie1_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
-+ { .name = "pcie20_phy1_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
-+ { P_PCIE20_PHY1_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux pcie1_pipe_clk_src = {
- .reg = 0x7601c,
- .shift = 8,
-@@ -1046,8 +750,8 @@ static struct clk_regmap_mux pcie1_pipe_
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "pcie1_pipe_clk_src",
-- .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1066,6 +770,20 @@ static const struct freq_tbl ftbl_sdcc_a
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll2.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL2, 2 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 sdcc1_apps_clk_src = {
- .cmd_rcgr = 0x42004,
- .freq_tbl = ftbl_sdcc_apps_clk_src,
-@@ -1074,8 +792,8 @@ static struct clk_rcg2 sdcc1_apps_clk_sr
- .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -1086,6 +804,20 @@ static const struct freq_tbl ftbl_sdcc_i
- F(308570000, P_GPLL6, 3.5, 0, 0),
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL6, 2 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 sdcc1_ice_core_clk_src = {
- .cmd_rcgr = 0x5d000,
- .freq_tbl = ftbl_sdcc_ice_core_clk_src,
-@@ -1094,8 +826,8 @@ static struct clk_rcg2 sdcc1_ice_core_cl
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_ice_core_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1108,8 +840,8 @@ static struct clk_rcg2 sdcc2_apps_clk_sr
- .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -1121,6 +853,18 @@ static const struct freq_tbl ftbl_usb_ma
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0_out_main_div2.hw },
-+ { .hw = &gpll0.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0_DIV2, 2 },
-+ { P_GPLL0, 1 },
-+};
-+
- static struct clk_rcg2 usb0_master_clk_src = {
- .cmd_rcgr = 0x3e00c,
- .freq_tbl = ftbl_usb_master_clk_src,
-@@ -1129,8 +873,8 @@ static struct clk_rcg2 usb0_master_clk_s
- .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb0_master_clk_src",
-- .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1148,8 +892,8 @@ static struct clk_rcg2 usb0_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb0_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1161,6 +905,20 @@ static const struct freq_tbl ftbl_usb_mo
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL6, 1 },
-+ { P_GPLL0, 3 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 usb0_mock_utmi_clk_src = {
- .cmd_rcgr = 0x3e020,
- .freq_tbl = ftbl_usb_mock_utmi_clk_src,
-@@ -1169,12 +927,22 @@ static struct clk_rcg2 usb0_mock_utmi_cl
- .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb0_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
-+ { .name = "usb3phy_0_cc_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
-+ { P_USB3PHY_0_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux usb0_pipe_clk_src = {
- .reg = 0x3e048,
- .shift = 8,
-@@ -1183,8 +951,8 @@ static struct clk_regmap_mux usb0_pipe_c
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "usb0_pipe_clk_src",
-- .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1199,8 +967,8 @@ static struct clk_rcg2 usb1_master_clk_s
- .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb1_master_clk_src",
-- .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1213,8 +981,8 @@ static struct clk_rcg2 usb1_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb1_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1227,12 +995,22 @@ static struct clk_rcg2 usb1_mock_utmi_cl
- .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb1_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
-+ { .name = "usb3phy_1_cc_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
-+ { P_USB3PHY_1_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux usb1_pipe_clk_src = {
- .reg = 0x3f048,
- .shift = 8,
-@@ -1241,8 +1019,8 @@ static struct clk_regmap_mux usb1_pipe_c
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "usb1_pipe_clk_src",
-- .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1256,8 +1034,9 @@ static struct clk_branch gcc_xo_clk_src
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_xo_clk_src",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-@@ -1271,9 +1050,8 @@ static struct clk_fixed_factor gcc_xo_di
- .div = 4,
- .hw.init = &(struct clk_init_data){
- .name = "gcc_xo_div4_clk_src",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1291,6 +1069,20 @@ static const struct freq_tbl ftbl_system
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL6, 2 },
-+ { P_GPLL0_DIV2, 3 },
-+};
-+
- static struct clk_rcg2 system_noc_bfdcd_clk_src = {
- .cmd_rcgr = 0x26004,
- .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
-@@ -1298,8 +1090,8 @@ static struct clk_rcg2 system_noc_bfdcd_
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_bfdcd_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- .flags = CLK_IS_CRITICAL,
- },
-@@ -1310,9 +1102,8 @@ static struct clk_fixed_factor system_no
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
-- .parent_names = (const char *[]){
-- "system_noc_bfdcd_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &system_noc_bfdcd_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1333,7 +1124,7 @@ static struct clk_rcg2 nss_ce_clk_src =
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ce_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1344,6 +1135,20 @@ static const struct freq_tbl ftbl_nss_no
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "bias_pll_nss_noc_clk" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll2.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
-+ { P_XO, 0 },
-+ { P_BIAS_PLL_NSS_NOC, 1 },
-+ { P_GPLL0, 2 },
-+ { P_GPLL2, 3 },
-+};
-+
- static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
- .cmd_rcgr = 0x68088,
- .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
-@@ -1351,8 +1156,8 @@ static struct clk_rcg2 nss_noc_bfdcd_clk
- .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_noc_bfdcd_clk_src",
-- .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1362,9 +1167,8 @@ static struct clk_fixed_factor nss_noc_c
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "nss_noc_clk_src",
-- .parent_names = (const char *[]){
-- "nss_noc_bfdcd_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_bfdcd_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1377,6 +1181,18 @@ static const struct freq_tbl ftbl_nss_cr
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &nss_crypto_pll.clkr.hw },
-+ { .hw = &gpll0.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_NSS_CRYPTO_PLL, 1 },
-+ { P_GPLL0, 2 },
-+};
-+
- static struct clk_rcg2 nss_crypto_clk_src = {
- .cmd_rcgr = 0x68144,
- .freq_tbl = ftbl_nss_crypto_clk_src,
-@@ -1385,8 +1201,8 @@ static struct clk_rcg2 nss_crypto_clk_sr
- .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_crypto_clk_src",
-- .parent_names = gcc_xo_nss_crypto_pll_gpll0,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_nss_crypto_pll_gpll0,
-+ .num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1400,6 +1216,24 @@ static const struct freq_tbl ftbl_nss_ub
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll2.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
-+ { P_XO, 0 },
-+ { P_UBI32_PLL, 1 },
-+ { P_GPLL0, 2 },
-+ { P_GPLL2, 3 },
-+ { P_GPLL4, 4 },
-+ { P_GPLL6, 5 },
-+};
-+
- static struct clk_rcg2 nss_ubi0_clk_src = {
- .cmd_rcgr = 0x68104,
- .freq_tbl = ftbl_nss_ubi_clk_src,
-@@ -1407,8 +1241,8 @@ static struct clk_rcg2 nss_ubi0_clk_src
- .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ubi0_clk_src",
-- .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-- .num_parents = 6,
-+ .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-+ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
- .ops = &clk_rcg2_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1421,9 +1255,8 @@ static struct clk_regmap_div nss_ubi0_di
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_ubi0_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_ubi0_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi0_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1438,8 +1271,8 @@ static struct clk_rcg2 nss_ubi1_clk_src
- .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ubi1_clk_src",
-- .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-- .num_parents = 6,
-+ .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-+ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
- .ops = &clk_rcg2_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1452,9 +1285,8 @@ static struct clk_regmap_div nss_ubi1_di
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_ubi1_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_ubi1_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi1_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1468,6 +1300,16 @@ static const struct freq_tbl ftbl_ubi_mp
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0_DIV2, 1 },
-+};
-+
- static struct clk_rcg2 ubi_mpt_clk_src = {
- .cmd_rcgr = 0x68090,
- .freq_tbl = ftbl_ubi_mpt_clk_src,
-@@ -1475,8 +1317,8 @@ static struct clk_rcg2 ubi_mpt_clk_src =
- .parent_map = gcc_xo_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ubi_mpt_clk_src",
-- .parent_names = gcc_xo_gpll0_out_main_div2,
-- .num_parents = 2,
-+ .parent_data = gcc_xo_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1487,6 +1329,18 @@ static const struct freq_tbl ftbl_nss_im
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL4, 2 },
-+};
-+
- static struct clk_rcg2 nss_imem_clk_src = {
- .cmd_rcgr = 0x68158,
- .freq_tbl = ftbl_nss_imem_clk_src,
-@@ -1494,8 +1348,8 @@ static struct clk_rcg2 nss_imem_clk_src
- .parent_map = gcc_xo_gpll0_gpll4_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_imem_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1506,6 +1360,24 @@ static const struct freq_tbl ftbl_nss_pp
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "bias_pll_cc_clk" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+ { .hw = &nss_crypto_pll.clkr.hw },
-+ { .hw = &ubi32_pll.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
-+ { P_XO, 0 },
-+ { P_BIAS_PLL, 1 },
-+ { P_GPLL0, 2 },
-+ { P_GPLL4, 3 },
-+ { P_NSS_CRYPTO_PLL, 4 },
-+ { P_UBI32_PLL, 5 },
-+};
-+
- static struct clk_rcg2 nss_ppe_clk_src = {
- .cmd_rcgr = 0x68080,
- .freq_tbl = ftbl_nss_ppe_clk_src,
-@@ -1513,8 +1385,8 @@ static struct clk_rcg2 nss_ppe_clk_src =
- .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ppe_clk_src",
-- .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
-- .num_parents = 6,
-+ .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
-+ .num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1524,9 +1396,8 @@ static struct clk_fixed_factor nss_ppe_c
- .div = 4,
- .hw.init = &(struct clk_init_data){
- .name = "nss_ppe_cdiv_clk_src",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1540,6 +1411,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_RX, 1 },
-+ { P_UNIPHY0_TX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port1_rx_clk_src = {
- .cmd_rcgr = 0x68020,
- .freq_tbl = ftbl_nss_port1_rx_clk_src,
-@@ -1547,8 +1434,8 @@ static struct clk_rcg2 nss_port1_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port1_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1560,9 +1447,8 @@ static struct clk_regmap_div nss_port1_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port1_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port1_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1577,6 +1463,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_TX, 1 },
-+ { P_UNIPHY0_RX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port1_tx_clk_src = {
- .cmd_rcgr = 0x68028,
- .freq_tbl = ftbl_nss_port1_tx_clk_src,
-@@ -1584,8 +1486,8 @@ static struct clk_rcg2 nss_port1_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port1_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1597,9 +1499,8 @@ static struct clk_regmap_div nss_port1_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port1_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port1_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1614,8 +1515,8 @@ static struct clk_rcg2 nss_port2_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port2_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1627,9 +1528,8 @@ static struct clk_regmap_div nss_port2_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port2_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port2_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1644,8 +1544,8 @@ static struct clk_rcg2 nss_port2_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port2_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1657,9 +1557,8 @@ static struct clk_regmap_div nss_port2_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port2_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port2_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1674,8 +1573,8 @@ static struct clk_rcg2 nss_port3_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port3_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1687,9 +1586,8 @@ static struct clk_regmap_div nss_port3_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port3_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port3_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1704,8 +1602,8 @@ static struct clk_rcg2 nss_port3_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port3_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1717,9 +1615,8 @@ static struct clk_regmap_div nss_port3_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port3_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port3_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1734,8 +1631,8 @@ static struct clk_rcg2 nss_port4_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port4_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1747,9 +1644,8 @@ static struct clk_regmap_div nss_port4_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port4_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port4_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1764,8 +1660,8 @@ static struct clk_rcg2 nss_port4_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port4_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1777,9 +1673,8 @@ static struct clk_regmap_div nss_port4_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port4_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port4_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1799,6 +1694,27 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .name = "uniphy1_gcc_rx_clk" },
-+ { .name = "uniphy1_gcc_tx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map
-+gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_RX, 1 },
-+ { P_UNIPHY0_TX, 2 },
-+ { P_UNIPHY1_RX, 3 },
-+ { P_UNIPHY1_TX, 4 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port5_rx_clk_src = {
- .cmd_rcgr = 0x68060,
- .freq_tbl = ftbl_nss_port5_rx_clk_src,
-@@ -1806,8 +1722,8 @@ static struct clk_rcg2 nss_port5_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port5_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
-- .num_parents = 7,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1819,9 +1735,8 @@ static struct clk_regmap_div nss_port5_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port5_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1841,6 +1756,27 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .name = "uniphy1_gcc_tx_clk" },
-+ { .name = "uniphy1_gcc_rx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map
-+gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_TX, 1 },
-+ { P_UNIPHY0_RX, 2 },
-+ { P_UNIPHY1_TX, 3 },
-+ { P_UNIPHY1_RX, 4 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port5_tx_clk_src = {
- .cmd_rcgr = 0x68068,
- .freq_tbl = ftbl_nss_port5_tx_clk_src,
-@@ -1848,8 +1784,8 @@ static struct clk_rcg2 nss_port5_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port5_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
-- .num_parents = 7,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1861,9 +1797,8 @@ static struct clk_regmap_div nss_port5_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port5_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1883,6 +1818,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy2_gcc_rx_clk" },
-+ { .name = "uniphy2_gcc_tx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY2_RX, 1 },
-+ { P_UNIPHY2_TX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port6_rx_clk_src = {
- .cmd_rcgr = 0x68070,
- .freq_tbl = ftbl_nss_port6_rx_clk_src,
-@@ -1890,8 +1841,8 @@ static struct clk_rcg2 nss_port6_rx_clk_
- .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port6_rx_clk_src",
-- .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1903,9 +1854,8 @@ static struct clk_regmap_div nss_port6_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port6_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port6_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1925,6 +1875,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy2_gcc_tx_clk" },
-+ { .name = "uniphy2_gcc_rx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY2_TX, 1 },
-+ { P_UNIPHY2_RX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port6_tx_clk_src = {
- .cmd_rcgr = 0x68078,
- .freq_tbl = ftbl_nss_port6_tx_clk_src,
-@@ -1932,8 +1898,8 @@ static struct clk_rcg2 nss_port6_tx_clk_
- .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port6_tx_clk_src",
-- .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1945,9 +1911,8 @@ static struct clk_regmap_div nss_port6_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port6_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port6_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1970,8 +1935,8 @@ static struct clk_rcg2 crypto_clk_src =
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "crypto_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1981,6 +1946,22 @@ static struct freq_tbl ftbl_gp_clk_src[]
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL6, 2 },
-+ { P_GPLL0_DIV2, 4 },
-+ { P_SLEEP_CLK, 6 },
-+};
-+
- static struct clk_rcg2 gp1_clk_src = {
- .cmd_rcgr = 0x08004,
- .freq_tbl = ftbl_gp_clk_src,
-@@ -1989,8 +1970,8 @@ static struct clk_rcg2 gp1_clk_src = {
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -2003,8 +1984,8 @@ static struct clk_rcg2 gp2_clk_src = {
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -2017,8 +1998,8 @@ static struct clk_rcg2 gp3_clk_src = {
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -2030,9 +2011,8 @@ static struct clk_branch gcc_blsp1_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2047,9 +2027,8 @@ static struct clk_branch gcc_blsp1_qup1_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup1_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2064,9 +2043,8 @@ static struct clk_branch gcc_blsp1_qup1_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup1_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2081,9 +2059,8 @@ static struct clk_branch gcc_blsp1_qup2_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup2_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2098,9 +2075,8 @@ static struct clk_branch gcc_blsp1_qup2_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup2_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2115,9 +2091,8 @@ static struct clk_branch gcc_blsp1_qup3_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup3_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2132,9 +2107,8 @@ static struct clk_branch gcc_blsp1_qup3_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup3_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2149,9 +2123,8 @@ static struct clk_branch gcc_blsp1_qup4_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup4_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2166,9 +2139,8 @@ static struct clk_branch gcc_blsp1_qup4_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup4_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2183,9 +2155,8 @@ static struct clk_branch gcc_blsp1_qup5_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup5_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2200,9 +2171,8 @@ static struct clk_branch gcc_blsp1_qup5_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup5_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2217,9 +2187,8 @@ static struct clk_branch gcc_blsp1_qup6_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup6_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2234,9 +2203,8 @@ static struct clk_branch gcc_blsp1_qup6_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup6_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2251,9 +2219,8 @@ static struct clk_branch gcc_blsp1_uart1
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart1_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart1_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart1_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2268,9 +2235,8 @@ static struct clk_branch gcc_blsp1_uart2
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart2_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart2_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart2_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2285,9 +2251,8 @@ static struct clk_branch gcc_blsp1_uart3
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart3_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart3_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart3_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2302,9 +2267,8 @@ static struct clk_branch gcc_blsp1_uart4
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart4_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart4_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart4_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2319,9 +2283,8 @@ static struct clk_branch gcc_blsp1_uart5
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart5_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart5_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart5_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2336,9 +2299,8 @@ static struct clk_branch gcc_blsp1_uart6
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart6_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart6_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart6_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2354,9 +2316,8 @@ static struct clk_branch gcc_prng_ahb_cl
- .enable_mask = BIT(8),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2371,9 +2332,8 @@ static struct clk_branch gcc_qpic_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qpic_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2388,9 +2348,8 @@ static struct clk_branch gcc_qpic_clk =
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qpic_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2405,9 +2364,8 @@ static struct clk_branch gcc_pcie0_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2422,9 +2380,8 @@ static struct clk_branch gcc_pcie0_aux_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_aux_clk",
-- .parent_names = (const char *[]){
-- "pcie0_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2439,9 +2396,8 @@ static struct clk_branch gcc_pcie0_axi_m
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_axi_m_clk",
-- .parent_names = (const char *[]){
-- "pcie0_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2456,9 +2412,8 @@ static struct clk_branch gcc_pcie0_axi_s
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_axi_s_clk",
-- .parent_names = (const char *[]){
-- "pcie0_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2474,9 +2429,8 @@ static struct clk_branch gcc_pcie0_pipe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_pipe_clk",
-- .parent_names = (const char *[]){
-- "pcie0_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2491,9 +2445,8 @@ static struct clk_branch gcc_sys_noc_pci
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_pcie0_axi_clk",
-- .parent_names = (const char *[]){
-- "pcie0_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2508,9 +2461,8 @@ static struct clk_branch gcc_pcie1_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2525,9 +2477,8 @@ static struct clk_branch gcc_pcie1_aux_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_aux_clk",
-- .parent_names = (const char *[]){
-- "pcie1_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2542,9 +2493,8 @@ static struct clk_branch gcc_pcie1_axi_m
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_axi_m_clk",
-- .parent_names = (const char *[]){
-- "pcie1_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2559,9 +2509,8 @@ static struct clk_branch gcc_pcie1_axi_s
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_axi_s_clk",
-- .parent_names = (const char *[]){
-- "pcie1_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2577,9 +2526,8 @@ static struct clk_branch gcc_pcie1_pipe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_pipe_clk",
-- .parent_names = (const char *[]){
-- "pcie1_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2594,9 +2542,8 @@ static struct clk_branch gcc_sys_noc_pci
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_pcie1_axi_clk",
-- .parent_names = (const char *[]){
-- "pcie1_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2611,9 +2558,8 @@ static struct clk_branch gcc_usb0_aux_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_aux_clk",
-- .parent_names = (const char *[]){
-- "usb0_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2628,9 +2574,8 @@ static struct clk_branch gcc_sys_noc_usb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_usb0_axi_clk",
-- .parent_names = (const char *[]){
-- "usb0_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2645,9 +2590,8 @@ static struct clk_branch gcc_usb0_master
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_master_clk",
-- .parent_names = (const char *[]){
-- "usb0_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2662,9 +2606,8 @@ static struct clk_branch gcc_usb0_mock_u
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_mock_utmi_clk",
-- .parent_names = (const char *[]){
-- "usb0_mock_utmi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_mock_utmi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2679,9 +2622,8 @@ static struct clk_branch gcc_usb0_phy_cf
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_phy_cfg_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2697,9 +2639,8 @@ static struct clk_branch gcc_usb0_pipe_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_pipe_clk",
-- .parent_names = (const char *[]){
-- "usb0_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2714,9 +2655,8 @@ static struct clk_branch gcc_usb0_sleep_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_sleep_clk",
-- .parent_names = (const char *[]){
-- "gcc_sleep_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_sleep_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2731,9 +2671,8 @@ static struct clk_branch gcc_usb1_aux_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_aux_clk",
-- .parent_names = (const char *[]){
-- "usb1_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2748,9 +2687,8 @@ static struct clk_branch gcc_sys_noc_usb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_usb1_axi_clk",
-- .parent_names = (const char *[]){
-- "usb1_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2765,9 +2703,8 @@ static struct clk_branch gcc_usb1_master
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_master_clk",
-- .parent_names = (const char *[]){
-- "usb1_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2782,9 +2719,8 @@ static struct clk_branch gcc_usb1_mock_u
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_mock_utmi_clk",
-- .parent_names = (const char *[]){
-- "usb1_mock_utmi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_mock_utmi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2799,9 +2735,8 @@ static struct clk_branch gcc_usb1_phy_cf
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_phy_cfg_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2817,9 +2752,8 @@ static struct clk_branch gcc_usb1_pipe_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_pipe_clk",
-- .parent_names = (const char *[]){
-- "usb1_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2834,9 +2768,8 @@ static struct clk_branch gcc_usb1_sleep_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_sleep_clk",
-- .parent_names = (const char *[]){
-- "gcc_sleep_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_sleep_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2851,9 +2784,8 @@ static struct clk_branch gcc_sdcc1_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2868,9 +2800,8 @@ static struct clk_branch gcc_sdcc1_apps_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_apps_clk",
-- .parent_names = (const char *[]){
-- "sdcc1_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &sdcc1_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2885,9 +2816,8 @@ static struct clk_branch gcc_sdcc1_ice_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ice_core_clk",
-- .parent_names = (const char *[]){
-- "sdcc1_ice_core_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &sdcc1_ice_core_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2902,9 +2832,8 @@ static struct clk_branch gcc_sdcc2_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2919,9 +2848,8 @@ static struct clk_branch gcc_sdcc2_apps_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_apps_clk",
-- .parent_names = (const char *[]){
-- "sdcc2_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &sdcc2_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2936,9 +2864,8 @@ static struct clk_branch gcc_mem_noc_nss
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mem_noc_nss_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2953,9 +2880,8 @@ static struct clk_branch gcc_nss_ce_apb_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ce_apb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2970,9 +2896,8 @@ static struct clk_branch gcc_nss_ce_axi_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ce_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2987,9 +2912,8 @@ static struct clk_branch gcc_nss_cfg_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_cfg_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3004,9 +2928,8 @@ static struct clk_branch gcc_nss_crypto_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_crypto_clk",
-- .parent_names = (const char *[]){
-- "nss_crypto_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_crypto_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3021,9 +2944,8 @@ static struct clk_branch gcc_nss_csr_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_csr_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3038,9 +2960,8 @@ static struct clk_branch gcc_nss_edma_cf
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_edma_cfg_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3055,9 +2976,8 @@ static struct clk_branch gcc_nss_edma_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_edma_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3072,9 +2992,8 @@ static struct clk_branch gcc_nss_imem_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_imem_clk",
-- .parent_names = (const char *[]){
-- "nss_imem_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_imem_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3089,9 +3008,8 @@ static struct clk_branch gcc_nss_noc_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_noc_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3106,9 +3024,8 @@ static struct clk_branch gcc_nss_ppe_btq
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_btq_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3123,9 +3040,8 @@ static struct clk_branch gcc_nss_ppe_cfg
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_cfg_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3140,9 +3056,8 @@ static struct clk_branch gcc_nss_ppe_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3157,9 +3072,8 @@ static struct clk_branch gcc_nss_ppe_ipe
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_ipe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3174,9 +3088,8 @@ static struct clk_branch gcc_nss_ptp_ref
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ptp_ref_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_cdiv_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_cdiv_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3192,9 +3105,8 @@ static struct clk_branch gcc_crypto_ppe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_ppe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3209,9 +3121,8 @@ static struct clk_branch gcc_nssnoc_ce_a
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ce_apb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3226,9 +3137,8 @@ static struct clk_branch gcc_nssnoc_ce_a
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ce_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3243,9 +3153,8 @@ static struct clk_branch gcc_nssnoc_cryp
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_crypto_clk",
-- .parent_names = (const char *[]){
-- "nss_crypto_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_crypto_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3260,9 +3169,8 @@ static struct clk_branch gcc_nssnoc_ppe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ppe_cfg_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3277,9 +3185,8 @@ static struct clk_branch gcc_nssnoc_ppe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ppe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3294,9 +3201,8 @@ static struct clk_branch gcc_nssnoc_qosg
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_qosgen_ref_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3311,9 +3217,8 @@ static struct clk_branch gcc_nssnoc_snoc
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_snoc_clk",
-- .parent_names = (const char *[]){
-- "system_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &system_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3328,9 +3233,8 @@ static struct clk_branch gcc_nssnoc_time
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_timeout_ref_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_div4_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_div4_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3345,9 +3249,8 @@ static struct clk_branch gcc_nssnoc_ubi0
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ubi0_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3362,9 +3265,8 @@ static struct clk_branch gcc_nssnoc_ubi1
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ubi1_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3380,9 +3282,8 @@ static struct clk_branch gcc_ubi0_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3398,9 +3299,8 @@ static struct clk_branch gcc_ubi0_axi_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3416,9 +3316,8 @@ static struct clk_branch gcc_ubi0_nc_axi
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_nc_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3434,9 +3333,8 @@ static struct clk_branch gcc_ubi0_core_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_core_clk",
-- .parent_names = (const char *[]){
-- "nss_ubi0_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi0_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3452,9 +3350,8 @@ static struct clk_branch gcc_ubi0_mpt_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_mpt_clk",
-- .parent_names = (const char *[]){
-- "ubi_mpt_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &ubi_mpt_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3470,9 +3367,8 @@ static struct clk_branch gcc_ubi1_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3488,9 +3384,8 @@ static struct clk_branch gcc_ubi1_axi_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3506,9 +3401,8 @@ static struct clk_branch gcc_ubi1_nc_axi
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_nc_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3524,9 +3418,8 @@ static struct clk_branch gcc_ubi1_core_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_core_clk",
-- .parent_names = (const char *[]){
-- "nss_ubi1_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi1_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3542,9 +3435,8 @@ static struct clk_branch gcc_ubi1_mpt_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_mpt_clk",
-- .parent_names = (const char *[]){
-- "ubi_mpt_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &ubi_mpt_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3559,9 +3451,8 @@ static struct clk_branch gcc_cmn_12gpll_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_cmn_12gpll_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3576,9 +3467,8 @@ static struct clk_branch gcc_cmn_12gpll_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_cmn_12gpll_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3593,9 +3483,8 @@ static struct clk_branch gcc_mdio_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdio_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3610,9 +3499,8 @@ static struct clk_branch gcc_uniphy0_ahb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3627,9 +3515,8 @@ static struct clk_branch gcc_uniphy0_sys
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3644,9 +3531,8 @@ static struct clk_branch gcc_uniphy1_ahb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3661,9 +3547,8 @@ static struct clk_branch gcc_uniphy1_sys
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3678,9 +3563,8 @@ static struct clk_branch gcc_uniphy2_ahb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3695,9 +3579,8 @@ static struct clk_branch gcc_uniphy2_sys
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3712,9 +3595,8 @@ static struct clk_branch gcc_nss_port1_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port1_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3729,9 +3611,8 @@ static struct clk_branch gcc_nss_port1_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port1_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3746,9 +3627,8 @@ static struct clk_branch gcc_nss_port2_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port2_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3763,9 +3643,8 @@ static struct clk_branch gcc_nss_port2_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port2_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3780,9 +3659,8 @@ static struct clk_branch gcc_nss_port3_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port3_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3797,9 +3675,8 @@ static struct clk_branch gcc_nss_port3_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port3_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3814,9 +3691,8 @@ static struct clk_branch gcc_nss_port4_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port4_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3831,9 +3707,8 @@ static struct clk_branch gcc_nss_port4_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port4_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3848,9 +3723,8 @@ static struct clk_branch gcc_nss_port5_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port5_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3865,9 +3739,8 @@ static struct clk_branch gcc_nss_port5_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port5_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3882,9 +3755,8 @@ static struct clk_branch gcc_nss_port6_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port6_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3899,9 +3771,8 @@ static struct clk_branch gcc_nss_port6_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port6_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3916,9 +3787,8 @@ static struct clk_branch gcc_port1_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port1_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3933,9 +3803,8 @@ static struct clk_branch gcc_port2_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port2_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3950,9 +3819,8 @@ static struct clk_branch gcc_port3_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port3_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3967,9 +3835,8 @@ static struct clk_branch gcc_port4_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port4_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3984,9 +3851,8 @@ static struct clk_branch gcc_port5_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port5_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4001,9 +3867,8 @@ static struct clk_branch gcc_port6_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port6_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4018,9 +3883,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port1_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4035,9 +3899,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port1_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4052,9 +3915,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port2_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4069,9 +3931,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port2_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4086,9 +3947,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port3_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4103,9 +3963,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port3_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4120,9 +3979,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port4_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4137,9 +3995,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port4_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4154,9 +4011,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port5_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4171,9 +4027,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port5_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4188,9 +4043,8 @@ static struct clk_branch gcc_uniphy1_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_port5_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4205,9 +4059,8 @@ static struct clk_branch gcc_uniphy1_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_port5_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4222,9 +4075,8 @@ static struct clk_branch gcc_uniphy2_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_port6_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4239,9 +4091,8 @@ static struct clk_branch gcc_uniphy2_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_port6_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4257,9 +4108,8 @@ static struct clk_branch gcc_crypto_ahb_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4275,9 +4125,8 @@ static struct clk_branch gcc_crypto_axi_
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_axi_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4293,9 +4142,8 @@ static struct clk_branch gcc_crypto_clk
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_clk",
-- .parent_names = (const char *[]){
-- "crypto_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &crypto_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4310,9 +4158,8 @@ static struct clk_branch gcc_gp1_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp1_clk",
-- .parent_names = (const char *[]){
-- "gp1_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gp1_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4327,9 +4174,8 @@ static struct clk_branch gcc_gp2_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp2_clk",
-- .parent_names = (const char *[]){
-- "gp2_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gp2_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4344,9 +4190,8 @@ static struct clk_branch gcc_gp3_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp3_clk",
-- .parent_names = (const char *[]){
-- "gp3_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gp3_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4368,7 +4213,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie0_rchng_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
+++ /dev/null
-From 813ba3e427671ba3ff35c825087b03f0ad91cf02 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 7 Nov 2022 14:28:59 +0100
-Subject: [PATCH] clk: qcom: reset: support resetting multiple bits
-
-This patch adds the support for giving the complete bitmask
-in reset structure and reset operation will use this bitmask
-for all reset operations.
-
-Currently, reset structure only takes a single bit for each reset
-and then calculates the bitmask by using the BIT() macro.
-
-However, this is not sufficient anymore for newer SoC-s like IPQ8074,
-IPQ6018 and more, since their networking resets require multiple bits
-to be asserted in order to properly reset the HW block completely.
-
-So, in order to allow asserting multiple bits add "bitmask" field to
-qcom_reset_map, and then use that bitmask value if its populated in the
-driver, if its not populated, then we just default to existing behaviour
-and calculate the bitmask on the fly.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221107132901.489240-1-robimarko@gmail.com
----
- drivers/clk/qcom/reset.c | 4 ++--
- drivers/clk/qcom/reset.h | 1 +
- 2 files changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/qcom/reset.c
-+++ b/drivers/clk/qcom/reset.c
-@@ -30,7 +30,7 @@ qcom_reset_assert(struct reset_controlle
-
- rst = to_qcom_reset_controller(rcdev);
- map = &rst->reset_map[id];
-- mask = BIT(map->bit);
-+ mask = map->bitmask ? map->bitmask : BIT(map->bit);
-
- return regmap_update_bits(rst->regmap, map->reg, mask, mask);
- }
-@@ -44,7 +44,7 @@ qcom_reset_deassert(struct reset_control
-
- rst = to_qcom_reset_controller(rcdev);
- map = &rst->reset_map[id];
-- mask = BIT(map->bit);
-+ mask = map->bitmask ? map->bitmask : BIT(map->bit);
-
- return regmap_update_bits(rst->regmap, map->reg, mask, 0);
- }
---- a/drivers/clk/qcom/reset.h
-+++ b/drivers/clk/qcom/reset.h
-@@ -12,6 +12,7 @@ struct qcom_reset_map {
- unsigned int reg;
- u8 bit;
- u8 udelay;
-+ u32 bitmask;
- };
-
- struct regmap;
+++ /dev/null
-From e78a40eb24187a8b4f9b89e2181f674df39c2013 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 7 Nov 2022 14:29:00 +0100
-Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add missing networking
- resets
-
-Add bindings for the missing networking resets found in IPQ8074 GCC.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221107132901.489240-2-robimarko@gmail.com
----
- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-@@ -367,6 +367,20 @@
- #define GCC_PCIE1_AHB_ARES 129
- #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
- #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
-+#define GCC_PPE_FULL_RESET 132
-+#define GCC_UNIPHY0_SOFT_RESET 133
-+#define GCC_UNIPHY0_XPCS_RESET 134
-+#define GCC_UNIPHY1_SOFT_RESET 135
-+#define GCC_UNIPHY1_XPCS_RESET 136
-+#define GCC_UNIPHY2_SOFT_RESET 137
-+#define GCC_UNIPHY2_XPCS_RESET 138
-+#define GCC_EDMA_HW_RESET 139
-+#define GCC_NSSPORT1_RESET 140
-+#define GCC_NSSPORT2_RESET 141
-+#define GCC_NSSPORT3_RESET 142
-+#define GCC_NSSPORT4_RESET 143
-+#define GCC_NSSPORT5_RESET 144
-+#define GCC_NSSPORT6_RESET 145
-
- #define USB0_GDSC 0
- #define USB1_GDSC 1
+++ /dev/null
-From da76cb63d04dc22ed32123b8c1d084c006d67bfb Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 7 Nov 2022 14:29:01 +0100
-Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets
-
-Downstream QCA 5.4 kernel defines networking resets which are not present
-in the mainline kernel but are required for the networking drivers.
-
-So, port the downstream resets and avoid using magic values for mask,
-construct mask for resets which require multiple bits to be set/cleared.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
----
- drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -4671,6 +4671,20 @@ static const struct qcom_reset_map gcc_i
- [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
- [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
- [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
-+ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
-+ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
-+ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
-+ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
-+ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
-+ [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
-+ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
-+ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
-+ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
-+ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
-+ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
-+ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
-+ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
-+ [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
- };
-
- static struct gdsc *gcc_ipq8074_gdscs[] = {
+++ /dev/null
-From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:46:55 +0100
-Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
-
-It appears that having only .name populated in parent_data for clocks
-which are only globally searchable currently will not work as the clk core
-won't copy that name if there is no .fw_name present as well.
-
-So, populate .fw_name for all parent clocks in parent_data.
-
-Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
-
-Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
----
- drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
- 1 file changed, 26 insertions(+), 26 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
- };
-
- static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
-- { .name = "pcie20_phy0_pipe_clk" },
-+ { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
- { .fw_name = "xo", .name = "xo" },
- };
-
-@@ -733,7 +733,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
- };
-
- static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
-- { .name = "pcie20_phy1_pipe_clk" },
-+ { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
- { .fw_name = "xo", .name = "xo" },
- };
-
-@@ -1137,7 +1137,7 @@ static const struct freq_tbl ftbl_nss_no
-
- static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "bias_pll_nss_noc_clk" },
-+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll2.clkr.hw },
- };
-@@ -1362,7 +1362,7 @@ static const struct freq_tbl ftbl_nss_pp
-
- static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll4.clkr.hw },
- { .hw = &nss_crypto_pll.clkr.hw },
-@@ -1413,10 +1413,10 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy0_gcc_rx_clk" },
-- { .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-@@ -1465,10 +1465,10 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy0_gcc_tx_clk" },
-- { .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-@@ -1696,12 +1696,12 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy0_gcc_rx_clk" },
-- { .name = "uniphy0_gcc_tx_clk" },
-- { .name = "uniphy1_gcc_rx_clk" },
-- { .name = "uniphy1_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
-+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map
-@@ -1758,12 +1758,12 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy0_gcc_tx_clk" },
-- { .name = "uniphy0_gcc_rx_clk" },
-- { .name = "uniphy1_gcc_tx_clk" },
-- { .name = "uniphy1_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
-+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map
-@@ -1820,10 +1820,10 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy2_gcc_rx_clk" },
-- { .name = "uniphy2_gcc_tx_clk" },
-+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
-+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
-@@ -1877,10 +1877,10 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy2_gcc_tx_clk" },
-- { .name = "uniphy2_gcc_rx_clk" },
-+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
-+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
+++ /dev/null
-From 9033c3c86ea0dd35bd2ab957317573b755967298 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 30 Oct 2022 18:57:03 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: pass XO and sleep clocks to GCC
-
-Pass XO and sleep clocks to the GCC controller so it does not have to
-find them by matching globaly by name.
-
-If not passed directly, driver maintains backwards compatibility by then
-falling back to global lookup.
-
-Since we are here, set cell numbers in decimal instead of hex.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -361,9 +361,11 @@
- gcc: gcc@1800000 {
- compatible = "qcom,gcc-ipq8074";
- reg = <0x01800000 0x80000>;
-- #clock-cells = <0x1>;
-+ clocks = <&xo>, <&sleep_clk>;
-+ clock-names = "xo", "sleep_clk";
-+ #clock-cells = <1>;
- #power-domain-cells = <1>;
-- #reset-cells = <0x1>;
-+ #reset-cells = <1>;
- };
-
- tcsr_mutex: hwlock@1905000 {
+++ /dev/null
-From fb76b808f8628215afebaf0f8af0bde635302590 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:18:14 +0200
-Subject: [PATCH] arm64: dts: qcom: add PMP8074 DTSI
-
-PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is
-controlled via SPMI.
-
-Add DTSI for it providing GPIO, regulator, RTC and VADC support.
-
-RTC is disabled by default as there is no built-in battery so it will
-loose time unless board vendor added a battery, so make it optional.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++
- 1 file changed, 125 insertions(+)
- create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
-@@ -0,0 +1,125 @@
-+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
-+
-+#include <dt-bindings/spmi/spmi.h>
-+#include <dt-bindings/iio/qcom,spmi-vadc.h>
-+
-+&spmi_bus {
-+ pmic@0 {
-+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
-+ reg = <0x0 SPMI_USID>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pmp8074_adc: adc@3100 {
-+ compatible = "qcom,spmi-adc-rev2";
-+ reg = <0x3100>;
-+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ #io-channel-cells = <1>;
-+
-+ ref-gnd@0 {
-+ reg = <ADC5_REF_GND>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ vref-1p25@1 {
-+ reg = <ADC5_1P25VREF>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ vref-vadc@2 {
-+ reg = <ADC5_VREF_VADC>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ pmic_die: die-temp@6 {
-+ reg = <ADC5_DIE_TEMP>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ xo_therm: xo-temp@76 {
-+ reg = <ADC5_XO_THERM_100K_PU>;
-+ qcom,ratiometric;
-+ qcom,hw-settle-time = <200>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ pa_therm1: thermistor1@77 {
-+ reg = <ADC5_AMUX_THM1_100K_PU>;
-+ qcom,ratiometric;
-+ qcom,hw-settle-time = <200>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ pa_therm2: thermistor2@78 {
-+ reg = <ADC5_AMUX_THM2_100K_PU>;
-+ qcom,ratiometric;
-+ qcom,hw-settle-time = <200>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ pa_therm3: thermistor3@79 {
-+ reg = <ADC5_AMUX_THM3_100K_PU>;
-+ qcom,ratiometric;
-+ qcom,hw-settle-time = <200>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ vph-pwr@131 {
-+ reg = <ADC5_VPH_PWR>;
-+ qcom,pre-scaling = <1 3>;
-+ };
-+ };
-+
-+ pmp8074_rtc: rtc@6000 {
-+ compatible = "qcom,pm8941-rtc";
-+ reg = <0x6000>;
-+ reg-names = "rtc", "alarm";
-+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
-+ allow-set-time;
-+ status = "disabled";
-+ };
-+
-+ pmp8074_gpios: gpio@c000 {
-+ compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
-+ reg = <0xc000>;
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ gpio-ranges = <&pmp8074_gpios 0 0 12>;
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+ };
-+
-+ pmic@1 {
-+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
-+ reg = <0x1 SPMI_USID>;
-+
-+ regulators {
-+ compatible = "qcom,pmp8074-regulators";
-+
-+ s3: s3 {
-+ regulator-name = "vdd_s3";
-+ regulator-min-microvolt = <592000>;
-+ regulator-max-microvolt = <1064000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ s4: s4 {
-+ regulator-name = "vdd_s4";
-+ regulator-min-microvolt = <712000>;
-+ regulator-max-microvolt = <992000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ l11: l11 {
-+ regulator-name = "l11";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+ };
-+ };
-+};
+++ /dev/null
-From 2c394cfc1779886048feca7dc7f4075da5f6328c Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:18:15 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply
-
-Since now we have control over the PMP8074 PMIC providing various system
-voltages including L11 which provides the SDIO/eMMC I/O voltage set it as
-the SDHCI VQMMC supply.
-
-This allows SDHCI controller to switch to 1.8V I/O mode and support high
-speed modes like HS200 and HS400.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -3,6 +3,7 @@
- /* Copyright (c) 2017, The Linux Foundation. All rights reserved.
- */
- #include "ipq8074.dtsi"
-+#include "pmp8074.dtsi"
-
- / {
- model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
-@@ -84,6 +85,7 @@
-
- &sdhc_1 {
- status = "okay";
-+ vqmmc-supply = <&l11>;
- };
-
- &qusb_phy_0 {
+++ /dev/null
-From 82ceb86227b1fc15c76d5fc691b2bf425f1a63b3 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 7 Nov 2022 10:29:30 +0100
-Subject: [PATCH] arm64: dts: qcom: hk01: use GPIO flags for tlmm
-
-Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of
-harcoding the cell value.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221107092930.33325-3-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -4,6 +4,7 @@
- */
- #include "ipq8074.dtsi"
- #include "pmp8074.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-
- / {
- model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
-@@ -52,12 +53,12 @@
-
- &pcie0 {
- status = "okay";
-- perst-gpios = <&tlmm 61 0x1>;
-+ perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- };
-
- &pcie1 {
- status = "okay";
-- perst-gpios = <&tlmm 58 0x1>;
-+ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- };
-
- &pcie_qmp0 {
+++ /dev/null
-From 1b1c1423ca3e740984aa883512a72c4ea08fbe28 Mon Sep 17 00:00:00 2001
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-Date: Mon, 7 Nov 2022 15:55:17 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074-*: Fix up comments
-
-Make sure all multiline C-style commends begin with just '/*' with
-the comment text starting on a new line.
-
-Also, fix up some whitespace within comments.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221107145522.6706-8-konrad.dybcio@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 3 ++-
- arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts | 3 ++-
- arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts | 3 ++-
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++------
- 4 files changed, 12 insertions(+), 9 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -1,6 +1,7 @@
- // SPDX-License-Identifier: GPL-2.0-only
- /dts-v1/;
--/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
- */
- #include "ipq8074.dtsi"
- #include "pmp8074.dtsi"
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
-@@ -1,5 +1,6 @@
- // SPDX-License-Identifier: GPL-2.0-only
--/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
-+/*
-+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
- */
- /dts-v1/;
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
-@@ -1,6 +1,7 @@
- // SPDX-License-Identifier: GPL-2.0-only
- /dts-v1/;
--/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
-+/*
-+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
- */
- #include "ipq8074-hk10.dtsi"
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -129,10 +129,10 @@
- status = "disabled";
-
- usb1_ssphy: phy@58200 {
-- reg = <0x00058200 0x130>, /* Tx */
-+ reg = <0x00058200 0x130>, /* Tx */
- <0x00058400 0x200>, /* Rx */
-- <0x00058800 0x1f8>, /* PCS */
-- <0x00058600 0x044>; /* PCS misc*/
-+ <0x00058800 0x1f8>, /* PCS */
-+ <0x00058600 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB1_PIPE_CLK>;
-@@ -172,10 +172,10 @@
- status = "disabled";
-
- usb0_ssphy: phy@78200 {
-- reg = <0x00078200 0x130>, /* Tx */
-+ reg = <0x00078200 0x130>, /* Tx */
- <0x00078400 0x200>, /* Rx */
-- <0x00078800 0x1f8>, /* PCS */
-- <0x00078600 0x044>; /* PCS misc*/
-+ <0x00078800 0x1f8>, /* PCS */
-+ <0x00078600 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
+++ /dev/null
-From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Tue, 8 Nov 2022 15:23:57 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
- DT schema
-
-DT schema expects TLMM pin configuration nodes to be named with
-'-state' suffix and their optional children with '-pins' suffix.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -318,35 +318,35 @@
- interrupt-controller;
- #interrupt-cells = <0x2>;
-
-- serial_4_pins: serial4-pinmux {
-+ serial_4_pins: serial4-state {
- pins = "gpio23", "gpio24";
- function = "blsp4_uart1";
- drive-strength = <8>;
- bias-disable;
- };
-
-- i2c_0_pins: i2c-0-pinmux {
-+ i2c_0_pins: i2c-0-state {
- pins = "gpio42", "gpio43";
- function = "blsp1_i2c";
- drive-strength = <8>;
- bias-disable;
- };
-
-- spi_0_pins: spi-0-pins {
-+ spi_0_pins: spi-0-state {
- pins = "gpio38", "gpio39", "gpio40", "gpio41";
- function = "blsp0_spi";
- drive-strength = <8>;
- bias-disable;
- };
-
-- hsuart_pins: hsuart-pins {
-+ hsuart_pins: hsuart-state {
- pins = "gpio46", "gpio47", "gpio48", "gpio49";
- function = "blsp2_uart";
- drive-strength = <8>;
- bias-disable;
- };
-
-- qpic_pins: qpic-pins {
-+ qpic_pins: qpic-state {
- pins = "gpio1", "gpio3", "gpio4",
- "gpio5", "gpio6", "gpio7",
- "gpio8", "gpio10", "gpio11",
+++ /dev/null
-From 77faa07c185c969e742cbb3e6aa487a11b0b616c Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Tue, 30 Aug 2022 09:57:42 +0300
-Subject: [PATCH] dt-bindings: arm: qcom: document qcom,msm-id and
- qcom,board-id
-
-The top level qcom,msm-id and qcom,board-id properties are utilized by
-bootloaders on Qualcomm MSM platforms to determine which device tree
-should be used and passed to the kernel.
-
-The commit b32e592d3c28 ("devicetree: bindings: Document qcom board
-compatible format") from 2015 was a consensus during discussion about
-upstreaming qcom,msm-id and qcom,board-id fields. There are however still
-problems with that consensus:
-1. It was reached 7 years ago but it turned out its implementation did
- not reach all possible products.
-
-2. Initially additional tool (dtbTool) was needed for parsing these
- fields to create a QCDT image consisting of multiple DTBs, later the
- bootloaders were improved and they use these qcom,msm-id and
- qcom,board-id properties directly.
-
-3. Extracting relevant information from the board compatible requires
- this additional tool (dtbTool), which makes the build process more
- complicated and not easily reproducible (DTBs are modified after the
- kernel build).
-
-4. Some versions of Qualcomm bootloaders expect these properties even
- when booting with a single DTB. The community is stuck with these
- bootloaders thus they require properties in the DTBs.
-
-Since several upstreamed Qualcomm SoC-based boards require these
-properties to properly boot and the properties are reportedly used by
-bootloaders, document them along with the bindings header with constants
-used by: bootloader, some DTS and socinfo driver.
-
-Link: https://lore.kernel.org/r/a3c932d1-a102-ce18-deea-18cbbd05ecab@linaro.org/
-Co-developed-by: Kumar Gala <galak@codeaurora.org>
-Signed-off-by: Kumar Gala <galak@codeaurora.org>
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220830065744.161163-2-krzysztof.kozlowski@linaro.org
----
- include/dt-bindings/arm/qcom,ids.h | 155 +++++++++++++++++++++++++++++
- 1 file changed, 155 insertions(+)
- create mode 100644 include/dt-bindings/arm/qcom,ids.h
-
---- /dev/null
-+++ b/include/dt-bindings/arm/qcom,ids.h
-@@ -0,0 +1,155 @@
-+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
-+/*
-+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2022 Linaro Ltd
-+ * Author: Krzysztof Kozlowski <krzk@kernel.org> based on previous work of Kumar Gala.
-+ */
-+#ifndef _DT_BINDINGS_ARM_QCOM_IDS_H
-+#define _DT_BINDINGS_ARM_QCOM_IDS_H
-+
-+/*
-+ * The MSM chipset and hardware revision used by Qualcomm bootloaders, DTS for
-+ * older chipsets (qcom,msm-id) and in socinfo driver:
-+ */
-+#define QCOM_ID_MSM8960 87
-+#define QCOM_ID_APQ8064 109
-+#define QCOM_ID_MSM8660A 122
-+#define QCOM_ID_MSM8260A 123
-+#define QCOM_ID_APQ8060A 124
-+#define QCOM_ID_MSM8974 126
-+#define QCOM_ID_MPQ8064 130
-+#define QCOM_ID_MSM8960AB 138
-+#define QCOM_ID_APQ8060AB 139
-+#define QCOM_ID_MSM8260AB 140
-+#define QCOM_ID_MSM8660AB 141
-+#define QCOM_ID_MSM8626 145
-+#define QCOM_ID_MSM8610 147
-+#define QCOM_ID_APQ8064AB 153
-+#define QCOM_ID_MSM8226 158
-+#define QCOM_ID_MSM8526 159
-+#define QCOM_ID_MSM8110 161
-+#define QCOM_ID_MSM8210 162
-+#define QCOM_ID_MSM8810 163
-+#define QCOM_ID_MSM8212 164
-+#define QCOM_ID_MSM8612 165
-+#define QCOM_ID_MSM8112 166
-+#define QCOM_ID_MSM8225Q 168
-+#define QCOM_ID_MSM8625Q 169
-+#define QCOM_ID_MSM8125Q 170
-+#define QCOM_ID_APQ8064AA 172
-+#define QCOM_ID_APQ8084 178
-+#define QCOM_ID_APQ8074 184
-+#define QCOM_ID_MSM8274 185
-+#define QCOM_ID_MSM8674 186
-+#define QCOM_ID_MSM8974PRO_AC 194
-+#define QCOM_ID_MSM8126 198
-+#define QCOM_ID_APQ8026 199
-+#define QCOM_ID_MSM8926 200
-+#define QCOM_ID_MSM8326 205
-+#define QCOM_ID_MSM8916 206
-+#define QCOM_ID_MSM8994 207
-+#define QCOM_ID_APQ8074PRO_AA 208
-+#define QCOM_ID_APQ8074PRO_AB 209
-+#define QCOM_ID_APQ8074PRO_AC 210
-+#define QCOM_ID_MSM8274PRO_AA 211
-+#define QCOM_ID_MSM8274PRO_AB 212
-+#define QCOM_ID_MSM8274PRO_AC 213
-+#define QCOM_ID_MSM8674PRO_AA 214
-+#define QCOM_ID_MSM8674PRO_AB 215
-+#define QCOM_ID_MSM8674PRO_AC 216
-+#define QCOM_ID_MSM8974PRO_AA 217
-+#define QCOM_ID_MSM8974PRO_AB 218
-+#define QCOM_ID_APQ8028 219
-+#define QCOM_ID_MSM8128 220
-+#define QCOM_ID_MSM8228 221
-+#define QCOM_ID_MSM8528 222
-+#define QCOM_ID_MSM8628 223
-+#define QCOM_ID_MSM8928 224
-+#define QCOM_ID_MSM8510 225
-+#define QCOM_ID_MSM8512 226
-+#define QCOM_ID_MSM8936 233
-+#define QCOM_ID_MSM8939 239
-+#define QCOM_ID_APQ8036 240
-+#define QCOM_ID_APQ8039 241
-+#define QCOM_ID_MSM8996 246
-+#define QCOM_ID_APQ8016 247
-+#define QCOM_ID_MSM8216 248
-+#define QCOM_ID_MSM8116 249
-+#define QCOM_ID_MSM8616 250
-+#define QCOM_ID_MSM8992 251
-+#define QCOM_ID_APQ8094 253
-+#define QCOM_ID_MDM9607 290
-+#define QCOM_ID_APQ8096 291
-+#define QCOM_ID_MSM8998 292
-+#define QCOM_ID_MSM8953 293
-+#define QCOM_ID_MDM8207 296
-+#define QCOM_ID_MDM9207 297
-+#define QCOM_ID_MDM9307 298
-+#define QCOM_ID_MDM9628 299
-+#define QCOM_ID_APQ8053 304
-+#define QCOM_ID_MSM8996SG 305
-+#define QCOM_ID_MSM8996AU 310
-+#define QCOM_ID_APQ8096AU 311
-+#define QCOM_ID_APQ8096SG 312
-+#define QCOM_ID_SDM660 317
-+#define QCOM_ID_SDM630 318
-+#define QCOM_ID_APQ8098 319
-+#define QCOM_ID_SDM845 321
-+#define QCOM_ID_MDM9206 322
-+#define QCOM_ID_IPQ8074 323
-+#define QCOM_ID_SDA660 324
-+#define QCOM_ID_SDM658 325
-+#define QCOM_ID_SDA658 326
-+#define QCOM_ID_SDA630 327
-+#define QCOM_ID_SDM450 338
-+#define QCOM_ID_SDA845 341
-+#define QCOM_ID_IPQ8072 342
-+#define QCOM_ID_IPQ8076 343
-+#define QCOM_ID_IPQ8078 344
-+#define QCOM_ID_SDM636 345
-+#define QCOM_ID_SDA636 346
-+#define QCOM_ID_SDM632 349
-+#define QCOM_ID_SDA632 350
-+#define QCOM_ID_SDA450 351
-+#define QCOM_ID_SM8250 356
-+#define QCOM_ID_IPQ8070 375
-+#define QCOM_ID_IPQ8071 376
-+#define QCOM_ID_IPQ8072A 389
-+#define QCOM_ID_IPQ8074A 390
-+#define QCOM_ID_IPQ8076A 391
-+#define QCOM_ID_IPQ8078A 392
-+#define QCOM_ID_SM6125 394
-+#define QCOM_ID_IPQ8070A 395
-+#define QCOM_ID_IPQ8071A 396
-+#define QCOM_ID_IPQ6018 402
-+#define QCOM_ID_IPQ6028 403
-+#define QCOM_ID_IPQ6000 421
-+#define QCOM_ID_IPQ6010 422
-+#define QCOM_ID_SC7180 425
-+#define QCOM_ID_SM6350 434
-+#define QCOM_ID_SM8350 439
-+#define QCOM_ID_SC8280XP 449
-+#define QCOM_ID_IPQ6005 453
-+#define QCOM_ID_QRB5165 455
-+#define QCOM_ID_SM8450 457
-+#define QCOM_ID_SM7225 459
-+#define QCOM_ID_SA8295P 460
-+#define QCOM_ID_SA8540P 461
-+#define QCOM_ID_SM8450_2 480
-+#define QCOM_ID_SM8450_3 482
-+#define QCOM_ID_SC7280 487
-+#define QCOM_ID_SC7180P 495
-+#define QCOM_ID_SM6375 507
-+
-+/*
-+ * The board type and revision information, used by Qualcomm bootloaders and
-+ * DTS for older chipsets (qcom,board-id):
-+ */
-+#define QCOM_BOARD_ID(a, major, minor) \
-+ (((major & 0xff) << 16) | ((minor & 0xff) << 8) | QCOM_BOARD_ID_##a)
-+
-+#define QCOM_BOARD_ID_MTP 8
-+#define QCOM_BOARD_ID_DRAGONBOARD 10
-+#define QCOM_BOARD_ID_SBC 24
-+
-+#endif /* _DT_BINDINGS_ARM_QCOM_IDS_H */
+++ /dev/null
-From a4748d2850783d36f77ccf2b5fcc86ccf1800ef1 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:48:36 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed
-
-Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
-generation limit.
-This allows the generic DWC code to configure the link speed correctly.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -766,6 +766,7 @@
- linux,pci-domain = <1>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
-+ max-link-speed = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
-
+++ /dev/null
-From f356132229b18ceef5d5ef9103bbaa9bdeb84c8d Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 13 Jan 2023 17:44:47 +0100
-Subject: [PATCH] PCI: qcom: Add IPQ8074 Gen3 port support
-
-IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
-Add compatible for Gen3 port which uses the same controller as IPQ6018.
-
-Link: https://lore.kernel.org/r/20230113164449.906002-7-robimarko@gmail.com
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
----
- drivers/pci/controller/dwc/pcie-qcom.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -1745,6 +1745,7 @@ static const struct of_device_id qcom_pc
- { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
- { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
- { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
-+ { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
- { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
- { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
- { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
+++ /dev/null
-From 614d31c231c7707322b643f409eeb7e28adc7f8c Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 8 Jan 2023 13:36:28 +0100
-Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for usb3phy-s
-
-Having only .name populated in parent_data for clocks which are only
-globally searchable currently will not work as the clk core won't copy
-that name if there is no .fw_name present as well.
-
-So, populate .fw_name for usb3phy clocks in parent_data as they were
-missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
-
-Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/clk/qcom/gcc-ipq8074.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -934,7 +934,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
- };
-
- static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
-- { .name = "usb3phy_0_cc_pipe_clk" },
-+ { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
- { .fw_name = "xo", .name = "xo" },
- };
-
-@@ -1002,7 +1002,7 @@ static struct clk_rcg2 usb1_mock_utmi_cl
- };
-
- static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
-- { .name = "usb3phy_1_cc_pipe_clk" },
-+ { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
- { .fw_name = "xo", .name = "xo" },
- };
-
projects / openwrt / staging / stintel.git / commitdiff