drm/amd/powerplay: Add mode2 mode for GPU RESET in SMU

Renoir need to use mode2 mode to implement GPU RESET

Signed-off-by: chen gong <curry.gong@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 45da21dc2356c3aaf8e8de1ebaa3f89e1a47f35b..149de9277f8e96b19271be8e93c0e3efc87de28d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -321,6 +321,13 @@ struct mclock_latency_table {
        struct mclk_latency_entries  entries[MAX_REGULAR_DPM_NUM];
 };
 
+enum smu_reset_mode
+{
+    SMU_RESET_MODE_0,
+    SMU_RESET_MODE_1,
+    SMU_RESET_MODE_2,
+};
+
 enum smu_baco_state
 {
        SMU_BACO_STATE_ENTER = 0,
@@ -537,6 +544,7 @@ struct smu_funcs
        enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
        int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
        int (*baco_reset)(struct smu_context *smu);
+       int (*mode2_reset)(struct smu_context *smu);
        int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
 };
 
@@ -760,6 +768,8 @@ struct smu_funcs
        ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
 #define smu_baco_reset(smu) \
        ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
+#define smu_mode2_reset(smu) \
+       ((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0)
 #define smu_asic_set_performance_level(smu, level) \
        ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
 #define smu_dump_pptable(smu) \

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 24274c9bb87da167cc59af2697d7a09adc62566e..d9d9473755578e7e0c6e5714657b6d8c0f6c16d8 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -380,6 +380,9 @@ failed:
        return ret;
 }
 
+static int smu_v12_0_mode2_reset(struct smu_context *smu){
+       return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2);
+}
 static const struct smu_funcs smu_v12_0_funcs = {
        .check_fw_status = smu_v12_0_check_fw_status,
        .check_fw_version = smu_v12_0_check_fw_version,
@@ -394,6 +397,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
        .fini_smc_tables = smu_v12_0_fini_smc_tables,
        .populate_smc_tables = smu_v12_0_populate_smc_tables,
        .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+       .mode2_reset = smu_v12_0_mode2_reset,
 };
 
 void smu_v12_0_set_smu_funcs(struct smu_context *smu)