for (unit = 0; unit < MAX_DRIVES; ++unit) {
ide_drive_t *drive = &hwif->drives[unit];
- if (hwif->no_io_32bit)
+ if (hwif->host_flags & IDE_HFLAG_NO_IO_32BIT)
drive->no_io_32bit = 1;
else
drive->no_io_32bit = drive->id->dword_io ? 1 : 0;
drive->io_32bit = 1;
if (hwif->host_flags & IDE_HFLAG_UNMASK_IRQS)
drive->unmask = 1;
+ if (hwif->host_flags & IDE_HFLAG_NO_UNMASK_IRQS)
+ drive->no_unmask = 1;
if ((hwif->host_flags & IDE_HFLAG_NO_AUTOTUNE) == 0)
drive->autotune = 1;
}
static const struct ide_port_info dtc2278_port_info __initdata = {
.chipset = ide_dtc2278,
.host_flags = IDE_HFLAG_SERIALIZE |
+ IDE_HFLAG_NO_UNMASK_IRQS |
IDE_HFLAG_IO_32BIT |
+ /* disallow ->io_32bit changes */
+ IDE_HFLAG_NO_IO_32BIT |
IDE_HFLAG_NO_DMA |
IDE_HFLAG_NO_AUTOTUNE,
.pio_mask = ATA_PIO4,
#endif
local_irq_restore(flags);
- hwif->no_io_32bit = 1; /* disallow ->io_32bit changes */
hwif->set_pio_mode = &dtc2278_set_pio_mode;
- hwif->drives[0].no_unmask = 1;
- hwif->drives[1].no_unmask = 1;
-
- mate->no_io_32bit = 1;
- mate->drives[0].no_unmask = 1;
- mate->drives[1].no_unmask = 1;
ide_device_add(idx, &dtc2278_port_info);
static const struct ide_port_info au1xxx_port_info = {
.host_flags = IDE_HFLAG_POST_SET_MODE |
IDE_HFLAG_NO_DMA | /* no SFF-style DMA */
+ IDE_HFLAG_NO_IO_32BIT |
IDE_HFLAG_UNMASK_IRQS,
.pio_mask = ATA_PIO4,
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
hwif->select_data = 0; /* no chipset-specific code */
hwif->config_data = 0; /* no chipset-specific code */
- hwif->no_io_32bit = 1;
-
auide_hwif.hwif = hwif;
hwif->hwif_data = &auide_hwif;
} else {
if (hwif->mate)
hwif->mate->serialized = hwif->serialized = 1;
- hwif->drives[0].no_unmask = 1;
- hwif->drives[1].no_unmask = 1;
+ hwif->host_flags |= IDE_HFLAG_NO_UNMASK_IRQS;
printk(KERN_INFO "%s: serialized, disabled unmasking "
"(buggy RZ1000/RZ1001)\n", hwif->name);
}
unsigned reset : 1; /* reset after probe */
unsigned auto_poll : 1; /* supports nop auto-poll */
unsigned sg_mapped : 1; /* sg_table and sg_nents are ready */
- unsigned no_io_32bit : 1; /* 1 = can not do 32-bit IO ops */
unsigned mmio : 1; /* host uses MMIO */
struct device gendev;
IDE_HFLAG_NO_SET_MODE = (1 << 9),
/* trust BIOS for programming chipset/device for DMA */
IDE_HFLAG_TRUST_BIOS_FOR_DMA = (1 << 10),
- /* host uses VDMA */
+ /* host uses VDMA (tied with IDE_HFLAG_CS5520 for now) */
IDE_HFLAG_VDMA = (1 << 11),
/* ATAPI DMA is unsupported */
IDE_HFLAG_NO_ATAPI_DMA = (1 << 12),
IDE_HFLAG_NO_DMA = (1 << 14),
/* check if host is PCI IDE device before allowing DMA */
IDE_HFLAG_NO_AUTODMA = (1 << 15),
+ /* don't autotune PIO */
+ IDE_HFLAG_NO_AUTOTUNE = (1 << 16),
/* host is CS5510/CS5520 */
- IDE_HFLAG_CS5520 = (1 << 16),
+ IDE_HFLAG_CS5520 = IDE_HFLAG_VDMA,
/* no LBA48 */
IDE_HFLAG_NO_LBA48 = (1 << 17),
/* no LBA48 DMA */
IDE_HFLAG_CLEAR_SIMPLEX = (1 << 28),
/* DSC overlap is unsupported */
IDE_HFLAG_NO_DSC = (1 << 29),
- /* don't autotune PIO */
- IDE_HFLAG_NO_AUTOTUNE = (1 << 30),
+ /* never use 32-bit I/O ops */
+ IDE_HFLAG_NO_IO_32BIT = (1 << 30),
+ /* never unmask IRQs */
+ IDE_HFLAG_NO_UNMASK_IRQS = (1 << 31),
};
#ifdef CONFIG_BLK_DEV_OFFBOARD