mxs: mmc: Fix MMC reset on iMX23

This does the same reset mask as done in v3.7 Linux kernel code.
The block is properly configured for MMC operation that way.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 0c4cd54b79afe05d5c765583af7f5d7d8c986724..9d71202ef34bac3f203af0a33564cef37b2a6245 100644 (file)
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -334,11 +334,17 @@ static int mxsmmc_init(struct mmc *mmc)
        /* Reset SSP */
        mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
 
-       /* 8 bits word length in MMC mode */
-       clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
-               SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK |
-               SSP_CTRL1_DMA_ENABLE,
-               SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
+       /* Reconfigure the SSP block for MMC operation */
+       writel(SSP_CTRL1_SSP_MODE_SD_MMC |
+               SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
+               SSP_CTRL1_DMA_ENABLE |
+               SSP_CTRL1_POLARITY |
+               SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
+               SSP_CTRL1_DATA_CRC_IRQ_EN |
+               SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
+               SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
+               SSP_CTRL1_RESP_ERR_IRQ_EN,
+               &ssp_regs->hw_ssp_ctrl1_set);
 
        /* Set initial bit clock 400 KHz */
        mxs_set_ssp_busclock(priv->id, 400);