drm/amdgpu: refine the PTE encoding of PRT for navi10
authorJack Xiao <Jack.Xiao@amd.com>
Fri, 22 Feb 2019 07:34:00 +0000 (15:34 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 21 Jun 2019 02:35:29 +0000 (21:35 -0500)
Due to GCR change from navi10, the PTE encoding of PRT
needs change VSCTL = 01111 (was 0XX1X).

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

index 14f96476f3b86205a8b0c85ee68299edef5a15ce..1951f2abbdbc8174d16358b3b2e25124994af139 100644 (file)
@@ -1585,6 +1585,11 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
        if ((mapping->flags & AMDGPU_PTE_PRT) &&
            (adev->asic_type >= CHIP_VEGA10)) {
                flags |= AMDGPU_PTE_PRT;
+               if (adev->asic_type >= CHIP_NAVI10) {
+                       flags |= AMDGPU_PTE_SNOOPED;
+                       flags |= AMDGPU_PTE_LOG;
+                       flags |= AMDGPU_PTE_SYSTEM;
+               }
                flags &= ~AMDGPU_PTE_VALID;
        }
 
index 778eb13ab1b8f7049b13253b8eeb991a13afb84b..489a162ca6207775b7bdcc3408bb0d77911701b9 100644 (file)
@@ -67,6 +67,8 @@ struct amdgpu_bo_list_entry;
 /* PDE is handled as PTE for VEGA10 */
 #define AMDGPU_PDE_PTE         (1ULL << 54)
 
+#define AMDGPU_PTE_LOG          (1ULL << 55)
+
 /* PTE is handled as PDE for VEGA10 (Translate Further) */
 #define AMDGPU_PTE_TF          (1ULL << 56)